IN THE UNITED STATES DISTRICT COURT
`FOR THE DISTRICT OF DELAWARE
`
`MONTEREY RESEARCH, LLC,
`
`Plaintiff,
`
`vs.
`
`Civil Action No. 19-2090-NIQA-LAS
`
`NANYA TECHNOLOGY CORPORATION,
`NANYA TECHNOLOGY CORPORATION,
`U.S.A., and NANYA TECHNOLOGY
`CORPORATION DELAWARE,
`
`Defendants.
`
`NANYA TECHNOLOGY CORPORATION, NANYA TECHNOLOGY CORPORATION,
`U.S.A., AND NANYA TECHNOLOGY CORPORATION DELAWARE’S
`INITIAL INVALIDITY CONTENTIONS
`
`IPR2021-00167
`Nanya Technology Corp. v. Monterey Research, LLC
`Monterey Research LLC Exhibit 2007
`Ex. 2007, Page 1
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`

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`I.
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`TABLE OF CONTENTS
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`Page
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`INTRODUCTION ................................................................................................................ 1
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`II.
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`CLAIM CONSTRUCTION ................................................................................................. 6
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`III. ASSERTED PATENT AND CLAIMS ................................................................................ 6
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`IV. PRIORITY ............................................................................................................................ 8
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`V.
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`STATE OF THE ART .......................................................................................................... 8
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`VI.
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`INVALIDITY BASED ON THE PRIOR ART ................................................................. 13
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`VII.
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`INVALIDITY UNDER 35 U.S.C. § 112 ........................................................................... 76
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`VIII. ADDITIONAL INVALIDITY CONTENTIONS .............................................................. 83
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`i
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`Ex. 2007, Page 2
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`Appendices D1-D18
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`Appendices E1-E7
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`Appendices I1-I3
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`Appendices J1-J5
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`Appendices K1-K3
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`EXHIBITS AND APPENDICES
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`Invalidity claim charts for U.S. Patent No. 6,651,134
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`Invalidity claim charts for U.S. Patent No. 6,680,516
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`Invalidity claim charts for U.S. Patent No. 6,902,993
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`Invalidity claim charts for U.S. Patent No. 7,158,429
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`Invalidity claim charts for U.S. Patent No. 6,825,526
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`Appendices M1-M5
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`Invalidity claim charts for U.S. Patent No. 6,363,031
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`
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`Appendix OD
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`Appendix OE
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`Appendix OJ
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`Appendix AD
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`Appendix AE
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`Obviousness references for U.S. Patent No. 6,651,134
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`Obviousness references for U.S. Patent No. 6,680,516
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`Obviousness references for U.S. Patent No. 7,158,429
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`Applicant Admitted Prior Art for U.S. Patent No. 6,651,134
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`Applicant Admitted Prior Art for U.S. Patent No. 6,680,516
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`ii
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`Ex. 2007, Page 3
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`INTRODUCTION
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`Pursuant to the Court’s Scheduling Order (Dkt. 38) Nanya Technology Corporation, Nanya
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`Technology Corporation, U.S.A., and Nanya Technology Corporation Delaware (collectively
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`“Defendant” or “Nanya”) serves these Initial Invalidity Contentions on Plaintiff Monterey
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`Research, LLC (“Plaintiff” or “Monterey”) for U.S. Patent Nos. 6,651,134 (the “’134 Patent”),
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`6,680,516 (the “’516 Patent”), 6,902,993 (the “’993 Patent”), 7,158,429 (the “’429 Patent”),
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`6,825,526 (the “’526 Patent”), and 6,363,031 (the “’031 Patent”) (collectively the “Asserted
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`Patents”). These Invalidity Contentions are based on Defendant’s current knowledge of the
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`Asserted Patents and prior art, along with their understanding of Plaintiff’s infringement
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`allegations set forth in its November 20. 2020 Preliminary Disclosure of Asserted Claims and
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`Infringement Contentions (“Infringement Contentions”). Defendant’s investigation of the prior
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`art is ongoing, and Defendant expressly reserve the right to supplement these Invalidity
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`Contentions as the case proceeds.
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`Nothing in these Invalidity Contentions is intended, nor should be construed, as a waiver
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`of any claim construction argument or non-infringement position. Defendant’s statements herein
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`(including the accompanying claim charts) reflect Defendant’s present understanding of the
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`purported potential scope of the claims that Monterey appears to be advocating by way of its
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`Infringement Contentions. They are not to be seen as any acquiescence to Plaintiff’s interpretation
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`of any claims. Defendant disagrees that any such claim scope is proper. Defendant reserves the
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`right to supplement these contentions to address any supplemental infringement contentions. For
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`purposes of these Invalidity Contentions, Defendant identifies prior art references and provide
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`element-by-element claim charts based on the apparent constructions of the Asserted Claims
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`advanced by Monterey in its Infringement Contentions (which, for at least some limitations,
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`contradict the plain language of the claim).
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`27581295.1
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`Ex. 2007, Page 4
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`Nothing herein shall be interpreted as an admission that: (1) the Asserted Claims are
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`infringed by any of Defendant’s instrumentalities, (2) any particular feature or aspect of any of the
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`accused instrumentalities practices any limitation of the Asserted Claims, (3) there is 35 U.S.C. §
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`112 support for any limitation of the Asserted Claims, or (4) any of Monterey’s proposed or
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`implied constructions are supportable or proper.
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`Consistent with the Court’s Scheduling Order and the Federal Rules of Civil Procedure,
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`Defendant reserves the right to amend these Invalidity Contentions. The information and
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`documents that Defendant produces are provisional and subject to further revision as follows.
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`Defendant expressly reserves the right to amend its disclosures and document production
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`referenced herein should Monterey provide any information that it failed to provide in its
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`Infringement Contention disclosures or should Monterey amend its disclosures in any way,
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`whether explicitly or implicitly. Further, because discovery has only recently begun and because
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`Defendant have not yet completed its search for and analysis of relevant prior art, Defendant
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`reserves the right to amend the information provided herein. Such amendments include, for
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`example, identifying and relying on additional references, should Defendant’s further search and
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`analysis yield additional information or references. Defendant reserves the right to supplement
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`these contentions in light of any additional prior art of which Plaintiff is aware, and did not disclose
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`to Defendant in discovery. Also, Defendant anticipates issuing subpoenas to third parties believed
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`to have knowledge, documentation and/or corroborating evidence concerning some of the prior art
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`listed herein and/or additional prior art. These third parties include, but are not limited to, the
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`authors, employers of authors, inventors, assignees, or former or current employee of assignees,
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`of the references identified or the Asserted Patents. Defendant reserves the right to supplement
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`27581295.1
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`these contentions in light of any newly discovered information produced by these or other
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`companies from which Defendant may seek discovery.
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`Defendant also contends that the Asserted Claims are invalid in view of public knowledge
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`and uses and/or offers for sale or sales of products and services that are under 35 U.S.C. § 102(a)
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`and/or 35 U.S.C. § 102(b) and/or prior inventions made in this country by other inventors who had
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`not abandoned, suppressed, or concealed them under 35 U.S.C. § 102(g), and that anticipate or
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`render obvious the Asserted Claims. The following lists each system that is now known by
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`Defendant to constitute prior art under 35 U.S.C. §§ 102(a), (b), (f), and/or (g). Defendant
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`contends that the following descriptions and events are stated on information and belief, and are
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`supported by the information and documents that will be produced by Defendant and/or third
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`parties. As discovery is ongoing, Defendant continues to investigate these events.
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`Moreover, Defendant reserves the right to revise its contentions concerning the invalidity
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`of the claims of the Asserted Patents based upon the Court’s construction of the claims of the
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`Asserted Patents, any findings as to the priority dates of the Asserted Claims, and/or positions that
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`Monterey’s, Defendant’s, or any expert witness may take concerning claim interpretation,
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`infringement, and/or invalidity issues.
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`Prior art not included in this disclosure, whether known or not known to Defendant, may
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`become relevant. In particular, Defendant is currently unaware of the extent, if any, to which
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`Monterey will contend that limitations of the Asserted Claims are not disclosed in the prior art
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`identified by Defendant. To the extent that such an issue arises, Defendant reserves the right to
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`identify other references that would have made the addition of the allegedly missing limitation to
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`the disclosed device or method obvious or show that the allegedly missing limitation would have
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`been known or readily apparent to one of ordinary skill in the art at the time of the alleged invention
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`in light of the disclosure of the prior art at issue.
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`Defendant’s claim charts in Appendices D, E, I, J, K, M, OD, OE, OJ, AD, and AE cite to
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`or reference particular teachings and disclosures of the prior art as applied to features of the
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`Asserted Claims, but persons having ordinary skill in the art generally may view an item of prior
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`art in the context of other publications, literature, products, and understanding. As such, the cited
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`portions are only examples, and Defendant reserves the right to rely on uncited portions of the
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`prior-art references and on other publications and expert testimony as aids in understanding and
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`interpreting the cited portions, as providing context thereto, and as additional evidence that the
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`prior art discloses a claim limitation. Defendant further reserves the right to rely on uncited
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`portions of the prior-art references, other publications, and testimony to establish reasons for
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`combining certain cited references that render the Asserted Claims obvious.
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`The references discussed below and in the claim charts in Exhibits D, E, I, J, K, M, OD,
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`OE, OJ, AD, and AE may disclose the elements of the Asserted Claims explicitly and/or inherently,
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`and/or they may be relied upon to show the state of the art in the relevant time frame. The
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`suggested obviousness combinations are provided in the alternative to Defendant’s anticipation
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`contentions and are not to be construed to suggest that any reference included in the combinations
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`is not by itself anticipatory.
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`Depending on the Court’s construction of the claims of the Asserted Patent, and/or
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`positions that Monterey, Defendant, or any expert witness may take concerning claim
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`interpretation, infringement, and/or invalidity issues, one or more of the charted prior-art
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`references may be of greater or lesser relevance and different combinations of these references
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`may be implicated. Given this uncertainty, the charts may reflect alternative applications of the
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`prior art against the Asserted Claims.
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`Defendant’s Invalidity Contentions are based at least in part on the filing dates of the
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`applications resulting in the Asserted Patents. Defendant reserves the right to challenge these
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`priority dates and any priority date that Monterey later alleges is appropriate.
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`Defendant reserves the right to assert invalidity under 35 U.S.C. §§ 101, 102(c), (d), or (f)
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`to the extent that discovery or further investigation yield information forming the basis for such
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`claims. Defendant reserves the right to assert that the Asserted Patent is invalid under 35 U.S.C.
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`§ 102(f) in the event Defendant obtains evidence that the named inventors of the Asserted Patents
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`did not invent the subject matter claimed in the Asserted Patent. Should Defendant obtain such
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`evidence, it will provide the name of the person(s) from whom and the circumstances under which
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`the invention or any part of it was derived.
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`Defendant incorporates in these Invalidity Contentions, in full, all prior art references cited
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`in the Asserted Patents and their prosecution histories and any applicable post-grant proceedings,
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`including ex parte reexaminations and inter partes reviews (currently pending or otherwise),
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`including but not limited to:
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` Advanced Micro Devices, Inc. v. Monterey Research, LLC, IPR2020-00985 (U.S.
`Patent No. 6,651,134)
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` Qualcomm Incorporated v. Monterey Research, LLC, IPR2020-01492 (U.S. Patent
`No. 6,651,134)
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` Nanya Technology Corporation v. Monterey Research, LLC, IPR2021-00167 (U.S.
`Patent No. 6,651,134)
`
` STMicroelectronics, Inc. v. Monterey Research, LLC, IPR2021-00355 (U.S. Patent
`No. 6,651,134)
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` Qualcomm Incorporated v. Monterey Research, LLC, IPR2021-00119, (U.S. Patent
`No. 6,680,516)
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` Nanya Technology Corporation et al v. Monterey Research, LLC, IPR2021-00171,
`(U.S. Patent No. 6,680,516)
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`27581295.1
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` Nanya Technology Corporation et al v. Monterey Research, LLC, IPR2021-00170,
`(U.S. Patent No. 7,158,429)
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` Nanya Technology Corporation et al v. Monterey Research, LLC, IPR2021-00172,
`(U.S. Patent No. 6,902,993)
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`Nanya further incorporates in these Invalidity Contentions all invalidity theories expressed
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`by Defendants STMicroelectronics, Inc (“ST, Inc.”) and/or Qualcomm Incorporated, Qualcomm
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`Technologies, Inc., and Qualcomm CDMA Technologies Asia-Pacific PTE Ltd. (“Qualcomm”)
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`that are complementary and/or supplementary to those expressed by Nanya as if those theories
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`were set forth in full in Nanya’s contentions.
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`Defendant has provided disclosures and related documents pertaining only to the Asserted
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`Claims as identified by Monterey in its Infringement Contentions. Defendant reserves the right to
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`modify, amend, or supplement these Invalidity Contentions to show the invalidity of any additional
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`claims that the Court may allow Monterey to later assert. Defendant further reserves the right to
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`supplement its document production should it later find additional, responsive documents.
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`CLAIM CONSTRUCTION
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`To the extent that these Invalidity Contentions rely on or otherwise embody particular
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`constructions of terms or phrases in the Asserted Claims, Nanya is not proposing any such
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`constructions as proper constructions of those terms or phrases at this time. The Court established
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`separate deadlines for the parties’ proposed claim constructions, and Nanya will disclose its
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`proposed constructions accordingly. For purposes of these Invalidity Contentions, Nanya may
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`adopt alternative claim construction positions. In particular, portions of these Invalidity
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`Contentions, including the claim charts attached as Appendices, may be based on the underlying
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`claim constructions and/or interpretations as understood from Plaintiff’s Infringement Contentions
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`and/or Plaintiff’s proposed claim constructions. Nanya, however, does not concede that Plaintiff’s
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`apparent constructions are supportable or proper, and Nanya expressly reserves the right to contest
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`any such constructions.
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`In addition, to the extent that these Invalidity Contentions rely on or
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`otherwise embody a particular order in which the steps of method claims are performed, Nanya
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`does not necessarily propose that the method claims must be limited to such order, although Nanya
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`reserves the right to propose such an order. Moreover, nothing disclosed herein is an admission
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`or acknowledgement that any Accused Instrumentality, or any of Nanya’s other products or
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`services, infringes any of the Asserted Claims. Nanya reserves the right to supplement, modify,
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`or otherwise amend these Invalidity Contentions,
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`including based on the Court’s claim
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`construction ruling and/or arguments or positions taken during the claim construction process.
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`Throughout the attached Appendices, Nanya provides examples of where references
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`disclose subject matter recited in preambles, without regard to whether the preambles are properly
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`considered to be limitations of the Asserted Claims. Nanya reserves the right to argue, at the
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`appropriate stage of this case, that the preambles are or are not limitations. Moreover, Nanya
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`reserves the right to argue that certain claim elements of the Asserted Claims do not in fact limit
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`the scope of the Asserted Claims.
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`ASSERTED PATENT AND CLAIMS
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`Plaintiff asserted the following patents and claims in its Infiingement Contentions against
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`Defendant1 :
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`“ Asserted Patents
`- US. Patent No. 6,651,134
`I US. Patent No. 6,680,516
`I US. Patent No. 6,902,993
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`1-2, 4-10, 12-19
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`Asserted Claims
`1-5, 9, 13, 14, 16-18
`5-7, 10, 11
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`l The asserted patents and claims are collectively referenced throughout these contentions
`as the “Asserted Patents” and the “Asserted Claims.”
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`27581295.]
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`4.
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`5.
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`6.
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`U.S. Patent No. 7,158,429
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`1-3
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`U.S. Patent No. 6,825,526
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`1-3, 8-10, 15-17
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`U.S. Patent No. 6,363,031
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`1, 3, 6, 9-11, 13, 15, 17, 19, 20
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`For the purposes of these contentions, Nanya addresses only those claims specifically
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`asserted by Plaintiff. Defendant reserves the right to amend or supplement this disclosure as
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`necessary in light of any changes or amendments made, for any reason, to Plaintiff’s infringement
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`theories, Infringement Contentions, or asserted claims.
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`PRIORITY
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`To the extent Plaintiff alleges that any prior art relied on in these Invalidity Contentions
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`does not actually qualify as prior art to an Asserted Patent, Defendant reserve the right to rebut
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`those allegations (e.g., by demonstrating an earlier critical date for the challenged prior art and/or
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`a later priority date for the Asserted Patent and/or Asserted Claim).
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`STATE OF THE ART
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`Defendant sets forth a summary of its current understanding of the state of the art for
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`general subject matter of the Asserted Patents. Defendant expressly reserves the right to rely on
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`each of the prior art references discussed in Section 0 below with respect to each of the Asserted
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`Claims. Defendant also reserves the right to rely on the discussions of the state of the art and prior
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`art for the Asserted Patents and their file histories in explaining the state of the art and the
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`references’ correspondence with the claims of the Asserted Patent. Defendant further expressly
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`reserves the right to supplement its summary of the state of the art, including for example, by
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`information from any of the authors or named inventors on any of the prior art references, by
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`personnel familiar with systems based on any of the prior art, or by technical experts retained on
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`behalf of any party.
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`State of the Art for the Asserted Patents
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`i. U.S. Patent No. 6,651,134
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`The ’134 Patent was filed on February 14, 2000. It is directed to a system and method for
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`addressing a memory circuit with a burst of internal address signals that may be non-
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`interruptible. ’134 Patent at Abstract. An embodiment of the alleged invention is “configured to
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`transfer a fixed number of words of data with each access (e.g., read or write).” ’134 Patent at
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`2:28-30. An array of memory cells may be addressed by a “burst address counter” circuit that
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`receives an external address (ADDR_EXT), a clock (CLK), and control signals (e.g., LOAD, ADV)
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`and that outputs a burst of internal addresses ADDR_INT that access the memory cells. See id. at
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`2:31-46. When ADV is asserted, a fixed number of internal addresses (ADDR_INT) are generated
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`in response to the CLK signal. Id. at 3:19-24. “Once the circuit 102 has started generating the fixed
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`number of addresses, the circuit 102 will generally not stop until the fixed number of addresses
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`has been generated (e.g., a non-interruptible burst).” Id. at 3:25-29.
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`During prosecution, the patentee argued that the claims were patentable over the prior art
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`of record because the prior art did not disclose “the generation of a predetermined number of
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`internal address signals that is non-interruptible, as presently claimed.” ’134 File History at 63.
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`The patentee similarly distinguished other prior art by arguing that they did not teach a memory
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`burst that was non-interruptible. See id. at 115-17, 172. However, transferring data in non-
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`interruptible bursts to or from memory was already well known before the earliest priority date of
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`the ’134 Patent. For example, Wada discloses a memory system with a controller for reading and
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`writing data in burst mode and expressly teaches “when the advance signal ADV is brought High,
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`the address on the burst counter 84 is incremented every time a leading edge of the clock signal
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`CLK is encountered.” Wada at 2:55-61 (emphasis added). And as such, “[t]his allows the data
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`corresponding to the address Am to be output uninterrupted in burst mode.” Id. at 16:7-10. “This
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`constitution provides one advantage identical to that of the first embodiment, i.e., the ability to
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`execute data burst output in uninterrupted fashion.” Id. at 16:14-15.
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`Other prior art similarly establishes that such uninterrupted burst transfers were well known
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`in the art before the ’134 Patent was filed. For example, Barrett discloses “once burst transfer is
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`initialized the sending device transmits an uninterrupted stream of n data words over the
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`communications bus . . . .” Barrett at Abstract (emphasis added). Indeed, “[t]he essential feature
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`of burst communication is that the data transfer takes place at high speed and without interruption.”
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`Id. at 1:64-66 (emphasis added). In fact, Barrett teaches that “allowing a pause at any point defeats
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`the purpose of burst transmission, which is to send data as rapidly as possible in an uninterrupted
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`stream.” Id. at 2:39-41. Similarly, Fujioka discloses “Hence, when the burst length is equal to 4,
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`the 4-bit parallel data read from the sense amplifiers are converted into serial data, so that data can
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`be consecutively read and output without any interruption.” Fujioka at 7:66-8:4. And “[w]hen
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`the data read operation is repeatedly carried out, data can serially be read without any interruption
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`with the burst length BL equal to four because the read cycle of the random access is comparatively
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`short.” Id. at 3:56-60. Likewise, Schaefer discloses read-and-write burst operations “with auto-
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`precharge” in which “[t]he user is not allowed to issue another command until the precharged
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`time (tRP)” at the end of the operation “is completed.” Schaefer at 7:42-44. Thus, it was well
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`known by the time the ’134 Patent was filed to generate addresses for burst memory transfers
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`without any interruption, and the claims of the ’134 Patent are invalid as anticipated or obvious
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`over the prior art discussed herein and in Appendices D, OD, and AD.
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`ii. U.S. Patent No. 6,680,516
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`The ’516 Patent was filed on December 6, 2002, and is directed towards “gate stack” for a
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`transistor with a height designed to address a perceived “aspect ratio” concern. ’516 Patent at 1:14-
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`64. According to the ’516 Patent, if the gate stack is too large relative to the via width in a transistor
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`(i.e. aspect ratio), “then it may not be possible to properly fill the via with a conductor.” Id. at 5:2-
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`28. The ’516 Patent does not provide any new layer, material, or arrangement of layers for the
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`gate structure but instead proposes specific thickness ranges for each of a series of known layers
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`that result in a gate stack height that does not exceed 2700 angstroms. Id. 1:14-5:39. But the
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`“ongoing need to reduce the size of the elements within integrated circuits and semiconductor
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`structures,” was well-known in the field. Id. at 1:55-57.
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`For example, Huang provides a method of fabricating semiconductor devices used to from
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`a self-aligned contact (SAC) to a substrate for a metal oxide semiconductor field effect
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`(MOSFET).” Huang at 1:6-10. Huang explains that the use of SAC results in a structure that
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`“allows the amount of source and drain contact area to be reduced, thus allowing smaller devices
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`to be constructed, resulting in faster, as well as lower cost devices, to be realized.” Id. at 1:33-37.
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`Huang further discloses the same layers claimed in the ’516 Patent resulting in a gate stack height
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`that is less than 2700 angstroms. Id. at 5:27-47; Fig. 2D. As another example, the objective of
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`Ohiwa is to “provide a semiconductor device capable of increasing the etching selectivity and
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`reducing the aspect ratio of the contact hole arranged between multilayered elements, thereby
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`increasing the integration density, and the manufacturing method thereof.” Ohiwa at 2:54-59.
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`Ohiwa’s method includes “forming an interlayer insulating film on the protective insulating film;
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`forming an opening to be aligned with the gate electrode in a self-aligned manner by etching a part
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`of the interlayer insulating film and a part of the protective insulating film in order to expose the
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`surface of the substrate at the bottom of the opening, and forming a wiring layer electrically
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`connected to the exposed surface of the substrate.” Ohiwa at 3:25-40. See also Qualcomm
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`Incorporated v. Monterey Research, LLC, IPR2021-00119, Paper 1 at 1-3, 6-17 (PTAB Oct. 26,
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`2020); Nanya Technology Corporation et al v. Monterey Research, LLC, IPR2021-00171, Paper
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`1 at 7-9 (PTAB Nov. 4, 2020).
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`Thus, it was well known by the time the ’516 Patent was filed there was an “ongoing need
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`to reduce the size of the elements within integrated circuits and semiconductor structures,”
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`including any apparent concern of aspect ratio and contact fill, and the claims of the ’516 Patent
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`are invalid as anticipated or obvious over the prior art discussed herein and in Appendices E, OE,
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`and AE.
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`iii. U.S. Patent No. 6,902,993
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`The ‘993 Patent was filed on March 28, 2003. The ‘993 Patent is directed towards forming
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`a gate of a transistor by performing a “first thermal treatment on a silicon layer” and a “second
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`thermal treatment on the metal stack.” According to the ‘993 Patent, the resulting gate “exhibits
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`relatively low interface contact resistance between the silicon layer and the metal stack”. ’993
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`Patent at Abstract.
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`iv. U.S. Patent No. 7,158,429
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`The ‘429 Patent was filed on March 16, 2004, and claims priority to provisional application
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`60/457,750 filed on March 26, 2003. The ’429 Patent is directed towards a “system for read path
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`acceleration” in electronic circuits. The ‘429 Patent teaches a “first strobe reset circuit coupled to
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`a first local amplifier”, a “second strobe reset circuit coupled to a second local amplifier”, and a
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`“main amplifier” coupled to the output of the first and second local amplifiers. ’429 Patent at
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`Abstract. The ’429 patent claims a well-known solution to a well-known problem of transmitting
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`read path signals over long distances on a memory core integrated circuits. ‘429 Patent at 1:19-25.
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`The ’429 Patent confirms that local amplifiers, global read data lines, an output registers,
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`and an equalization circuits were well-known. During prosecution, the examiner rejected Claim 1
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`as unpatentable over U.S. Patent No. 6,542,424 to Endo et. al. ‘429 Prosecution History at 57-58.
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`The examiner reasoned that “[i]t would have been obvious to one having ordinary skill in the art
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`at the time of the invention to utilizing Endo et al.’s data output buffer without altering the
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`performing functional of the device for outputting data from the main amplifier.” Id. Applicant
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`amended Claim 1, adding an unrelated element “a main amplifier strobe coupled to each of the
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`plurality of local amplifiers.” Id. at 64-70.
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`v. U.S. Patent No. 6,825,526
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`The ‘526 Patent was filed on January 16, 2004. The ’526 Patent is directed towards a
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`“structure for increasing drive current in a memory array.” The ’526 Patent describes the
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`background art as “non-volatile memory arrays” including a number of pre-existing circuits as
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`“related art,” including “ead-only-memory (ROM), programmable-read-only memory (PROM),
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`erasable-programmable-read-only-memory (EPROM), and electrically-erasable-programmable-
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`read-only-memory (EEPROM) arrays.” ‘526 patent at 1:11-20.
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`According to the ’526 Patent, the invention “resolves the need in the art for a flash memory
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`array, such as a floating gate flash memory array, having increased drive current, where the
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`increased drive current is achieved without increasing the size of the flash memory array.” ‘526
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`Patent at 1:54-58.
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`vi. U.S. Patent No. 6,363,031
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`The ’031 Patent was filed on December 22, 2000 and claims priority to Application No.
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`09/433,822 filed November 3, 1999. The ‘031 Patent is directed towards “a circuit configured to
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`automatically generate a sleep signal upon detecting that one or more chip select signals has been
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`in a first state for a predetermined number of clock cycles.” ’031 Patent at Abstract.
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`INVALIDITY BASED ON THE PRIOR ART
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`The primary prior art references that Nanya relies on for each Asserted Patent are identified
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`in the sections below. The Appendices to these Invalidity Contentions contain claim charts for the
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`primary prior art references selected by Nanya, along with obviousness claim charts for other
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`invalidating prior art.2 Nanya’s proposed combinations of the primary prior art references are
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`separately identified throughout these Invalidity Contentions (including in Section 0, below). In
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`addition, reasons to combine each of the Primary References with each other or with other
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`secondary references are provided below in detail.
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`Nanya’s reliance on each prior art reference identified throughout these Invalidity
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`Contentions (whether primary references or obviousness references) includes the reference itself,
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`anything incorporated by the reference or described as relevant technology by the reference, any
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`system embodying the reference, and any testimony by those with knowledge of the reference,
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`such as named authors and inventors. All such documents and information shall be considered
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`one prior art reference to the extent they describe a single prior art system, technology or solution.
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`Moreover, while some prior art may be charted separately, Nanya reserves the right to show that
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`combinations of individual charts describe a portion of single prior art system or solution. To the
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`extent that Plaintiff argues that some limitation is not shown in the primary reference, Nanya
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`reserves the right to show that element would have been well known to one of ordinary skill in
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`view of other documents describing the same technology (e.g., the element was specified in
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`published textbooks), or was admitted prior art (APA) of the named inventor. Nanya reserves the
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`right to revise, amend, and/or supplement the information provided herein, including by
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`identifying and relying on additional references, based on developments in the case including,
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`without limitation, based on changes in the priority date of any Asserted Claim, newly discovered
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`prior art, depositions and document productions of prior art witnesses, claim construction
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`2 To the extent any of these charts cite a Figure or text related to a Figure, any
`corresponding text or Figure are incorporated by reference.
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`determinations, challenges by Plaintiff to the authenticity or content of the prior art and positions
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`taken by Plaintiff during the litigation. In particular, Nanya reserves the right to supplement these
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`Invalidity Contentions as discovery reveals further information about prior use and/or prior public
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`knowledge of products, methods, or systems that Nanya has reason to believe anticipate or render
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`obvious one or more asserted claims. Nanya further reserves the right to identify and rely on
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`additional prior art in Plaintiff’s possession, custody, or control that has not yet been produced or
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`identified to Nanya. For instance, as discussed above, Nanya anticipates seeking discovery from
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`several of the individuals and companies associated with the references below and reserves the
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`right to rely on such discovery and/or supplement these contentions to the extent that discovery
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`reveals additional facts and/or prior art bases. Discovery is on-going, and Nanya reserves the right
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`to