Paper No.
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`NANYA TECHNOLOGY CORPORATION,
`NANYA TECHNOLOGY CORPORATION, U.S.A., and
`NANYA TECHNOLOGY CORPORATION DELAWARE,
`Petitioners
`v.
`
`MONTEREY RESEARCH, LLC,
`Patent Owner.
`
`Patent No. 6,651,134
`Issue Date: November 18, 2003
`
`Title: MEMORY DEVICE WITH FIXED LENGTH NON INTERRUPTIBLE
`BURST
`
`Inter Partes Review No. Unassigned
`
`PETITION FOR INTER PARTES REVIEW
`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. § 42.100 ET. SEQ.
`
`

`

`Table of Contents
`
`Page
`
`I.
`
`II.
`III.
`
`IV.
`
`INTRODUCTION ........................................................................................ 1
`A.
`Notice of Each Real Party in Interest (37 C.F.R. § 42.8(b)(1)) ............ 1
`B.
`Notice of Related Matters (37 C.F.R. § 42.8(b)(2)) .............................. 2
`C.
`Notice of Lead and Backup Counsel (37 C.F.R. § 42.8(b)(3)) ............. 3
`D.
`Notice of Service Information (37 C.F.R. § 42.8(b)(4)) ....................... 3
`E.
`Payment of Fees .................................................................................... 4
`F.
`Grounds for Standing ............................................................................ 4
`G.
`The Grounds in This Petition Are Not Cumulative over the Grounds
`in IPR2020-00985 Or the Grounds in IPR2020-01492 ........................ 4
`STATEMENT OF PRECISE RELIEF REQUESTED ................................. 5
`THE ’134 PATENT PETITIONED FOR REVIEW .................................... 7
`A.
`Summary of the ’134 Patent .................................................................. 7
`B.
`Admitted Prior Art ................................................................................ 9
`C.
`Relevant Prosecution History of the ’134 Patent ................................ 13
`D.
`Person of Ordinary Skill in the Art ..................................................... 14
`E.
`Priority Date of ’134 Patent ................................................................ 14
`F.
`Claim Construction ............................................................................. 15
`STATEMENT OF HOW EACH CLAIM IS UNPATENTABLE BASED
`ON THE PRIOR ART ................................................................................ 15
`A.
`Ground 1: Anticipation by Zagar ........................................................ 15
`Independent Claim 1 .................................................................16
`Dependent Claim 2....................................................................21
`Dependent Claim 3....................................................................22
`Dependent Claim 5....................................................................22
`Dependent Claim 8....................................................................22
`Dependent Claim 9....................................................................23
`Dependent Claim 10 .................................................................23
`Dependent Claim 12 .................................................................24
`Dependent Claim 13 .................................................................25
`Dependent Claim 14 .................................................................25
`Independent Claim 16 ...............................................................26
`Independent Claim 17 ...............................................................28
`Dependent Claim 18 .................................................................29
`Dependent Claim 21 .................................................................29
`Ground 2: Obviousness over Zagar in View of Fujioka ..................... 30
`
`B.
`
`i
`
`

`

`Table of Contents (continued)
`
`Page
`Dependent Claim 2....................................................................32
`Dependent Claim 3....................................................................32
`Dependent Claim 4....................................................................33
`Dependent Claim 5....................................................................34
`Dependent Claim 6....................................................................35
`Dependent Claim 7....................................................................36
`Dependent Claim 19 .................................................................36
`Dependent Claim 20 .................................................................37
`Ground 3: Obviousness over Zagar in View of Lysinger ................... 37
`Dependent Claim 11 .................................................................39
`Dependent Claim 15 .................................................................39
`Ground 4: Anticipation by Takasugi ................................................... 40
`Independent Claim 1 .................................................................40
`Dependent Claim 2....................................................................46
`Dependent Claim 3....................................................................46
`Dependent Claim 4....................................................................47
`Dependent Claim 5....................................................................47
`Dependent Claim 11 .................................................................48
`Dependent Claim 12 .................................................................48
`Dependent Claim 13 .................................................................48
`Dependent Claim 15 .................................................................49
`Independent Claim 16 ...............................................................49
`Independent Claim 17 ...............................................................50
`Dependent Claim 18 .................................................................51
`Ground 5: Obviousness over Takasugi in View of Fujioka ................ 51
`Dependent Claim 6....................................................................52
`Dependent Claim 7....................................................................52
`Dependent Claim 14 .................................................................53
`Dependent Claim 19 .................................................................53
`Dependent Claim 20 .................................................................53
`Ground 6: Obviousness over Takasugi in View of Zagar ................... 53
`Dependent Claim 8....................................................................53
`Dependent Claim 9....................................................................54
`Dependent Claim 10 .................................................................54
`Dependent Claim 21 .................................................................55
`
`C.
`
`D.
`
`E.
`
`F.
`
`ii
`
`

`

`Table of Contents (continued)
`
`G.
`
`H.
`
`I.
`
`Page
`Ground 7: Anticipation by Wada ........................................................ 55
`Independent Claim 1 .................................................................62
`Dependent Claim 2....................................................................67
`Dependent Claim 3....................................................................68
`Dependent Claim 8....................................................................69
`Dependent Claim 12 .................................................................70
`Dependent Claim 13 .................................................................71
`Independent Claim 16 ...............................................................72
`Independent Claim 17 ...............................................................73
`Ground 8: Obviousness over Wada in View of Takasugi ................... 74
`Dependent Claim 4....................................................................74
`Dependent Claim 11 .................................................................74
`Dependent Claim 15 .................................................................74
`Ground 9: Obviousness over Wada in View of Zagar ........................ 75
`Dependent Claim 5....................................................................75
`Dependent Claim 9....................................................................75
`Dependent Claim 10 .................................................................75
`Dependent Claim 14 .................................................................76
`Dependent Claim 18 .................................................................76
`Dependent Claim 21 .................................................................76
`Ground 10: Obviousness over Wada in View of Zagar and Further in
`View of Fujioka ................................................................................... 77
`Dependent Claim 6....................................................................77
`Dependent Claim 7....................................................................77
`Dependent Claim 19 .................................................................77
`Dependent Claim 20 .................................................................77
`CONCLUSION ........................................................................................... 78
`
`J.
`
`V.
`
`iii
`
`

`

`Patent No. 6,651,134
`Petition for Inter Partes Review
`
`PETITIONERS’ EXHIBIT LIST
`
`Exhibit No.
`
`Description
`
`Ex.1001
`
`Ex.1002
`
`Ex.1003
`
`Ex.1004
`Ex.1005
`Ex.1006
`Ex.1007
`Ex.1008
`Ex.1009
`
`U.S. Patent No. 6,651,134 (“the ’134 patent”)
`Prosecution File History for U.S. Patent No. 6,651,134 (“the
`’134 patent prosecution history”)
`Expert Declaration of Dr. Erik Chmelar in support of Petition
`for IPR of the ’134 patent
`Curriculum Vitae of Dr. Erik Chmelar
`U.S. Patent No. 5,666,323 (“Zagar”)
`U.S. Patent No. 5,978,303 (“Takasugi”)
`U.S. Patent No. 6,115,280 (“Wada”)
`U.S. Patent No. 6,185,149 (“Fujioka”)
`U.S. Patent No. 5,784,331 (“Lysinger”)
`
`iv
`
`

`

`Patent No. 6,651,134
`Petition for Inter Partes Review
`
`I.
`
`INTRODUCTION
`This petition is for inter partes review of U.S. Patent No. 6,651,134 (Ex.1001,
`
`“the ’134 patent”) assigned to Monterey Research, LLC (“the Patent Owner”).
`
`Petitioners contend that there is a reasonable likelihood that one or more claims of
`
`the ’134 patent will be found unpatentable.
`
`The ’134 patent claims a well-known solution to a well-known problem of
`
`“burst” functionality wherein a memory device generates a number of internal
`
`addresses in response to a single external address. (Ex.1001, Abstract; 1:57-58.)
`
`Multiple prior art references discuss this problem in detail and propose the same or
`
`very similar solutions as the ’134 patent.
`
`A.
`
`Notice of Each Real Party in Interest (37 C.F.R. § 42.8(b)(1))
`
`The real parties in interest include the following:
`
` Nanya Technology Corporation (“NTC”), a corporation organized and
`
`existing under the laws of Taiwan, having a place of business at No. 98,
`
`Nanlin Road., Taishan District, New Taipei City 243, Taiwan (One of the
`
`Petitioners).
`
` Nanya Technology Corporation U.S.A., a wholly-owned subsidiary of
`
`NTC, having a place of business at 1735 Technology Drive, Suite 400, San
`
`Jose, California 95110 (One of the Petitioners).
`
` Nanya Technology Corporation Delaware, a corporation organized and
`
`1
`
`

`

`Patent No. 6,651,134
`Petition for Inter Partes Review
`
`existing under the laws of Delaware, having a place of business at 20
`
`Winter Sports Lane, Suite 105, Williston, Vermont 05945 (One of the
`
`Petitioners).
`
`B.
`
`Notice of Related Matters (37 C.F.R. § 42.8(b)(2))
`
`The related matters include the following:
`
` Cypress Semiconductor Corporation v. GSI Technology, Inc. 0-11-cv-
`
`00789 (D. Min. 2011), which involves the ’134 patent.
`
` Static Random Access Memories and Products Containing Same, ITC-
`
`337-TA-792 (I.T.C. 2011) (hereafter the “792 Investigation”), which
`
`involves the ’134 patent.
`
` Cypress Semiconductor Corporation v. GSI Technology, Inc. 3-13-cv-
`
`02013 (N.D. Cal. 2013), which involves the ’134 patent.
`
` Cypress Semiconductor Corporation v. GSI Technology, Inc. 3-13-cv-
`
`03757 (N.D. Cal. 2013), which involves the ’134 patent.
`
` Monterey Research, LLC v. Qualcomm Inc. et al., Civil Action No. 1:19-
`
`cv-02083 (D. Del. 2019), which involves the ’134 patent.
`
` Monterey Research, LLC v. Nanya Technology Corp. et al., Civil Action
`
`No. 1:19-cv-02090 (D. Del. 2019), which involves the ’134 patent.
`
` Monterey Research, LLC v. Advanced Micro Devices, Inc., Civil Action
`
`No. 1:19-cv-02149 (D. Del. 2019), which involves the ’134 patent.
`
`2
`
`

`

`Patent No. 6,651,134
`Petition for Inter Partes Review
`
` Monterey Research, LLC v. STMicroelectronics NV et al., Civil Action No.
`
`1:20-cv-00089 (D. Del. 2020), which involves the ’134 patent.
`
` Monterey Research, LLC v. Marvell Technology Group, Ltd. et al., Civil
`
`Action No. 1:20-cv-00158 (D. Del. 2020), which involves the ’134 patent.
`
` Marvell Semiconductor Inc. v. Monterey Research, LLC, Civil Action No.
`
`3:20-cv-03296 (N.D. Cal. 2020), which involves the ’134 patent.
`
` Advanced Micro Devices, Inc. v. Monterey Research, LLC, IPR2020-
`
`00985 (P.T.A.B. 2020), which involves the ’134 patent.
`
` Qualcomm Inc. v. Monterey Research, LLC, IPR2020-01492 (P.T.A.B.
`
`2020), which involves the ’134 patent.
`
`C.
`
`Notice of Lead and Backup Counsel (37 C.F.R. § 42.8(b)(3))
`
` Lead Counsel: Peter J. Wied (Reg. No. 43,264), Nixon Peabody LLP, 300
`
`South Grand Avenue, Suite 4100, Los Angeles, CA 90071 (Tel: 213-629-
`
`6194; Fax: 844-295-1224; Email: pwied@nixonpeabody.com)
`
` First Backup Counsel: Vincent K. Yip (Reg. No. 42,245), Nixon Peabody
`
`LLP, 300 South Grand Avenue, Suite 4100, Los Angeles, CA 90071 (Tel:
`
`213-629-6196; Fax: 844-295-1221; Email: vyip@nixonpeabody.com)
`
`D.
`
`Notice of Service Information (37 C.F.R. § 42.8(b)(4))
`
`Please address all correspondence to the lead counsel at the address shown
`
`above. Petitioners consent to service by email at the following email addresses:
`
`3
`
`

`

`Patent No. 6,651,134
`Petition for Inter Partes Review
`
`pwied@nixonpeabody.com; and
`
`vyip@nixonpeabody.com.
`
`E.
`
`Payment of Fees
`
`The petition for inter partes review is accompanied by a payment of $42,625
`
`and requests review of 21 claims of the ’134 patent. No additional fees are believed
`
`to be due. However, if any additional fees are deemed to be due, the Director is
`
`authorized to charge any additional fees or credit overpayment to Deposit Account
`
`No. 50-4166, Order No. 081976-000003.
`
`F.
`
`Grounds for Standing
`
`Petitioners hereby certify that the patent for which review is sought is
`
`available for inter partes review and that the Petitioners are not barred or estopped
`
`from requesting an inter partes review challenging the patent claims on the grounds
`
`identified in the petition.
`
`The Grounds in This Petition Are Not Cumulative over the
`G.
`Grounds in IPR2020-00985 Or the Grounds in IPR2020-01492
`The grounds presented here are not cumulative over those in IPR2020-00985
`
`or those in IPR2020-01492, because the present Petition represents different primary
`
`references. Zagar and Takasugi are not primary references in either IPR2020-00985
`
`or IPR2020-01492.
`
`4
`
`

`

`Patent No. 6,651,134
`Petition for Inter Partes Review
`
`II.
`
`STATEMENT OF PRECISE RELIEF REQUESTED
`Claims 1-21 of the ’134 patent are unpatentable as being anticipated by or
`
`rendered obvious and should be cancelled in view of the following prior art:
`
`Ex.
`
`Reference
`
`1005 U.S. Patent No. 5,666,323 (issued September 9, 1997) (“Zagar”)
`
`1006 U.S. Patent No. 5,978,303 (issued November 2, 1999) (“Takasugi”)
`
`1007 U.S. Patent No. 6,115,280 (issued September 5, 2000) (“Wada”)
`
`1008 U.S. Patent No. 6,185,149 (issued February 6, 2001) (“Fujioka”)
`
`1009 U.S. Patent No. 5,784,331 (issued July 21, 1998) (“Lysinger”)
`
`The ’134 patent issued from U.S. Application No. 09/504,344 (“the ’344
`
`application”), filed February 14, 2000. (Ex.1001.) Therefore, the filing date of the
`
`claims, if fully supported, of the ’134 patent is February 14, 2000. Because the filing
`
`date is before March 16, 2013, the version of 35 U.S.C. §102 that predates the
`
`America Invents Act (“pre-AIA §102”) is applicable to the ’134 patent.
`
`U.S. Patent No. 5,666,323 (“Zagar”) (Ex.1005) issued on September 9, 1997.
`
`Accordingly, Zagar is prior art to the ’134 patent under at least pre-AIA 35 U.S.C.
`
`§102(b).
`
`5
`
`

`

`Patent No. 6,651,134
`Petition for Inter Partes Review
`
`U.S. Patent No. 5,978,303 (“Takasugi”) (Ex.1006) issued on November 2,
`
`1999. Accordingly, Takasugi is prior art to the ’134 patent under at least pre-AIA 35
`
`U.S.C. §102(b).
`
`U.S. Patent No. 6,115,280 (“Wada”) (Ex.1007) issued from U.S. Application
`
`No. 08/833,178, filed April 4, 1997. Accordingly, Wada is prior art to the ’134 patent
`
`under at least pre-AIA 35 U.S.C. §102(e).
`
`U.S. Patent No. 6,185,149 (“Fujioka”) (Ex.1008) issued from U.S.
`
`Application No. 09/340,147, filed June 28, 1999. Accordingly, Fujioka is prior art
`
`to the ’134 patent under at least pre-AIA 35 U.S.C. §102(e).
`
`U.S. Patent No. 5,784,331 (“Lysinger”) (Ex.1009) issued on July 21, 1998.
`
`Accordingly, Lysinger is prior art to the ’134 patent under at least pre-AIA 35 U.S.C.
`
`§102(b).
`
`Petitioners respectfully request that claims 1-21 of the ’134 patent be
`
`cancelled based on the following grounds:
`
`Ground
`1
`
`2
`
`3
`
`4
`
`Description
`Anticipation under 35 U.S.C. §102(b) by Zagar
`
`Claims
`1-3, 5, 8-10, 12-
`14, 16-18, 21
`2-7, 19-20
`
`11, 15
`
`Rendered obvious under 35 U.S.C. §103 over Zagar in
`view of Fujioka
`Rendered obvious under 35 U.S.C. §103 over Zagar in
`view of Lysinger
`1-5, 11-13, 15-18 Anticipation under 35 U.S.C. §102(b) over Takasugi
`
`6
`
`

`

`Patent No. 6,651,134
`Petition for Inter Partes Review
`
`Ground
`5
`
`Claims
`6-7, 14, 19-20
`
`6
`
`7
`
`8
`
`9
`
`10
`
`8-10, 21
`
`1-3, 8, 12-13, 16-
`17
`4, 11, 15
`
`5, 9-10, 14, 18,
`21
`6-7, 19-20
`
`Description
`Rendered obvious under 35 U.S.C. §103 over
`Takasugi in view of Fujioka
`Rendered obvious under 35 U.S.C. §103 over
`Takasugi in view of Zagar
`Anticipation under 35 U.S.C. §102(e) over Wada
`
`Rendered obvious under 35 U.S.C. §103 over Wada
`in view of Takasugi
`Rendered obvious under 35 U.S.C. §103 over Wada
`in view of Zagar
`Rendered obvious under 35 U.S.C. §103 over Wada
`in view of Zagar and further in view of Fujioka
`
`III. THE ’134 PATENT PETITIONED FOR REVIEW
`A. Summary of the ’134 Patent
`The ’134 patent relates to “a memory device that transfers a fixed number of
`
`words of data with each access.” (Ex.1001, 1:6-8.) The ’134 patent claims a well-
`
`known solution to a well-known problem of “burst” functionality in which a memory
`
`device generates a number of internal addresses in response to a single external
`
`address. (See Ex.1001, 1:10-18; Ex.1003, ¶35.) The ’134 patent asserts this solution
`
`is accomplished by having “a memory device that has a fixed burst length.” (See
`
`Ex.1001, 1:44-45.)
`
`The ’134 patent has three independent claims: 1, 16 and 17. (Ex.1001.) Claims
`
`1 and 16 are directed to circuits; claim 17 is directed to a method of providing a fixed
`
`burst length data transfer.
`
`7
`
`

`

`Patent No. 6,651,134
`Petition for Inter Partes Review
`
`Claim 1
`[1a] A circuit
`comprising:
`
`Claim 16
`[16a] A circuit
`comprising:
`
`[1b] a memory
`comprising a plurality of
`storage elements each
`configured to read and
`write data in response to
`an internal address signal;
`and
`
`[16b] means for
`reading data from and
`writing data to a plurality
`of storage elements in
`response to a plurality of
`internal address signals;
`and
`
`[1c] a logic circuit
`configured to generate
`a predetermined number
`of said internal address
`signals in response to
`(i) an external address
`signal,
`(ii) a clock signal and
`(iii) one or more control
`signals,
`[1d] wherein said
`generation of said
`predetermined number of
`internal address signals is
`non-interruptible.
`
`[16c] means for
`generating
`a predetermined number
`of said internal address
`signals in response to
`(i) an external address
`signal,
`(ii) a clock signal and
`(iii) one or more control
`signals,
`[16d] wherein said
`generation of said
`predetermined number of
`internal address signals is
`non-interruptible.
`
`Claim 17
`[17a] A method of
`providing a fixed burst
`length data transfer
`comprising the steps of:
`[17b] accessing a
`memory in response to a
`plurality of internal
`address signals; and
`
`[17c] generating
`
`a predetermined number
`of said internal address
`signals in response to
`(i) an external address
`signal,
`(ii) a clock signal and
`(iii) a control signal,
`
`[17d] wherein said
`generation of said
`predetermined number of
`internal address signals is
`non-interruptible.
`
`As shown above, claim elements [1a] and [16a] are identical. Claim elements
`
`[1b], [16b], and [17b] are nearly identical but differ slightly in the way the memory
`
`is recited. Claim elements [1c], [16c], and [17c] are also nearly identical in reciting
`
`the way the predetermined number of internal address signals is generated. Claim
`
`8
`
`

`

`Patent No. 6,651,134
`Petition for Inter Partes Review
`
`elements of [1d], [16d], [17d] are identical. The key provision of claims 1, 16, and
`
`17 is element [1d], [16d], [17d], respectively, which is directed to the generation of
`
`the predetermined number of internal address signals being non-interruptible. This
`
`element was used to distinguish the applied references during prosecution as
`
`explained below.
`
`The ’134 patent discloses a memory circuit that reads and writes data from
`
`memory using a burst of a “predetermined” number of “internal address signals”
`
`wherein the generation of internal address signals is “non-interruptible.” (Ex.1001,
`
`1:55-56.) The ’134 patent further asserts that in such a memory circuit or system: (1)
`
`“refresh activity (e.g., writeback, read for refresh, and writeback for refresh) may be
`
`completed within the time of the burst transfer,” and (2) “the address bus and control
`
`bus” are “free[d] up” “for a known number of cycles.” (Id., 5:8-15, 3:56-61.)
`
`B. Admitted Prior Art
`The ’134 patent confirms that “provid[ing] data from multiple address
`
`locations using a single address,” also called “burst mode access,” was well-known.
`
`(Ex.1001, 1:11-14 (Background).) Further, the ’134 patent admits that, “the burst
`
`mode of a conventional synchronous SRAM can be started and stopped in response
`
`to a control signal.” (Id., 1:16-27 (Background).)
`
`As shown in FIG. 1 of the ’134 patent, circuit 100 includes a circuit 102 that
`
`generates one or more internal address signals (ADDR_INT) that are input to a
`
`9
`
`

`

`Patent No. 6,651,134
`Petition for Inter Partes Review
`
`memory 104 to write/read burst data to/from that array. The memory 104 is where
`
`data is stored (a “write” operation) or accessed (a “read” operation). (Id., claim 1,
`
`2:26-30, 2:61-65, 3:2-4.)
`
`The circuit 100 of FIG. 1 is further depicted in FIG. 2. An embodiment of the
`
`circuit 102 includes an address counter register 126 and a burst counter 128. The
`
`circuit generates the predetermined number of internal address signals when the
`
`address counter register 126 receives (i) an external address signal (ADDR_EXT),
`
`(ii) a clock signal (CLK), and (iii) one or more control signals (e.g., LOAD; ADV).
`
`(Id., claim 1; 3:65-4:1.)
`
`10
`
`

`

`Patent No. 6,651,134
`Petition for Inter Partes Review
`
`The specification of the ’134 patent provides the following example: when the
`
`LOAD signal is asserted at input 108, the address counter register 126 latches in the
`
`external address ADDR_EXT to generate an initial internal address. (Id., 4:6-8.)
`
`Additional internal addresses are generated when the ADV is asserted (e.g., at input
`
`112), which causes the burst counter 128 to output the BURST_CLK signal at output
`
`132 in response to each clock signal CLK asserted at input 130. Receiving the
`
`BURST_CLK signal, the address counter register 126 increments the latched
`
`address to generate and output the next internal address. (Id., 4:8-14.) “Once the
`
`circuit 102 has started generating the fixed number of addresses, the circuit 102 will
`
`generally not stop until the fixed number of addresses has been generated (e.g., a
`
`non-interruptible burst).” (Id., 3:25-29.)
`
`Referring to FIG. 3 of the ’134 patent, another embodiment of the circuit 102’
`
`11
`
`

`

`Patent No. 6,651,134
`Petition for Inter Partes Review
`
`includes a latch 134, a counter 138, and a multiplexer MUX 136. An n-bit external
`
`address (ADDR_EXT) is divided into an m-bit portion and a k-bit portion. (Id., 4:18-
`
`25.) The k-bit portion is sent to the counter 138 and is incremented by the CLK
`
`signal when the ADV signal is asserted. (Id., 4:28-33.) The multiplexer MUX 136
`
`selects either the latched k-bit portion of the external address from output 142 or the
`
`k-bit output of the counter 138 and concatenates the k-bit portion / output with the
`
`latched m-bit portion of the external address to create the one or more internal
`
`addresses (ADDR_INT) that are used to address the memory. (Id., 4:34-39; Ex.1003,
`
`¶43.)
`
`12
`
`

`

`Patent No. 6,651,134
`Petition for Inter Partes Review
`
`C. Relevant Prosecution History of the ’134 Patent
`The ’134 patent issued from U.S. Application No. 09/504,344, which was
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`filed February 14, 2000. (Ex.1001.) The claims of the ’134 patent were repeatedly
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`rejected, and were only allowed after the Examiner did not file a response to the
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`applicant’s appeal brief.
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`In response to the §102 rejections where all claims were rejected as anticipated
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`by Yip (U.S. 6,289,138), the applicant argued that Yip did not disclose “the
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`generation of a predetermined number of internal address signals that is non-
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`interruptible.” (Id., 107.) Specifically, the applicant argued that Yip’s write burst
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`“can be interrupted when there is a cycle request from a higher priority port.” (Id.,
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`108.)
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`In a second Office Action, the Examiner rejected all pending claims under
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`§102 as anticipated by Cowles (US 5,729,504). (Id., 114-116.) The applicant
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`responded by arguing that Cowles’ internal address bursts were not non-
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`interruptible. (Id., 142-144.) The applicant also argued that “Cowles teaches that a
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`low to high transition of the WE* signal within a burst write access to the memory
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`array 112 will terminate the burst access, preventing further writes from occurring.”
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`(Id., 143.)
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`In a third Office Action, the Examiner maintained and made final the Cowles
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`rejection. (Id., 151-154.) The applicant again argued that Cowles did not teach that
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`Patent No. 6,651,134
`Petition for Inter Partes Review
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`the burst memory accesses were non-interruptible. (Id., 164.) The Examiner rejected
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`that argument in an Advisory Action (Id. 178), and the applicant appealed using the
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`same arguments. (Id., 189.) The Examiner did not file a responsive brief, and issued
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`a Notice of Allowance, conceding that Cowles disclosed:
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`[T]o terminate a continuous burst read operation, the WE signal merely
`has to transition high prior to a falling edge of the CAS signal (see, for
`example, Cowles). [T]hus prior art of record does not teach or fairly
`suggest the non-interruptible generation of a predetermined number of
`internal address signals.”
`(Id., 272 (emphasis in original).)
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`D. Person of Ordinary Skill in the Art
`A person of ordinary skill in the art (“POSITA”) at the time at which the
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`earliest application to which the ’134 patent claims priority was filed (February 14,
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`2000) would have been a technical person with a Bachelor’s degree in electrical
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`engineering, computer engineering, applied physics, or a related field, and
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`approximately two years of experience working in the design, development, and/or
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`testing of memory circuits, related hardware design, or the equivalent, with
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`additional education substituting for experience and vice versa. (Ex.1003, ¶27.)
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`E. Priority Date of ’134 Patent
`The ’134 patent issued from U.S. Application No. 09/504,344, filed February
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`14, 2000. (Ex.1001.) All of the references discussed herein are prior art to the ’134
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`patent.
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`Patent No. 6,651,134
`Petition for Inter Partes Review
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`F. Claim Construction
`Pursuant to 37 C.F.R. §42.100(b), claim terms should be given a meaning in
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`accordance with the standard used in §282(b) civil actions, including their “ordinary
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`and customary meaning … as understood by [a POSITA] and the prosecution
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`history.” For purposes of this IPR only, Petitioners propose that all terms should be
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`given their plain and ordinary meaning.
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`IV.
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`STATEMENT OF HOW EACH CLAIM IS UNPATENTABLE BASED
`ON THE PRIOR ART
`Petitioners assert that claims 1-21 of the ’134 patent are either anticipated or
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`rendered obvious in light of the prior art as set forth in detail below. The ’134 patent
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`claims a well-known solution to a well-known problem of “burst” functionality in
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`which a memory device generates a number of internal addresses in response to a
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`single external address. (See Ex.1001, 1:13-14; Ex.1003, ¶35.) The ’134 patent
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`asserts that this solution is accomplished by having “a memory device that has a
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`fixed burst length.” (See Ex.1001, 44-45.) Yet, both the problem and the solution
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`were well known to POSITA well before the filing date of the ’134 patent.
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`A. Ground 1: Anticipation by Zagar
`Zagar is §102(b) prior art and was not cited in the ’134 patent. Zagar identifies
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`the same problem addressed by the ’134 patent and addresses it in a similar, if not
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`identical manner, as in the ’134 patent. (See Ex.1005, 1:14-34; Ex.1001, 1:10-45;
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`Ex.1003, ¶52.)
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`Patent No. 6,651,134
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`Zagar relates to an integrated circuit memory device that has memory cells
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`and a clock input for synchronously latching control, address, and data signals.
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`(Ex.1005, Abstract.) Zagar discloses that time delays of sequentially accessing and
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`restoring memory bits in the NAND structure are masked through its architecture
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`and synchronous timing. (Id.) Zagar discloses a memory structure that is used to
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`provide continuous sequential access to the memory array by masking row access
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`and precharge times. (Id., 1:37-40.) By latching data from the array in temporary
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`high speed random access registers, the data can be rapidly read out of the part either
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`in a random page mode type access, or sequentially through the use of an integrated
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`column address counter. (Id., 1:43-48.)
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`Synchronous data input/output with the clock signal simplifies the interface
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`between the memory and external circuitry, and allows for a high speed data pipeline
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`between the random access registers and the input/output buffers. (Id., 1:41:43.)
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`Further, Zagar discloses that a programmable burst length counter may be included
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`to allow for a predetermined number of interleaved or linear data accesses. (Id., 1:51-
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`53.)
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`Independent Claim 1
`[1a] A circuit comprising:
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`Patent No. 6,651,134
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`To the extent that the preamble is limiting, Zagar discloses a “circuit.” FIG. 1
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`discloses “an electrical schematic diagram of a memory device.” (Ex.1005, 1:60-61;
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`FIG. 1.)
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`Additionally, FIG. 2 discloses “an electrical schematic diagram of a memory
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`device.” (Ex.1005, 1:62-64; FIG. 2.)
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`Patent No. 6,651,134
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`Thus, Zagar discloses claim element [1a]. (See id., ¶¶55-57.)
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`[1b] a memory comprising a plurality of storage elements
`each configured to read and write data in response to an
`internal address signal; and
`As shown in FIG. 1, the circuit includes a memory comprising a plurality of
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`storage elements (140, 142, 144, 146). “When a command is received on the control
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`node 40 to access a row in the memory, the word line generator will activate a series
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`of word lines 120, 122, 124 and 126” (i.e., internal address signals), “which in turn
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`sequentially actuate access devices 130, 132, 134 and 136 sequentially accessing
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`Patent No. 6,651,134
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`data stored on storage elements 140, 142, 144 and 146.” (Ex.1005, 2:22-27; Ex.1003,
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`¶58.)
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`These storage elements (140, 142, 144, 146) are configured to read and write
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`data in response to the series of word lines (120, 122, 124, 126) (i.e., one or more of
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`the internal address signals). (Ex.1003, ¶59.) For example, FIGS. 3-4 illustrate the
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`read operation and write operation of the circuit FIG. 1, respectively. (Ex.1005, 1:65-
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`2:3.)
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`Referring to FIG. 2, “[t]he memory device of FIG. 2 operates in a similar
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`fashion to the device of FIG. 1 (id., 3:10-11),” such that “[e]lements of like function
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`between F