United States Patent (19)
`Wada
`
`USOO611528OA
`Patent Number:
`11
`(45) Date of Patent:
`
`6,115,280
`*Sep. 5, 2000
`
`54 SEMICONDUCTOR MEMORY CAPABLE OF
`BURST OPERATION
`
`75 Inventor: Tomohisa Wada, Hyogo, Japan
`
`73 Assignee: Mitsubishi Denki Kabushiki Kaisha,
`Tokyo, Japan
`
`*
`
`Notice:
`
`This patent issued on a continued pros-
`ecution application filed under 37 CFR
`1.53(d), and is Subject to the twenty year
`patent term provisions of 35 U.S.C.
`154(a)(2).
`
`21 Appl. No.: 08/833,178
`22 Filed:
`Apr. 4, 1997
`Related U.S. Application Data
`63 Continuation of application No. 08/547,341, Oct. 24, 1995,
`(631 centation of app
`30
`Foreign Application Priority Data
`5
`Nov. 1, 1994
`JP
`Japan .................................... 6-26892
`(51) Int. Cl." ....................................................... G11C 7700
`52 U.S. Cl. ......................... 365/78; 365/236, 365/1892;
`365/230.03
`58) Field of Search
`365/236, 230.03
`365is012,240, 18902 23002. 78 233
`s a
`as
`s
`s
`Y-9
`References Cited
`
`56)
`
`U.S. PATENT DOCUMENTS
`4,899,310 2/1990 Baba et al. ............................ 365/78 X
`5,200,925 4/1993 Morooka ................................. 365/219
`
`5,220,529 6/1993 Kohiyara et al. ..................... 365/78 X
`5,463,591 10/1995 Aimoto et al...
`... 365/189.12 X
`5.535,172 7/1996 Reddy et al. ...
`... 365/189.12 X
`5,561,633 10/1996 Yamano ......................... 365/230.03 X
`FOREIGN PATENT DOCUMENTS
`3-58386 3/1991 Japan.
`3-76094 4/1991 Japan.
`4-184791
`7/1992 Japan.
`5–144269 6/1993 Japan.
`OTHER PUBLICATIONS
`“IBM Prepares Synch SRAM Entries,” Electric News, Jun.
`6, 1994, p. 70.
`Child, “RISC and Pentium drive demand for SRAMs that
`are fastest of the fast,” Computer Design, Mar. 28, 1994, pp.
`47-48.
`Primary Examiner A. Zarabian
`Attorney, Agent, or Firm McDermott, Will & Emery
`57
`ABSTRACT
`A Semiconductor memory for operating in burst mode. The
`memory has a memory cell array divided into a plurality of
`memory blocks, a plurality of (e.g., 2) output registers each
`including a plurality of output data retaining blocks corre
`sponding to the multiple memory blocks, and a burst counter
`unit. The output registers alternately receive data transferred
`from the memory cell array. In accordance with the result of
`counting by the burst counter unit, the data retained in the
`output registers is output alternately in bursts, whereby the
`Speed of data read operation in the memory is boosted
`regardless of the operating Speed of the memory cell array
`therein.
`
`12 Claims, 16 Drawing Sheets
`
`CONTROL
`CIRCUT
`
`
`
`SELASELB
`
`
`
`Bill b2. B3
`AY
`
`63
`
`CLKO
`
`EXCHAC
`ADWO
`ADSC
`
`
`
`NTCHA
`
`COUNTER
`UNIT
`
`NANYA TECHNOLOGY EXHIBIT 1007
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`U.S. Patent
`
`Sep. 5, 2000
`
`Sheet 1 of 16
`
`6,115,280
`
`| BITINE PRECHARGING
`CIRCUIT
`
`3
`
`FIG. 1
`
`2
`2O
`
`MADD O
`
`DECODER
`
`90 INTADD
`
`11
`
`.
`
`72BIT
`
`71
`
`72
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`TRA
`
`CONTROL
`CIRCUIT
`
`DECODER
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`5B
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`MUXHMUXHMUXHMUX
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`91
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`CLK C
`
`SELASELB
`
`EXT. CHAO 93
`ADV O 94
`ADS O
`
`
`
`
`
`BURST
`COUNTER
`UNIT
`
`MUX -7
`
`O)-9
`
`NANYA TECHNOLOGY EXHIBIT 1007
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`U.S. Patent
`
`Sep. 5, 2000
`
`Sheet 2 of 16
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`6,115,280
`
`
`
`
`
`‘ON ETIOÅO
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`NANYA TECHNOLOGY EXHIBIT 1007
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`U.S. Patent
`
`Sep. 5, 2000
`
`Sheet 3 of 16
`
`6,115,280
`
`FIG.3
`
`1
`
`BIT LINE PRECHARGING
`CIRCUIT
`
`3
`
`2
`
`2O
`
`C
`
`MADD O
`
`DECODER
`
`90 INTADD
`
`1
`1
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`TR
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`CLK G2
`92
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`EXT.CHAO
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`BURST
`COUNTER
`
`NT. CHA
`
`94
`
`ADSO
`
`O-9
`
`NANYA TECHNOLOGY EXHIBIT 1007
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`

`U.S. Patent
`
`Sep. 5, 2000
`
`Sheet 4 of 16
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`6,115,280
`
`
`
`NANYA TECHNOLOGY EXHIBIT 1007
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`US. Patent
`
`Sep. 5, 2000
`
`Sheet 5 0f 16
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`6,115,280
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`NANYA TECHNOLOGY EXHIBIT 1007
`
`NANYA TECHNOLOGY EXHIBIT 1007
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`
`
`
`

`

`US. Patent
`
`Sep. 5,2000
`
`Sheet 6 0f 16
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`6,115,280
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` CYCLENO
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`EXTCHA
`CLK
`FIG.6I
`
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`NANYA TECHNOLOGY EXHIBIT 1007
`
`NANYA TECHNOLOGY EXHIBIT 1007
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`U.S. Patent
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`6,115,280
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`NANYA TECHNOLOGY EXHIBIT 1007
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

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`U.S. Patent
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`Sep. 5, 2000
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`Sheet 8 of 16
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`6,115,280
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`NANYA TECHNOLOGY EXHIBIT 1007
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`

`U.S. Patent
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`Sep. 5, 2000
`
`Sheet 9 of 16
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`6,115,280
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`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

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`U.S. Patent
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`Sep. 5, 2000
`
`Sheet 10 of 16
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`6,115,280
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`NANYA TECHNOLOGY EXHIBIT 1007
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

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`U.S. Patent
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`Sep. 5, 2000
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`Sheet 11 of 16
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`6,115,280
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`NANYA TECHNOLOGY EXHIBIT 1007
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`U.S. Patent
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`Sep. 5, 2000
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`Sheet 12 of 16
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`6,115,280
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`NANYA TECHNOLOGY EXHIBIT 1007
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

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`U.S. Patent
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`Sep. 5, 2000
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`Sheet 13 of 16
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`6,115,280
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`NANYA TECHNOLOGY EXHIBIT 1007
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

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`U.S. Patent
`
`Sep. 5, 2000
`
`Sheet 14 of 16
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`6,115,280
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`
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`NANYA TECHNOLOGY EXHIBIT 1007
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

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`U.S. Patent
`
`Sep. 5, 2000
`
`Sheet 15 of 16
`
`6,115,280
`
`| BINE PRECHARGING La
`CIRCUIT
`
`FIG. 15 PRIOR ART
`
`2
`
`20
`
`MADD O
`
`DECODER
`
`90 INTADD
`
`1
`
`41
`
`72BITY72BITY72BTY72BIT
`
`TR
`
`50
`
`51 : 52 : 53
`51 : 52 : 53
`
`
`
`91
`CLK O
`92
`
`EXT.CHAO
`
`94
`
`ADS (O
`
`BURST
`COUNTER NT. CHA
`
`MUX
`
`7
`
`C-9
`
`NANYA TECHNOLOGY EXHIBIT 1007
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`U.S. Patent
`
`Sep. 5, 2000
`
`Sheet 16 of 16
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`6,115,280
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`ZI | | | | 01 | 6 | 8 || L | 9 | ? | jv | C | Z | | | `ON ETOÃO
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`NANYA TECHNOLOGY EXHIBIT 1007
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`1
`SEMCONDUCTOR MEMORY CAPABLE OF
`BURST OPERATION
`
`6,115,280
`
`2
`100 admits an external address signal EXTADD from the
`outside. An input pin 101 gets a read/write control Signal
`/WE furnished externally. The slash symbol (/) indicates that
`the Signal having the Symbol is an inverted Signal. This
`applies throughout the description hereunder.
`The burst counter unit 80 includes AND gates 81 and 82,
`a register 83 and a burst counter 84. The AND gate 81
`receives the advance Signal ADV and clock Signal CLK, and
`outputs a Signal representing the result of the AND operation
`on the two signals. The AND gate 82 admits the address
`Strobe Signal ADS and clock signal CLK, and outputs a
`signal denoting the result of the AND operation on the two
`Signals.
`The register 83 receives both the output signal of the AND
`gate 82 and the external address signal EXTADD. In
`operation, the register 83 takes the external address Signal
`EXT ADD into the burst counter unit 80 in response to the
`output signal from the AND gate 82. The n-bit address
`admitted into the register 83 is separated into a k-bit address
`and an (n-k)-bit address.
`The burst counter 84 is a binary counter that receives the
`output signals of the AND gates 81 and 82, and the k-bit
`address following the address Separation. In operation, the
`burst counter 84 loads the k-bit address by responding to the
`output signal of the AND gate 82, and increments the value
`of the k-bit address in reply to the output signal of the AND
`gate 81.
`The k-bit address representing the result of the counting
`by the burst counter 84 is then recombined with the sepa
`rated (n-k)-bit address. The result is an n-bit internal address
`that is fed to the decoder 2. Given the n-bit internal address
`signal INTADD, the decoder 2 selects one word line 11.
`The register 21 receives the clock signal CLK and the
`read/write control signal /WE. The read/write control signal
`/WE is admitted into the register 21 responding to a leading
`edge of the clock signal CLK. The read/write control Signal
`/WE indicates a write state when brought Low, and denotes
`a read state when driven High. The read/write control circuit
`22 outputs a control Signal for controlling the bit line
`precharging circuit 3 and the Sense amplifier and write driver
`4 in reply to the read/write control signal /WE admitted
`through the register 21.
`Given the control signal from the read/write control
`circuit 22, the bit line precharging circuit 3 precharges a bit
`line pair 12, 12 to a predetermined high level in preparation
`for a read operation. Upon receipt of the control Signal from
`the read/write control circuit 22, the Sense amplifier and
`write driver 4 operates as follows:
`In the write operation, the Sense amplifier and write driver
`4 transfers to the bit line pair 12, 12 the input data DI
`admitted into the register 23 from the outside via a data
`input/output pin 9.
`The conventional SRAM of the above constitution typi
`cally works as follows: when the advance signal ADV is
`brought High, the address on the burst counter 84 is incre
`mented every time a leading edge of the clock Signal CLK
`is encountered. As the internal address signal INTADD is
`incremented in this manner, the decoder 2 Selects different
`word lines 11 successively.
`Below is a description of how the SRAM of FIG. 12
`Works in a read operation. FIG. 13 is a timing chart showing
`typical waveforms of signals used by the SRAM of FIG. 12
`in the read operation.
`Referring to FIGS. 12 and 13, the read/write control
`signal /WE is fixed to the high level for the read operation.
`
`5
`
`25
`
`35
`
`40
`
`15
`
`This application is a continuation of application Ser. No.
`08/547,341 filed Oct. 24, 1995, now abandoned.
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates to a Semiconductor memory
`capable of operating in burst mode and, more particularly, to
`a high-Speed Semiconductor memory used illustratively as a
`cache memory.
`2. Description of the Related Art
`There exist Semiconductor memories capable of the
`So-called burst output. Such Semiconductor memories
`include an address counter and a memory cell array. The
`address counter operates in response to a clock signal input.
`When read from memory cells in the memory cell array, the
`data is output in accordance with the result of the counting
`by the address counter.
`FIG. 12 is a block diagram of a typical conventional
`SRAM capable of operating in burst mode. Referring to
`FIG. 12, the SRAM comprises a memory cell array 1, a
`decoder 2, a bit line precharging circuit 3, a Sense amplifier
`and write driver 4, registers 21 and 23, a read/write control
`circuit 22, and a burst counter unit 80.
`The memory cell array 1 includes a plurality of memory
`cells MC, MC, etc., a plurality of word lines 11, 11, etc., and
`a plurality of bit line pairs 12, 12, etc. The memory cells MC,
`MC, etc. constitute a matrix made of rows and columns,
`each cell accommodating data.
`Each memory cell MC comprises two access transistors
`13 and 14, two driver transistors 15 and 16, and two load
`resistors 17 and 18. The access transistors 13 and 14 and the
`driver transistors 15 and 16 are an n-channel MOS transistor
`each. The load resistors 17 and 18 are each composed of a
`resistance element, a p-channel MOS transistor or a thin film
`transistor.
`The load resistor 17 and the driver transistor 15 are
`connected in Series between a power Supply node N1 that
`receives a Supply potential and a grounding node N2 that
`receives a grounding potential. The load resistor 18 and the
`driver transistor 16 are also connected serially between the
`two nodes N1 and N2. The driver transistors 15 and 16 have
`their gate and drain electrodes connected by interSection.
`The access transistor 13 has its gate electrode connected
`to a word line 11. The access transistor 13 is connected
`interposingly between one of the two bit lines constituting a
`bit line pair 12, 12 on the one hand, and the connection node
`(storage node) between the load resistor 17 and the driver
`transistor 15 on the other hand.
`The access transistor 14 has its gate electrode connected
`to the word line 11. The access transistor 14 is connected
`interposingly between the other of the two bit lines consti
`tuting the bit line pair 12, 12 on the one hand, and the
`connection node (Storage node) between the load resistor 18
`and the driver transistor 16 on the other hand.
`The word lines 11, 11, etc. are each furnished to select the
`memory cells arranged thereon. The bit line pairs 12, 12, etc.
`are each provided to transfer write and read data to and from
`the memory cell MC selected by the applicable word line 11.
`An input pin 91 admits a clock signal CLK from the
`outside. An input pin 93 receives an advance signal ADV
`65
`that is externally furnished. An input pin 94 receives an
`externally provided address Strobe Signal ADS. An input pin
`
`45
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`50
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`55
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`60
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`NANYA TECHNOLOGY EXHIBIT 1007
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`6,115,280
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`15
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`25
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`35
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`40
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`3
`When a leading edge of the clock signal CLK is
`encountered, the address Strobe Signal ADS is brought High.
`This allows the external address input signal EXTADD to
`be admitted into the register 83.
`Thereafter, every time the clock Signal CLK is at a leading
`edge and the advance Signal ADV is High, the address
`indicated by the internal address signal INTADD based on
`the address An given by the external address signal
`EXT ADD is incremented by the burst counter 84. The
`incremented address occurs as An, An+1, An+2, etc. This
`causes a different word line 11 to be Selected in each cycle
`of the clock signal CLK. As a result, the output data DO
`varies in the Sequence of Qn, Qn+1, Qn+2, etc. This in turn
`allows data to be output in burst mode from memory cells
`MC, MC, etc. in the memory cell array 1.
`Below is a description of how the SRAM of FIG. 12
`Works in a write operation. FIG. 14 is a timing chart showing
`typical waveforms of signals used by the SRAM of FIG. 12
`in the write operation.
`Referring to FIGS. 12 and 14, the read/write control
`Signal (WE for the write operation is given as a pulse signal
`as opposed to the high-level Signal used in the read opera
`tion. The input data DI (Dn, Dn+1, Dn+2, etc.) is admitted
`in Synchronism with the pulse-type read/write control Signal
`/WE.
`In the write operation, the internal address INTADD
`based on the address An designated by the external address
`signal EXTADD varies in the same manner as in the read
`operation. This allows the input data DI to be written to
`memory cells MC, MC, etc. of the memory cell array 1 in
`the Sequence of Dn, Dn+1, Dn+2, etc.
`What follows is a description of another conventional
`Semiconductor memory capable of operating in burst mode.
`The description will center on the read circuit portion of the
`Semiconductor memory.
`FIG. 15 is a block diagram of one such conventional
`SRAM also capable of operating in burst mode. In FIG. 15,
`the common parts that also appear in FIG. 12 are designated
`by like reference numerals, and their descriptions are omit
`ted hereunder where redundant.
`The semiconductor memory of FIG. 15 differs from that
`of FIG. 12 in the following aspects: the burst counter unit 80
`is not provided; an output register 5, a multiplexer 7, a burst
`counter unit 8 and an internal register 20 are furnished; and
`the memory cell array 1 is divided into a plurality of memory
`blocks M0 through M3.
`The memory cell array 1 has a plurality of memory cells
`(like the memory cells MC, MC, etc. in FIG. 12) divided into
`a plurality of (e.g., four) memory blocks M0 through M3 in
`columns. In this case, the memory cell array 1 is divided into
`four memory blocks M0 through M3 illustratively of 72 bits
`each. In FIG. 15, a single unit of data is shown to be
`composed of 72 bits.
`An input pin 90 receives a memory address input signal
`MADD for selecting one of the word lines 11 in the memory
`cell array 1. The internal register 20 admits the memory
`address signal MADD using an appropriate timing (e.g., in
`synchronism with the address strobe signal ADS) and sends
`the admitted address to the decoder 2 as an internal address
`signal INTADD.
`In response to the internal address signal INTADD, the
`decoder 2 selects one of the word lines 11 in the memory cell
`array 1. A sense amplifier 41 in FIG. 15 is a latch type sense
`amplifier that constitutes part of the Sense amplifier and
`write driver 4 in FIG. 12.
`
`45
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`50
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`55
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`60
`
`65
`
`4
`With the word line 11 selected, the sense amplifier 41
`receives the data items read simultaneously from the
`memory blocks M0 through M3 over the bit lines (see FIG.
`12). The sense amplifier 41 amplifies each of the data items
`thus received.
`The output register 5 is composed of a plurality of D type
`flip-flop circuits each retaining the data item amplified by
`the sense amplifier 41. With this output register 5, the D type
`flip-flop circuits correspond to the memory blocks MO
`through M3 in the memory cell array 1, Serving as four data
`retaining blocks 50 through 53 respectively. Each of the data
`retaining blocks 50 through 53 in the output register 5 retains
`data in reply to a transfer signal TR.
`An input pin 92 receives an external chunk address Signal
`EXTCHA for selecting one of the data retaining blocks 50
`through 53 in the output register 5.
`The burst counter unit 8 is identical in structure to the
`burst counter unit 80 in FIG. 12, except that the external
`address signal EXTADD of FIG. 12 is replaced by the
`external chunk address signal EXTCHA. Thus the detailed
`structure of the burst counter unit 8 will not be discussed
`further.
`Responding to the clock signal CLK, the burst counter
`unit 8 increments the value designated by the external chunk
`address signal EXTCHA. The incremented result of the
`counting Serves as an internal chunk address Signal
`INTCHA.
`In reply to the internal chunk address signal INTCHA, the
`multiplexer 7 selects and outputs one of the four 72-bit data
`items retained in the output register 5. That is, the multi
`plexer 7 selects one of the data retaining blocks 50 through
`53 in the output register 5 by responding to the result of the
`counting by the burst counter unit 8.
`Given the internal chunk address signal INTCHA, the
`multiplexer 7 Successively transferS to the data input/output
`pin 9 the four 72-bit data items retained in the data retaining
`blocks 50 through 53.
`In the manner described, the SRAM of FIG. 15 performs
`the read operation in burst mode.
`Below is a more detailed description of how the SRAM of
`FIG. 15 works in a read operation. FIG. 16 is a timing chart
`showing typical waveforms of signals used by the SRAM of
`FIG. 15 in the read operation. In FIG. 16, the cycles of the
`clock signal CLK are numbered 1, 2, 3, etc.
`Referring to FIG. 16, the address An designated by the
`memory address signal MADD is admitted into the internal
`register 20 in response to the first leading edge in the Second
`cycle of the clock signal CLK. With the address An thus
`admitted, the word line 11 (WL) becomes selectable
`between the Second and the fourth cycle. In response to this,
`data is read from the memory cell array 1 and is amplified
`by the sense amplifier 41.
`In the fourth cycle, the transfer signal TR is brought High
`for a predetermined period of time. In response, the Sense
`amplifier 41 transfers the amplified data to each of the data
`retaining blocks 50 through 53 in the output register 5 while
`the fourth cycle is in effect.
`In the fifth cycle, the burst counter unit 8 admits an
`address AC Stemming from the external chunk address
`signal EXTCHA. The counting by the burst counter unit 8
`starts in the fifth cycle. Between the fifth and the eighth
`cycle, the internal chunk address signal INTCHA varies in
`the Sequence of Ac, Ac+1, Ac+2, etc.
`Consequently, the data items held in the data retaining
`blocks 50 through 53 of the output register 5 are output
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`NANYA TECHNOLOGY EXHIBIT 1007
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`successively from the multiplexer 7 to the outside via the
`data input/output pin 9.
`AS described, the output data DO is output in burst mode,
`i.e., in the Sequence of D(An), D(An+1), etc., from the fifth
`through the eighth cycle.
`Data is then read from an address Am that is input as the
`memory address signal MADD following the address An. In
`this case, the data corresponding to the address Am is read
`in the same manner as the data corresponding to the address
`An
`While the data related to the current address An is under
`way, it is necessary to retain, in the data retaining blockS 50
`through 53 of the output register 5, the data associated with
`the address An. For this reason, the transfer signal TR for
`reading the data corresponding to the next address Am is
`driven High in the ninth cycle following the completion of
`the burst output of the data associated with the current
`address An.
`Therefore, the burst output of the output data DO related
`to the next address Am is carried out one cycle after the end
`of the burst output concerning the current address An, as
`shown in the sequence of D(Am), D(Am+1), etc. In this
`manner, the SRAM of FIG. 15 also allows the data therein
`to be read out in burst mode.
`The conventional SRAMs outlined above have some
`disadvantages that will now be described.
`With the conventional SRAM of FIG. 12, a word line 11
`is Selected and the related parts of the memory cell array 1
`are activated in each of the cycles of the furnished clock
`Signal CLK. It follows that the clock cycle time defining a
`period in which to repeat data output (called the data transfer
`called hereunder) is determined by the delay times in
`operations of the word lines 11, 11, etc., of the bit line pairs
`12, 12, etc., and of the memory cell arrays MC, MC, etc.
`This means that, with the SRAM of FIG. 12, attempts to
`reduce the cycle time of the clock signal CLK for higher
`operating Speeds fail to make the cycle time shorter than the
`Sum of the operative delays resulting from the parts of the
`memory cell array 1. Such delays in the operations of
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`various parts in the memory cell array 1 prevent the SRAM
`of FIG. 12 from operating more quickly than at present.
`With the SRAM of FIG. 15, the timing for the burst output
`of data is irrelevant to the operative delays of the various
`parts in the memory cell array 1. Such delays do not hamper
`efforts to make the memory as a whole operate at higher
`speeds than before. However, as mentioned above, the burst
`output of the data read from the memory cell array 1 poses
`a different problem.
`That is, a data-free period (an interruption in the flow of
`data output) is bound to occur between two burst outputs,
`one relating to the current memory address An, the other
`asSociated with the next memory address Am.
`Suppose that a data output interruption of one cycle
`period occurs following each burst output lasting four
`cycles. In that case, if one burst output is taken as a Single
`period, the data transfer period is prolonged by 20 percent.
`In other words, the data transfer rate declines by 20 percent.
`Thus although the SRAM of FIG. 15 is exempt from the
`operative delays in the parts of the memory cell array 1, the
`memory fails to shorten Sufficiently the data transfer period
`in enhancing its operation speed. As a result, the SRAM of
`FIG. 15 is incapable of operating at a Sufficiently high Speed.
`SUMMARY OF THE INVENTION
`It is therefore an object of the present invention to provide
`a Semiconductor memory operating in burst mode at a
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`Sufficiently high Speed irrespective of the operating Speed of
`its memory cell array.
`It is another object of the present invention to provide a
`Semiconductor memory working in burst mode for a high
`Speed read operation irrespective of the operating Speed of
`its memory cell array and without causing data output
`interruptions.
`It is a further object of the invention to provide a semi
`conductor memory working in burst mode for a high-speed
`write operation irrespective of the operating Speed of its
`memory cell array.
`In carrying out the invention and according to one aspect
`thereof, there is provided a Semiconductor memory com
`prising a memory cell array, a plurality of output registers,
`an output register Selecting circuit, a counter circuit, a data
`output pin and an output data transfer circuit. Each of the
`output registers includes a plurality of output data retaining
`blocks made of a plurality of columns each.
`The memory cell array has a plurality of memory cells
`arranged in a plurality of rows and a plurality of columns for
`Storing data. The memory cells are divided into a plurality of
`blocks.
`The output registers each retain data read from the blockS
`of the memory cell array. The output data retaining blocks in
`each of the output registers correspond to the blocks of the
`memory cell array. Each of the output data retaining blockS
`retains data read from the corresponding block of the
`memory cell array.
`The output register Selecting circuit Selects one of the
`output registers. The counter circuit performs a count in
`Synchronism with a clock signal externally Supplied. The
`data output pin outputs data to the outside.
`The output data transfer circuit Successively Selects, in
`accordance with the result of the counting by the counter
`circuit, the output data retaining blocks of the output register
`Selected by the output register Selecting circuit. The output
`data transfer circuit then transferS the data from the Succes
`Sively Selected output data retaining blocks to the data
`output pin, thereby outputting the data over a plurality of
`cycles of the clock signal.
`With this structure, the data read from the multiple blocks
`of the memory cell array is Set to and retained in the
`respective data retaining blocks in each of the multiple
`output registers.
`The output register Selecting circuit Selects one output
`register. The data held in the multiple data retaining blockS
`of the Selected output register is transferred to the data
`output pin by the output data transfer circuit. Data transfer
`is effected by the output data transfer circuit Successively
`Selecting the data in the data retaining blocks in response to
`the count result from the counter circuit. This causes the data
`read from the multiple blocks of the memory cell array to be
`output in burst mode.
`Operating in this manner, the inventive Semiconductor
`memory outputs in burst mode the retained data from one
`output register while transferring the data read from memory
`cells of the memory cell array to another output register. This
`makes it possible to output a plurality of target data items in
`burst mode without interruption therebetween.
`With this kind of burst output carried out, the speed of the
`data read operation from the memory cell array to the
`outside is increased regardless of the operating Speed of the
`memory cell array.
`In a preferred Structure according to the invention, the
`output register Selecting circuit may receive an externally
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`NANYA TECHNOLOGY EXHIBIT 1007
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`furnished address input signal designating the output register
`to be Selected, and Select that output register in accordance
`with the address input signal.
`With this preferred Structure, the output register Selecting
`circuit Selects one output register in response to the address
`input Signal from the outside. This feature allows the output
`register to be selected externally as desired.
`According to another aspect of the invention, there is
`provided a Semiconductor memory comprising a memory
`cell, a plurality of output registers, a write register Selecting
`circuit, a read register Selecting circuit, a counter circuit, a
`data output pin and an output data transfer circuit. Each of
`the output registers includes a plurality of output data
`retaining blockS.
`The memory cell array has a plurality of memory cells
`arranged in a plurality of rows and a plurality of columns for
`Storing data. The memory cells are divided into a plurality of
`blocks made of a plurality of columns each.
`The output registers each retain data written thereto after
`being read from the blocks of the memory cell array. The
`output data retaining blocks in each of the output registers
`correspond to the blocks of the memory cell array. Each of
`the output data retaining blocks retains data read from the
`corresponding block of the memory cell array.
`The write register Selecting circuit Selects one of the
`output registers to which to write data read from the memory
`cell array. The read register Selecting circuit Selects one of
`the output registers from which to read the retained data. The
`counter circuit performs a count in Synchronism with a clock
`Signal externally Supplied. The data output pin outputs data
`to the outside.
`The output data transfer circuit Successively selects, in
`accordance with the result of the counting by the counter
`circuit, the output data retaining blocks of the output register
`Selected by the read register Selecting circuit. The output
`data transfer circuit then transferS the data from the Succes
`Sively Selected output data retaining blocks to the data
`output pin, thereby outputting the data over a plurality of
`cycles of the clock signal.
`With this structure, the data read from the multiple blocks
`of the memory cell array is retained in the respective data
`retaining blocks in each of the output registers.
`One of the multiple output registers is Selected by the
`write register Selecting circuit. The output register thus
`Selected has data written thereto after its retrieval from the
`blocks of the memory cell array. Another output register is
`Selected by the read register Selecting circuit. From the
`output register thus Selected, the retained data is read out. In
`this manner, the output register to which to write data and
`the output register from which to read retained data are
`Selected by different Selecting circuits.
`The data retained in the multiple data retaining blocks of
`the Selected output register is transferred by the output data
`transfer circuit to the data output pin. Data transfer is
`effected by the output data transfer circuit Successively
`Selecting the data in the data retaining blocks in response to
`the count result from the counter circuit. This causes the data
`read from the blocks of the memory cell array to be output
`in burst mode.
`Operating in this fashion, the Semiconductor memory of
`the invention outputs in burst mode the retained data from
`one output register while transferring the data read from the
`memory cell array to another output register. This makes it
`possible to output a plurality of target data items in burst
`mode without interruption therebetween.
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`With this kind of burst output carried out, the speed of the
`data read operation from the memory cell array to the
`outside is also increased regardless of the operating Speed of
`the memory cell array.
`In a preferred Structure of the Semiconductor memory
`according to the above aspect of the invention, the write
`register Selecting circuit may receive an externally Supplied
`first address input signal designating the output register to be
`Selected, and Select that output register in accordance with
`the first address input signal. Furthermore, the read register
`Selecting circuit may receive an e