(12) United States Patent
`Yamazaki et al.
`
`USOO665726OB2
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,657,260 B2
`Dec. 2, 2003
`
`(54) THIN FILM TRANSISTORS HAVING
`SOURCE WIRING AND TERMINAL
`PORTION MADE OF THE SAME MATERIAL
`AS THE GATE ELECTRODES
`
`(75) Inventors: Shunpei Yamazaki, Tokyo (JP);
`Hideomi Suzawa, Kanagawa (JP);
`Yoshihiro Kusuyama, Kanagawa (JP);
`Koji Ono, Kanagawa (JP); Jun
`Koyama, Kanagawa (JP)
`(73) Assignee: Semiconductor Energy Laboratory
`Co., Ltd., Atsugi (JP)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(*) Notice:
`
`(21) Appl. No.: 10/078,489
`(22) Filed:
`Feb. 21, 2002
`(65)
`Prior Publication Data
`US 2002/0158288 A1 Oct. 31, 2002
`Foreign Application Priority Data
`(30)
`(JP) ....................................... 2001-056063
`Feb. 28, 2001
`Sep. 28, 2001
`(JP) ....................................... 2001-302687
`(51) Int. Cl." ......................... H01L 27/01; H01L 27/12;
`H01L 31/0392; H01L 29/04; H01L 31/20
`(52) U.S. Cl. ........................... 257/350; 257/59; 257/72;
`257/311; 257/412
`(58) Field of Search ............................ 257/59, 72,296,
`257/311, 350, 412
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`2/2000 Miyazaki et al.
`
`6,031.290 A
`
`4/2002 Yamazaki
`6,365.917 B1
`6,448,578 B1 * 9/2002 Shimada et al. .............. 257/59
`6,475,836 B1 11/2002 Suzawa et al.
`6,515,336 B1
`2/2003 Suzawa et al.
`2001/003O322 A1 10/2001 Yamazaki et al.
`2001/0049.197 A1 12/2001 Yamazaki et al.
`2001/005295.0 A1 12/2001 Yamazaki et al.
`2001/0055841 A1 12/2001 Yamazaki et al.
`2002/OOO6705 A1
`1/2002 Suzawa et al.
`2002/0013022 A1
`1/2002 Yamazaki et al.
`2002/0016028 A1
`2/2002 Arao et al.
`2002/0017685 A1
`2/2002 Kasahara et al.
`2002/0070382 A1
`6/2002 Yamazaki et al.
`2002/0110941 A1
`8/2002 Yamazaki et al.
`
`FOREIGN PATENT DOCUMENTS
`
`JP
`JP
`JP
`
`6-148685
`7-23568O
`8-274336
`
`5/1994
`9/1995
`10/1996
`
`* cited by examiner
`
`Primary Examiner Ngan V. Ngó
`(74) Attorney, Agent, or Firm-Fish & Richardson P.C.
`(57)
`ABSTRACT
`There are provided a structure of a Semiconductor device in
`which low power consumption is realized even in a case
`where a size of a display region is increased to be a large size
`Screen and a manufacturing method thereof. Agate electrode
`in a pixel portion is formed as a three layered Structure of a
`material film containing mainly W, a material film contain
`ing mainly Al, and a material film containing mainly Tito
`reduce a wiring resistance. A wiring is etched using an IPC
`etching apparatus. The gate electrode has a taper shape and
`the width of a region which becomes the taper shape is Set
`to be 1 um or more.
`
`29 Claims, 18 Drawing Sheets
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`Page 1 of 33
`
`APPLIED MATERIALS EXHIBIT 1046
`
`

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`U.S. Patent
`US. Patent
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`Dec. 2, 2003
`Dec. 2, 2003
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`Sheet 1 of 18
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`Dec. 2, 2003
`Dec. 2, 2003
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`Sheet 2 of 18
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`US 6,657,260 B2
`US 6,657,260 B2
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`Page 3 of 33
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`U.S. Patent
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`Dec. 2, 2003
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`

`

`US 6,657,260 B2
`
`1
`THIN FILM TRANSISTORS HAVING
`SOURCE WIRING AND TERMINAL
`PORTION MADE OF THE SAME MATERIAL
`AS THE GATE ELECTRODES
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates to a Semiconductor device
`having a circuit composed of thin film transistors
`(hereinafter referred to as TFTs) and a manufacturing
`method thereof. The present invention relates to, for
`example, a device represented by a liquid crystal display
`device (on which a liquid crystal module is mounted) and an
`electronic device on which Such a device is mounted as a
`part.
`Note that the Semiconductor device in this Specification
`indicates a device in general, which can function by utilizing
`a Semiconductor characteristic, and an electro-optical
`device, a light emitting device, a Semiconductor circuit, and
`an electronic device each are the Semiconductor devices.
`2. Description of the Related Art
`In recent years, a technique for constructing a thin film
`transistor (TFT) using a semiconductor thin film (about
`Several to Several hundreds nm in thickness) formed on a
`Substrate having an insulating Surface has been noted. The
`thin film transistor is widely applied to an electronic device
`Such as an IC or an electro-optical device and its develop
`ment as a Switching element of an image display device is
`particularly demanded.
`Conventionally, a liquid crystal display device is known
`as the image display device. Since a high resolution image
`is obtained as compared with a passive liquid crystal display
`device, an active matrix liquid crystal display device is used
`in many cases. According to the active matrix liquid crystal
`display device, when pixel electrodes arranged in matrix are
`driven, a display pattern is formed on a Screen. In more
`detail, when a Voltage is applied between a Selected pixel
`electrode and an opposite electrode corresponding to the
`Selected pixel electrode, a liquid crystal layer located
`between the pixel electrode and the opposite electrode is
`optically modulated and the optical modulation is recog
`nized as the display pattern by an observer.
`The range of use of Such an active matrix liquid crystal
`display device is increased. Demands for a higher resolution,
`a higher opening ratio, and high reliability are increased
`along with increase in a Screen size. Simultaneously,
`demands for improvement of productivity and cost reduction
`are also increased.
`Conventionally, when a TFT is manufactured using alu
`minum as a material of a gate wiring of the above-mentioned
`TFT, a protrusion such as hillock or a whisker is produced
`by thermal treatment and an aluminum atom is diffused to a
`channel forming region. Thus, an operation failure of the
`TFT and a deterioration of a TFT characteristic are caused.
`In order to Solve this, a metallic material which can be
`resistant to thermal treatment, typically, a metallic element
`having a high melting point is used. However, a problem in
`which a wiring resistance is increased due to increase in a
`Screen size arises, and increase in power consumption and
`the like are caused.
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`SUMMARY OF THE INVENTION
`Therefore, an object of the present invention is to provide
`a structure of a Semiconductor device in which low power
`
`65
`
`2
`consumption is realized even when a Screen size is
`increased, and a manufacturing method thereof
`According to the present invention, a gate electrode
`Structure is made to be a laminate Structure in which a
`material film containing mainly TaN or W is used as a first
`layer for preventing diffusion to a channel forming region,
`a low resistance material film containing mainly Al or Cu is
`used as a Second layer, and a material film containing mainly
`Ti is used as a third layer. Thus, a resistance of a wiring is
`reduced.
`According to a structure of the present invention disclosed
`in this specification, a Semiconductor device including a
`TFT which is composed of a semiconductor layer formed on
`an insulating Surface, an insulating film formed on the
`Semiconductor layer, and a gate electrode formed on the
`insulating film is characterized by comprising: a pixel por
`tion including a first n-channel TFT having a Source wiring
`made of the same material as the gate electrode, a driver
`circuit including a circuit which is composed of a Second
`n-channel TFT and a third n-channel TFT, and a terminal
`portion made of the Same material as the gate electrode.
`In the above-mentioned Structure, the gate electrode is
`characterized by having a laminate Structure of a material
`film containing mainly TaN (a first layer), a material film
`containing mainly Al (a Second layer), and a material film
`containing mainly Ti (a third layer). Also, the gate electrode
`is characterized by having a laminate Structure of a material
`film containing mainly W (a first layer), a material film
`containing mainly Al (a Second layer), and a material film
`containing mainly Ti (a third layer).
`According to Such agate electrode Structure, when an ICP
`(inductively coupled plasma) etching method is used, end
`portions of the gate electrode can be formed into a taper
`shape. Note that a taper angle in this specification indicates
`an angle formed by a horizontal Surface and a Side Surface
`of a material layer. Also, in this specification, a Side Surface
`having the taper angle is called a taper shape and a portion
`having the taper shape is called a taper portion.
`Also, in the above-mentioned Structure, the present inven
`tion is characterized in that the second n-channel TFT and
`the third n-channel TFT compose an EEMOS circuit or an
`EDMOS circuit. The driver circuit of the present invention
`is made from an NMOS circuit composed of only n-channel
`TFTs, and the TFTs of the pixel portion are also composed
`of n-channel TFTS. Thus, a proceSS is simplified. A general
`driver circuit is designed based on a CMOS circuit com
`posed of an n-channel Semiconductor element and a
`p-channel Semiconductor element, which are complemen
`tally combined with each other. However, according to the
`present invention, the driver circuit is composed of a com
`bination of only n-channel TFTs.
`Further, in order to achieve the above-mentioned
`Structure, according to a structure of the present invention,
`there is provided a method of manufacturing a Semiconduc
`tor device including a driver circuit, a pixel portion, and a
`terminal portion, which are located on an insulating Surface,
`the method comprising the Steps of
`forming a Semiconductor layer on the insulating Surface;
`forming a first insulating film on the Semiconductor layer;
`forming a gate electrode, a Source wiring of the pixel
`portion, and an electrode of the terminal portion on the
`first insulating film;
`adding an impurity element for providing an n-type to the
`Semiconductor layer using the gate electrode as a mask
`to form an n-type impurity region;
`
`Page 20 of 33
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`

`

`3
`etching the gate electrode to form a taper portion;
`forming a Second insulating film which covers the Source
`wiring of the pixel portion and the terminal portion; and
`forming a gate wiring and a Source wiring of the driver
`circuit on the Second insulating film.
`In the above-mentioned Structure, it is characterized in
`that, in the Step of forming the gate electrode, the Source
`wiring of the pixel portion, and the electrode of the terminal
`portion, a material film containing mainly TaN, a material
`film containing mainly Al, and a material film containing
`mainly Ti are formed to be laminated, and then etched using
`a mask to form the gate electrode, the Source wiring of the
`pixel portion, and the electrode of the terminal portion. Also,
`in the above-mentioned Structure, it is characterized in that,
`in the Step of forming the gate electrode, the Source wiring
`of the pixel portion, and the electrode of the terminal
`portion, a material film containing mainly W, a material film
`containing mainly Al, and a material film containing mainly
`Ti are formed to be laminated, and then etched using a mask
`to form the gate electrode, the Source wiring of the pixel
`portion, and the electrode of the terminal portion.
`Also, according to the present invention, a liquid crystal
`display device having the pixel portion and the driver circuit
`as described in the above-mentioned Structure or a light
`emitting device with an OLED having the pixel portion and
`the driver circuit as described in the above-mentioned Struc
`ture can be manufactured.
`Also, according to the present invention, Since a step of
`manufacturing a p-channel TFT is omitted, a manufacturing
`Step of a liquid crystal display device or a light emitting
`device is simplified and a manufacturing cost can be
`reduced.
`
`1O
`
`15
`
`25
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`In the accompanying drawings:
`FIGS. 1A to 1C show manufacturing steps of an
`AM-LCD;
`FIGS. 2A and 2B show manufacturing steps of the
`AM-LCD;
`FIG. 3 shows manufacturing steps of the AM-LCD;
`FIG. 4 is a top view of a pixel;
`FIG. 5 shows an appearance of a liquid crystal module,
`FIG. 6 is a croSS Sectional view of a transmission type
`liquid crystal display device;
`FIGS. 7A and 7B show structures of NMOS circuits;
`FIGS. 8A and 8B show structures of a shift resistor;
`FIG. 9 is a top view of a pixel portion of the present
`invention;
`FIG. 10 is a cross sectional view of the pixel portion of the
`present invention;
`FIGS. 11A to 11C show examples of electronic devices;
`FIGS. 12A and 12B show examples of electronic devices;
`FIG. 13 is an observation SEM picture after etching;
`FIG. 14 is an observation SEM picture after etching:
`FIG. 15 shows a relationship between reliability (20
`hours assurance voltage and 10-years assurance voltage) and
`a Lov length in a TFT of a driver circuit;
`FIGS. 16A and 16B are a top view of an EL module and
`a croSS Sectional view thereof, respectively;
`FIG. 17 is a cross sectional view of an EL module;
`FIG. 18 shows a structure of a gate side driver circuit;
`FIG. 19 is a timing chart of decoder input signals, and
`FIG. 20 shows a structure of a source side driver circuit.
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`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`An embodiment mode of the present invention will be
`described below.
`First, a base insulating film is formed on a Substrate and
`then a Semiconductor layer having a predetermined shape is
`formed by a first photolithography Step.
`Next, an insulating film (including a gate insulating film)
`covering the Semiconductor layer is formed. A first conduc
`tive film, a Second conductive film, and a third conductive
`film are laminated on the insulating film. First etching
`processing is performed for the laminated films by a Second
`photolithography Step to form a gate electrode made from a
`first conductive layer and a Second conductive layer, a
`Source wiring of a pixel portion, and an electrode of a
`terminal portion. Note that, in the present invention, after the
`gate electrode is formed, a gate wiring is formed on an
`interlayer insulating film.
`Next, with a state in which a resist mask formed in the
`Second photolithography Step is left as it is, an impurity
`element (phosphorus or the like) for providing an n-type is
`added to the Semiconductor layer to form n-type impurity
`regions (having high concentrations) in self alignment.
`Next, with a state in which the resist mask formed in the
`Second photolithography Step is left as it is, an etching
`condition is changed and Second etching processing is
`performed to form a first conductive layer (first width), a
`Second conductive layer (Second width), and a third con
`ductive layer (third width), which have taper portions. Note
`that the first width is wider than the second width, and the
`Second width is wider than the third width. Here, an elec
`trode composed of the first conductive layer, the second
`conductive layer, and the third conductive layer becomes a
`gate electrode of an n-channel TFT (first gate electrode).
`A material film containing mainly TaN or W may be used
`as the first conductive layer which is in contact with the
`insulating film in order to prevent diffusion to a channel
`forming region. Also, a low resistance material film con
`taining mainly Al or Cu may be used as the Second conduc
`tive layer. Further, a material film containing mainly Ti,
`which has a low contact resistance, may be used as the third
`conductive layer.
`Next, after the resist mask is removed, an impurity
`element for providing an n-type is added to the Semicon
`ductor layer through the insulating film using the first gate
`electrode as a mask.
`After that, a resist mask is formed by a third photolithog
`raphy method (step) and an impurity element for providing
`an n-type is Selectively added in order to reduce an off
`current of a TFT in the pixel portion.
`Next, an interlayer insulating film is formed and a trans
`parent conductive film is formed thereon. The transparent
`conductive film is patterned by a fourth photolithography
`method (step) to form a pixel electrode. Then, contact holes
`are formed by a fifth photolithography Step. Here, contact
`holes which reach impurity regions, a contact hole which
`reaches the gate electrode, and a contact hole which reaches
`a Source wiring are formed.
`Next, a conductive film made of a low resistance metallic
`material is formed. A gate wiring, an electrode for connect
`ing the Source wiring and the impurity region, and an
`electrode for connecting the pixel electrode and the impurity
`region are formed by a sixth photolithography Step. In the
`present invention, the gate wiring is electrically connected
`with the first gate electrode or a Second gate electrode
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`S
`through a contact hole provided in the interlayer insulating
`film. Also, the Source wiring is electrically connected with
`the impurity region (Source region) through a contact hole
`provided in the interlayer insulating film. Further, the elec
`trode connected with the pixel electrode is electrically
`connected with the impurity region (drain region) through a
`contact hole provided in the interlayer insulating film.
`Thus, an element Substrate including a pixel portion
`having a pixel TFT (n-channel TFT) and a driver circuit
`having an EEMOS circuit (n-channel TFTs) as shown in
`FIG. 7A can be formed by performing a photolithography
`Step for Six times in total, that is, by using Six masks. Note
`that the example in which a transmission type display device
`is manufactured is indicated here. However, a reflection type
`display device can be also manufactured using a material
`having a high reflecting property for the pixel electrode.
`When the reflection type display device is manufactured,
`Since the pixel electrode can be formed being Simultaneous
`with the gate wiring, the element Substrate can be formed by
`using five maskS.
`Also, an active matrix light emitting device having an
`OLED (organic light emitting device) can be manufactured.
`Even in case of the light emitting device, the whole driver
`circuit is composed of n-channel TFTS and the pixel portion
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`is also composed of a plurality of n-channel TFTs. In the
`light emitting device employing the OLED, at least a TFT
`which functions as a Switching element and a TFT for
`Supplying a current to the OLED are provided in each pixel.
`Irrespective of a circuit structure of a pixel and a driving
`method, a TFT which is electrically connected with the
`OLED and Supplies a current thereto is made to be an
`n-channel TFT,
`The OLED has a layer including an organic compound
`(organic light emitting material) in which luminescence
`produced by applying an electric field thereto (electro
`luminescence) is obtained (hereinafter referred to as an
`organic light emitting layer), an anode, and a cathode. The
`luminescence in the organic compound includes light emis
`Sion produced when it is returned from a Singlet excitation
`State to a ground State (fluorescence) and light emission
`produced when it is returned from a triplet excitation-state to
`a ground State (phosphorescence). In case of the light
`emitting device of the present invention, of the above
`mentioned light emissions, either light emission may be
`used or both the light emissions may be used.
`Note that in this specification, all layers formed between
`the anode and the cathode in the OLED are defined as an
`organic light emitting layer. Concretely, the organic light
`emitting layer includes a light emitting layer, a hole injection
`layer, an electron injection layer, a hole transport layer, and
`an electron transport layer. Basically, the OLED has a
`Structure in which the anode, the light emitting layer, and the
`cathode are laminated in order. In addition to this structure,
`there is a case where the OLED has a structure in which the
`anode, the hole injection layer, the light emitting layer, and
`the cathode are laminated in order or a structure in which the
`anode, the hole injection layer, the light emitting layer, the
`electron transport layer, and the cathode are laminated in
`order.
`Also, when an EDMOS circuit as shown in FIG. 7B is
`formed by combining an enhancement type and a depletion
`type, before the formation of the conductive film, a mask is
`formed in advance, and an element belonging to the group
`15 of the periodic table (preferably, phosphorus) or an
`element belonging to the group 13 of the periodic table
`(preferably, boron) may be selectively added to the semi
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`conductor layer which is to be the channel forming region.
`In this case, the element Substrate can be formed by using
`Seven maskS.
`Also, description has been made using the n-channel TFT
`here. However, it goes without Saying that a p-channel TFT
`can be formed by using a p-type impurity element instead of
`the n-type impurity element. In this case, the whole driver
`circuit is composed of p-channel TFTS and the pixel portion
`is also composed of the p-channel TFTs.
`The present invention made by the above structure will be
`described in more detail based on the following embodi
`mentS.
`
`Embodiment
`
`Embodiment 1
`An embodiment of the present invention will be described
`using FIGS. 1A to 1C to FIG. 6. Here, a method of
`Simultaneously manufacturing TFTS composing a pixel por
`tion and TFTs (only n-channel TFTs) composing a driver
`circuit provided in a periphery of the pixel portion on the
`same Substrate will be described in detail.
`In FIG. 1A, a glass Substrate, a quartz Substrate, a ceramic
`Substrate, or the like can be used as a Substrate 100. Asilicon
`Substrate, a metallic Substrate, or a stainless Substrate, in
`which an insulating film is formed on the Surface, may also
`be used. Also, a plastic Substrate having a heat resistance,
`which is resistant to a processing temperature in this
`embodiment may be used.
`Then, as shown in FIG. 1A, a base insulating film 101
`made from an insulating film Such as a Silicon oxide film, a
`silicon nitride film, or a silicon oxynitride film (SiO.N.) is
`formed on the substrate 100. As a typical example, a
`laminate structure is used in which a two-layered structure
`is used for the base insulating film 101, and a first silicon
`oxynitride film 101a is formed with a thickness of 50 nm to
`100 nm using SiH, NH, and N2O as reactive gases and a
`second silicon oxynitride film 101b is formed with a thick
`ness of 100 nm to 150 nm using SiH, and NO as reactive
`gases. Also, a Silicon nitride film having a film thickness of
`10 nm or less may be used as the base insulating film 101.
`When the silicon nitride film is used, it has an effect of
`improving gettering efficiency in a gettering Step which will
`be performed later in addition to an effect Such as a blocking
`layer. Nickel tends to move to a region having a high oxygen
`concentration at gettering. Thus, it is extremely effective to
`use the Silicon nitride film as the base insulating film which
`is in contact with a Semiconductor film. Also, a three-layered
`structure may be used in which the first silicon oxynitride
`film, the Second Silicon oxynitride film, and the Silicon
`nitride film are laminated in order.
`The Semiconductor film as an active layer is obtained by
`crystallizing an amorphous Semiconductor film formed on
`the base insulating film 101. The amorphous semiconductor
`film is formed with a thickness of 30 nm to 60 nm. After that,
`a metallic element (nickel in this embodiment) having a
`catalytic action for promoting crystallization is used and a
`nickel acetate Solution including nickel at 1 ppm to 100 ppm
`in weight conversion is applied onto the Surface of the
`amorphous Semiconductor film with a Spinner to form a
`catalytic contained layer.
`With keeping a State in which the amorphous Semicon
`ductor film is in contact with the catalytic element contained
`layer, thermal treatment for crystallization is performed. In
`this embodiment, the thermal treatment is performed by an
`RTA method. A lamp light Source for heating is tuned on for
`1 second to 60 seconds, preferably, 30 seconds to 60 seconds
`and this operation is repeated for 1 time to 10 times,
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`preferably, for 2 times to 6 times. Although the light emis
`Sion intensity of the lamp light Source is Set to be an arbitrary
`intensity, the Semiconductor film is heated So as to be
`instantaneously heated at 600 C. to 1000 C., preferably,
`about 650 C. to 750° C. Even if such a high temperature is
`obtained, the Semiconductor film is just heated in a moment
`and there is no case where the Substrate 100 itself is distorted
`and deformed. In this way, the amorphous Semiconductor
`film can be crystallized to obtain the crystalline Semicon
`ductor film.
`In order to increase a crystallization ratio (a percentage of
`crystalline components in the entire Volume of the film)
`further and to repair a defect left in a crystal grain, laser light
`is irradiated to the crystalline Semiconductor film. AS the
`laser light, excimer laser light having a wavelength of 400
`nm or less, a Second harmonic of a YAG laser, or a third
`harmonic thereof can be also used. In any of the cases, pulse
`laser light having a repetition frequency of about 10 HZ to
`1000 Hz is used, the laser light is condensed to be 100
`mJ/cm to 400 m.J/cm by an optical system, and laser
`processing for a crystalline Semiconductor film 104 may be
`performed at an overlap ratio of 90% to 95%.
`Note that an example using the pulse laser is indicated
`here. However, a continuous Oscillation laser may also be
`used. In order to obtain a crystal with a large grain size at
`crystallization of the amorphous Semiconductor film, it is
`preferable that a Solid laser capable of producing continuous
`oscillation is used and one of a Second harmonic to a fourth
`harmonic of a fundamental wave is applied. Typically, a
`second harmonic (532 nm) or a third harmonic (355 nm) of
`an Nd:YVO laser (fundamental wave: 1064 nm) may be
`applied. When the continuous oscillation laser is used, laser
`light emitted from the continuous oscillation YVO laser
`having an output of 10 W is converted into a harmonic by
`a non-linear optical element. Also, there is a method of
`locating a YVO crystal and a non-linear optical element in
`a resonator and emitting a harmonic. Then, laser light is
`preferably formed into a rectangular shape or an elliptical
`shape on an irradiating Surface by an optical System and
`irradiated to an object to be processed. At this time, an
`energy density of about 0.01 MW/cm° to 100 MW/cm
`(preferably, 0.1 MW/cm to 10 MW/cm) is required. Then,
`the semiconductor film may be moved relatively to laser
`light at a speed of about 10 cm/s to 2000 cm/s to be
`irradiated.
`Note that a technique for irradiating laser light after
`thermal crystallization using nickel as a metallic element for
`promoting crystallization of Silicon is used here. However,
`an amorphous Silicon film may be crystallized by the con
`tinuous oscillation laser (the second harmonic of the YVO
`laser) without adding nickel thereto.
`Next, the following gettering processing is performed to
`remove a catalytic element included in the crystalline Semi
`conductor film. A barrier layer is formed on the crystalline
`Semiconductor film. AS the barrier layer, a porous film is
`formed Such that the catalytic element (nickel) can be
`moved to a gettering cite by thermal treatment and further an
`etching Solution used in a step of removing the gettering cite
`does not penetrate. For example, a chemical oxide film
`formed by processing using OZone water or a Silicon oxide
`(SiO) film may be used. In this specification, a film having
`Such a property is particularly called a porous film.
`Next, a Semiconductor film including a noble gas element
`is formed as a gettering cite. In this embodiment, at a stage
`of