PA-RISC 2.0
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`PA-RISC 2.0
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`Oracle-1044 p. 1
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`The information contained in this document is subject to change without notice.
`HEWLETT-PACKARD MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS
`MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
`MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
`Hewlett-Packard shall not be liable for errors contained herein or for incidental or consequential
`damages in connection with furnishing, performance, or use of this material.
`Hewlett-Packard assumes no responsibility for the use or reliability of its software on equipment that is
`not furnished by Hewlett-Packard.
`This document contains proprietary information which is protected by copyright. All rights
`are reserved. No part of this document may be photocopied, reproduced, or translated to another
`language without the prior written consent of Hewlett-Packard Company.
`Copyright © 1995 by HEWLETT-PACKARD COMPANY
`
`Published by Prentice-Hall, Inc.
`A Simon & Schuster Company
`Englewood Cliffs, New Jersey 07632
`
`Book Design: Suzanne Hayes
`
`Acknowledgements
`
`Special thanks to Martin Whittaker who was the impetus behind this book and provided leadership and
`direction at every turn and to Dale Morris and Jim Hall who contributed key sections. Many other folks
`at Hewlett-Packard provided critical information: among them Ruby Lee, and Jerry Huck.
`Personal thanks go to the usual suspects: Sean, Kyle, Ambrose, Marcella.
`
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`Foreword
`
`“Everything should be made as simple as possible, but not simpler.”
`
`A. Einstein
`
`When the first PA-RISC systems were shipped in 1986, the architecture was clearly recognized as a
`break with the past, with regular, hardware-inspired instructions rather than variable, interpretive forms.
`But its simple instructions were somewhat richer than other RISC designs, providing basic support for
`operations on strings and other data types prevalent in commercial applications. This semantic richness,
`unusual in the RISC designs of the time, was a direct result of the breadth of markets for HP computers
`and the decision to optimize PA-RISC for the full range of technical and commercial applications.
`In the intervening years, PA-RISC has become the basis of a large family of computer systems,
`currently spanning a capacity range of over two orders of magnitude. As the product family has grown,
`the range of applications has also expanded geometrically. PA-RISC workstations now host applications
`which were once the province of supercomputers. Database servers now supply realtime streams of
`compressed video and audio. And PA-RISC has evolved to meet the demands for leadership
`performance in these emerging application domains.
`The purpose of a processor architecture is to define a stable interface which can efficiently couple
`multiple generations of software investment to successive generations of hardware technology. Stability
`and efficiency are the goals, and the range of software and hardware technologies expected during the
`architecture’s life determine the scope for which the goals must be achieved.
`The desired stability does not rule out change, but it does require that any evolution of the architecture
`contain the prior definition as a subset. This is the principle of “forward compatibility” which ensures
`that all prior software will continue to work on all later machines⎯a straightforward idea whose value
`to users is obvious. Over the last decade, PA-RISC has evolved in response both to significant changes
`in the nature of customer applications and to rapid advances in technology, particularly chip fabrication
`technology and compiler technology.
`Efficiency also has evident value to users, but there is no simple recipe for achieving it. Optimizing
`architectural efficiency is a complex search in a multidimensional space, involving disciplines ranging
`from device physics and circuit design at the lower levels of abstraction, to compiler optimizations and
`application structure at the upper levels.
`Because of the inherent complexity of the problem, the design of processor architecture is an iterative,
`heuristic process which depends upon methodical comparison of alternatives (“hill climbing”) and upon
`creative flashes of insight (“peak jumping”), guided by engineering judgement and good taste.
`To design an efficient processor architecture, then, one needs excellent tools and measurements for
`accurate comparisons when “hill climbing,” and the most creative and experienced designers for
`superior “peak jumping.” At HP, this need is met within a cross-functional team of about twenty
`designers, each with depth in one or more technologies, all guided by a broad vision of the system as a
`whole.
`Since the inception of PA-RISC, nearly fifty people have contributed directly to its definition as
`
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`members of the architecture team. With the generous support of colleagues and managers in their
`respective organizations, they have made careful measurements of application workloads, designed
`ingenious tools and methods to analyze data, created novel semantics and encodings, deliberated
`intently to hone the best cost-performance design, and crafted clear, unambiguous descriptions. It was
`my great privilege and pleasure to lead this team of talented designers, and it is their achievement which
`is documented in this book.
`
`⎯ Michael Mahon
`Principal Architect
`Hewlett-Packard
`August, 1995
`
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`Contents
`
`2
`
`Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
`Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
`Preface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv
`Compatibility with PA-RISC 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv
`PA-RISC 2.0 Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv
`How This Book is Organized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii
`Conventions Used in This Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii
`Instruction Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xviii
`1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
`Traditional RISC Characteristics of PA-RISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
`PA-RISC - The Genius is in the Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2
`A Critical Calculus: Instruction Pathlength. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2
`Multimedia Support: The Precision Process Illustrated . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
`Integrated CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7
`Extensibility and Longevity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9
`System Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-10
`Processing Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
`Non-Privileged Software-Accessible Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
`Privileged Software-Accessible Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
`Unused Registers and Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-17
`Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-18
`Byte Ordering (Big Endian/Little Endian) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-19
`3 Addressing and Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
`Physical and Absolute Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
`Virtual Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5
`Pointers and Address Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6
`Address Resolution and the TLB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
`Access Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11
`Page Table Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15
`Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16
`4 Control Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
`Branching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
`Nullification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7
`Instruction Execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7
`Instruction Pipelining. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9
`Interruptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
`Interrupt Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
`Interruption Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
`Instruction Recoverability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3
`Masking and Nesting of Interruptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4
`Interruption Priorities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4
`Return from Interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4
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`6
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`7
`8
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`Interruption Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
`Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
`Computation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
`Multimedia Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
`Memory Reference Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
`Long Immediate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
`Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
`System Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
`Assist Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
`Conditions and Control Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
`Additional Notes on the Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
`Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
`Floating-point Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
`The IEEE Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
`The Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
`Coprocessor Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
`Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
`Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
`Floating-Point Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
`Floating-Point Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
`Floating-Point Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
`9
`10 Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
`Exception Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
`Interruptions and Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
`Saving and Restoring State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
`11 Performance Monitor Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
`Performance Monitor Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
`Performance Monitor Interruptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
`Monitor Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
`A Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
`B Instruction Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-1
`C Operation Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-1
`Major Opcode Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-1
`Opcode Extension Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-3
`D Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1
`Arithmetic/Logical Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1
`Unit Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-7
`Shift/Extract/Deposit Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-8
`Branch On Bit Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-9
`E Instruction Notation Control Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E-1
`F
`TLB and Cache Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-1
`TLB Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-1
`TLB Operation Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-3
`Address Aliasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-5
`Cache Move-in Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-7
`Cache Coherence with I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-11
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`I
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`Cache and TLB Coherence in Multiprocessor Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . F-12
`G Memory Ordering Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-1
`Atomicity of Storage Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-1
`Ordering of References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-1
`Completion of Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-6
`Formal Memory Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-7
`H Address Formation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-1
`Memory Reference Instruction Address Formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-1
`Absolute Address Formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-9
`Programming Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-1
`Privilege Level Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-1
`Testing the Current State of the PSW W-Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-2
`Procedure Call and Return. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-3
`Static Branch Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-3
`Return from Interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-5
`Trap Handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-5
`Reserved-op Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-6
`Endian Byte Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-6
`PA-RISC 2 Instruction Completers
` & Pseudo-Ops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .J-1
`PA-RISC 2 Instruction Completers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .J-1
`Pseudo-Op Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .J-3
`Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IN-1
`
`J
`
`PA-RISC 2.0 Architecture
`
`vii
`
`Oracle-1044 p. 7
`Oracle v. Teleputers
`IPR2021-00078
`
`

`

`viii
`
`PA-RISC 2.0 Architecture
`
`Oracle-1044 p. 8
`Oracle v. Teleputers
`IPR2021-00078
`
`

`

`Figures
`
`PA-RISC Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
`Figure 1-1.
`Processor Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-11
`Figure 1-2.
`Memory Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-12
`Figure 1-3.
`Software Accessible Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
`Figure 2-1.
`General Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
`Figure 2-2.
`Example Space Register Usage Convention . . . . . . . . . . . . . . . . . . . . . 2-4
`Figure 2-3.
`Instruction Address Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
`Figure 2-4.
`Branch Target Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
`Figure 2-5.
`Branch Nomination Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
`Figure 2-6.
`Processor Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
`Figure 2-7.
`Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11
`Figure 2-8.
`Interruption Instruction Address Queues with Wide Virtual Addresses . . . . . . .2-14
`Figure 2-9.
`Interruption Instruction Address Queues with Narrow Virtual Addresses . . . . . .2-14
`Figure 2-10.
`Interruption Instruction Address Queues with Absolute Addresses . . . . . . . . .2-14
`Figure 2-11.
`Reforming Space Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-15
`Figure 2-12.
`Interruption Space and Offset Registers with Virtual Address . . . . . . . . . . . .2-16
`Figure 2-13.
`Interruption Space and Offset Registers with Absolute Address . . . . . . . . . . .2-16
`Figure 2-14.
`Big Endian Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-20
`Figure 2-15.
`Little Endian Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-20
`Figure 2-16.
`64-bit Physical Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
`Figure 3-1.
`n-bit Physical Address Space Implementation . . . . . . . . . . . . . . . . . . . . 3-3
`Figure 3-2.
`62-bit Absolute Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
`Figure 3-3.
`32-bit Absolute Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
`Figure 3-4.
`Physical Memory Addressing and Storage Units . . . . . . . . . . . . . . . . . . . 3-4
`Figure 3-5.
`Global Virtual Address Formation . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
`Figure 3-6.
`Structure of the Virtual Address Space . . . . . . . . . . . . . . . . . . . . . . . . 3-6
`Figure 3-7.
`Space Identifier Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
`Figure 3-8.
`TLB Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10
`Figure 3-9.
`Protection ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12
`Figure 3-10.
`Figure 3-11. Access Rights Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13
`Figure 3-12. Access Control Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15
`Figure 3-13.
`Page Table Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16
`Figure 4-1.
`Delayed Branching Illustrated . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
`Figure 4-2.
`Updating Instruction Address Queues . . . . . . . . . . . . . . . . . . . . . . . . 4-4
`Figure 4-3.
`Branch in the Delay slot of a Branch . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
`Figure 4-4.
`Interruption Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
`Figure 6-1.
`Example Address Formation for Memory Reference Instructions . . . . . . . . . . 6-9
`Figure 6-2.
`Immediate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-13
`Figure 6-3.
`Classification of Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .6-17
`Figure 6-4.
`System Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-19
`Figure 7-1.
`Instruction Description Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
`Figure 8-1.
`Single-word Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
`
`PA-RISC 2.0 Architecture
`
`ix
`
`Oracle-1044 p. 9
`Oracle v. Teleputers
`IPR2021-00078
`
`

`

`Figure 8-2.
`Figure 8-3.
`Figure 8-4.
`Figure 8-5.
`Figure 8-6.
`Figure 8-7.
`Figure 8-8.
`Figure 8-9.
`Figure 10-1.
`Figure 10-2.
`Figure C-1.
`Figure C-2.
`Figure C-3.
`Figure C-4.
`Figure C-5.
`Figure C-6.
`Figure C-7.
`Figure C-8.
`Figure C-9.
`Figure C-10.
`Figure C-11.
`Figure C-12.
`Figure C-13.
`Figure C-14.
`Figure C-15.
`Figure C-16.
`Figure H-1.
`Figure H-2.
`Figure H-3.
`Figure H-4.
`Figure H-5.
`Figure H-6.
`Figure H-7.
`Figure H-8.
`Figure H-9.
`Figure H-10.
`Figure H-11.
`
`Double-word Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
`Quad-word Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
`Floating-point Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
`Fixed-point Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
`Floating-Point Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
`Single-operation Instruction Formats . . . . . . . . . . . . . . . . . . . . . . . . 8-14
`Fused-Operation Instruction Format. . . . . . . . . . . . . . . . . . . . . . . . . 8-18
`Multiple-Operation Instruction Format . . . . . . . . . . . . . . . . . . . . . . . 8-19
`Floating-Point Exception Register Format . . . . . . . . . . . . . . . . . . . . . 10-2
`Exception Field Underflow Parameters . . . . . . . . . . . . . . . . . . . . . . 10-13
`Format for System Control Instructions . . . . . . . . . . . . . . . . . . . . . . . .C-3
`Formats for Memory Management Instructions . . . . . . . . . . . . . . . . . . . .C-5
`Format for Arithmetic/Logical Instructions . . . . . . . . . . . . . . . . . . . . . .C-7
`Formats for Indexed and Short Displacement Load/Store Instructions . . . . . . . .C-9
`Format for Load/Store Doubleword Instructions . . . . . . . . . . . . . . . . . . C-11
`Format for Load/Store Word Instructions . . . . . . . . . . . . . . . . . . . . . . C-12
`Format for Arithmetic Immediate Instructions . . . . . . . . . . . . . . . . . . . C-13
`Formats for Shift, Extract, and Deposit Instructions . . . . . . . . . . . . . . . . C-14
`Formats for Multimedia Instructions . . . . . . . . . . . . . . . . . . . . . . . . C-16
`Formats for Unconditional Branch Instructions . . . . . . . . . . . . . . . . . . . C-17
`Formats for Coprocessor Load/Store Instructions . . . . . . . . . . . . . . . . . . C-18
`Formats for Special Function Unit (SFU) Instructions . . . . . . . . . . . . . . . C-19
`Formats for Floating-Point Operations - Major Opcode 0C . . . . . . . . . . . . . C-20
`Formats for Floating-Point Operations - Major Opcode 0E . . . . . . . . . . . . . C-22
`Format for Floating-Point Fused-Operation Instructions . . . . . . . . . . . . . . C-24
`Format for Performance Monitor Coprocessor Instructions . . . . . . . . . . . . . C-25
`Space Identifier Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-2
`Offset computation with long displacement . . . . . . . . . . . . . . . . . . . . . H-3
`Global Virtual Address Formation. . . . . . . . . . . . . . . . . . . . . . . . . . H-3
`Offset computation with short displacement . . . . . . . . . . . . . . . . . . . . H-5
`Offset computation for Store Bytes and Store Doubleword Bytes . . . . . . . . . H-7
`Offset computation with indexed addressing . . . . . . . . . . . . . . . . . . . . H-9
`62-bit Absolute Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-10
`62-bit Absolute Accesses when PSW W-bit is 1 . . . . . . . . . . . . . . . . . . H-11
`32-bit Absolute Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-11
`32-bit Absolute Accesses when PSW W-bit is 0 . . . . . . . . . . . . . . . . . . H-12
`Physical Address Space Mapping - An Example . . . . . . . . . . . . . . . . . . H-13
`
`x
`
`PA-RISC 2.0 Architecture
`
`Oracle-1044 p. 10
`Oracle v. Teleputers
`IPR2021-00078
`
`

`

`Tables
`
`Processor Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
`Table 2-1.
`Page Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11
`Table 3-1.
`Access Rights Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
`Table 3-2.
`Computation Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
`Table 6-1.
`Multimedia Instruction Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
`Table 6-2.
`Signed Saturation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
`Table 6-3.
`Unsigned Saturation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
`Table 6-4.
`Memory Reference Instruction Summary. . . . . . . . . . . . . . . . . . . . . . . 6-6
`Table 6-5.
`Address Formation Options for Memory Reference Instructions. . . . . . . . . . . 6-8
`Table 6-6.
`Load Instruction Cache Control Hints . . . . . . . . . . . . . . . . . . . . . . . .6-10
`Table 6-7.
`Store Instruction Cache Control Hints . . . . . . . . . . . . . . . . . . . . . . . .6-10
`Table 6-8.
`Load And Clear Word Instruction Cache Control Hints . . . . . . . . . . . . . . .6-11
`Table 6-9.
`Data Prefetch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-11
`Table 6-10.
`Immediate Instruction Summary . . . . . . . . . . . . . . . . .