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`A Crypto-Engine. - Google Scholar
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`Design of a reconfigurable AES encryption/decryption engine for mobile terminals
`T Pionteck, T Staake, T Stiefmeier… - … on Circuits and …, 2004 - ieeexplore.ieee.org
`… The re- configurable crypto-engine is integrated as a function unit in a 32 bit RISC processor
`and can operate in parallel with the standard ALU … The RISC processor with the crypto-engine
`was synthesized using a 0.25 m CMOS technology. 1. INTRODUCTION …
`
` Cited by 46 Related articles All 6 versions
`A low-cost and high efficiency architecture of AES crypto-engine
`YQ Zhong, JM Wang, ZF Zhao… - … on Communications and …, 2007 - ieeexplore.ieee.org
`… AES Crypto-engine Yan Qing. Zhong*, Jian Ming … Further more, AES Encryptor and Decryptor
`is integrated into a full functional crypto-engine. This very low-cost and high efficiency AES core
`of IEEE 802.15.4-2006 is designed and emulated on Xilinx FPGA …
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` Cited by 13 Related articles All 4 versions
`Side channel analysis of AVR XMEGA crypto engine
`I Kizhvatov - Proceedings of the 4th Workshop on Embedded …, 2009 - dl.acm.org
`Page 1. Side Channel Analysis of AVR XMEGA Crypto Engine Ilya … attack. Our analysis
`was performed without knowing the details of the crypto engine internals; quite the
`contrary, it reveals some details about the implementation …
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` Cited by 27 Related articles All 2 versions
`A crypto-engine
`GI Davida, FB Dancs - Conference on the Theory and Application of …, 1987 - Springer
`In this paper we present a design for a crypto-engine. We shall discuss the design and show
`the instruction set of this coprocessor and then show how this could be used to implement
`most of the known encryption algorithms. We will discuss why a coprocessor approach may …
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` Cited by 5 Related articles All 5 versions
`Method for managing a buffer memory in a crypto engine
`WL Chin - US Patent App. 10/707,381, 2005 - Google Patents
`A method for managing a buffer memory in a crypto engine includes defining an
`IO writing address, a program reading address, a program writing address, and an
`IO reading address in the buffer memory. Input data is written …
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` Cited by 5 Related articles All 2 versions
`A low cost and inner-round pipelined design of ECB-AES-256 crypto engine for solid state disk
`F Wu, L Wang, J Wan - 2010 IEEE Fifth International …, 2010 - ieeexplore.ieee.org
`Page 1. A low cost and inner-round pipelined design of ECB-AES-256 crypto engine
`for Solid State Disk Fei Wu, Liang Wang, Jiguang … 1.0 interface. Keywords-SSD;
`inner-round; ECB-AES-256 crypto engine I. INTRODUCTION Compared …
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` Cited by 13 Related articles All 6 versions
`Compact crypto-engine for random number and stream cipher generation
`LM Cheng, CK Chan, CK Chan - US Patent 7,003,109, 2006 - Google Patents
`US7003109B2 - Compact crypto-engine for random number and stream cipher generation -
`Google Patents. Compact crypto-engine for random number and stream cipher generation.
`Download PDF Info … FIG. 2 illustrates the structure of the Crypto-engine; FIG …
`
` Cited by 9 Related articles All 6 versions
`A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-
`gate CMOS
`T Karnik, D Kurian, P Aseron… - … Solid-State Circuits …, 2018 - ieeexplore.ieee.org
`… voltage (NTV) for maximum energy efficiency; (ii) an efficient 600K-transistor convolutional neural
`network (CNN) accelerator, as part of a CNN-based 1.04M-transistor visual recognition and
`classification engine; (iii) a 70K-transistor lightweight crypto engine for secure boot and …
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` Cited by 32 Related articles
`Crypto-engine for cryptographic processing of data
`LM Cheng, TO Ngan, KW Hau - US Patent 7,634,666, 2009 - Google Patents
`US7634666B2 - Crypto-engine for cryptographic processing of data - Google Patents.
`Crypto-engine for cryptographic processing of data. Download PDF Info … It is a further object of
`the invention to provide a crypto-engine that operates as a coprocessor to a host processor …
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` Cited by 6 Related articles All 4 versions
`A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence
`PC Liu, JH Hsiao, HC Chang… - 2011 Proceedings of the …, 2011 - ieeexplore.ieee.org
`… Abstract—This paper presents a DPA-resistant AES crypto engine … The cell area for
`the DPA- resistant AES crypto engine is 0.104 mm2 in UMC 90 nm CMOS technology,
`which is only 6.2% larger than an unprotected AES engine …
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` Cited by 16 Related articles All 4 versions
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`buffer memory crypto engine
`random number crypto engine
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`A Crypto-Engine. - Google Scholar
`pipelined design crypto engine
`state disk crypto engine
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`Davida: A crypto-engine - Google Scholar
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`A crypto-engine
`Search within citing articles
`Experimental testing of the gigabit IPSec-Compliant implementations of Rijndael and triple DES using
`SLAAC-1V FPGA accelerator board
`P Chodowiec, K Gaj, P Bellows, B Schott - International Conference on …, 2001 - Springer
`In this paper, we present the results of the first phase of a project aimed at implementing a
`full suite of IPSec cryptographic transformations in reconfigurable hardware. Full
`implementations of the new Advanced Encryption Standard, Rijndael, and the older …
`
` Cited by 76 Related articles All 19 versions
`Cryptography based data security
`GI Davida, Y Desmedt - Advances in computers, 1990 - Elsevier
`Publisher Summary The chapter discusses the types of data security problems. The
`categories where data protections are falling are physical security, communication security,
`and operational security (database security, operating security, computer viruses) …
`
` Cited by 4 Related articles All 3 versions
`DES 의 고속 암호화를 위한 파이프라인 구조
`박태규, 황대준 - 정보보호학회논문지, 1993 - dbpia.co.kr
`요 약 DES 암호 알고리즘에서 빈번하게 사용되는 치환연산과 대치연산은 병렬로 처리될 수
`있으며, 암호화의 16 회 반복 과정을 긴 선형 파이프라인으로 모두 펼쳐 구성할 수 있다. 따라서
`본 논문에서는치환 및 대치연산의 병렬처리, 파이프라인 처리가 가능한 구분화된 암호화 전용 …
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` Cited by 3 Related articles
`GEORGE I. DAVIDA
`YVO DESMEDT - Advances in Computers, 1990 - Academic Press
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` Related articles
`Cryptography Based Data Security
`YVO DESMEDT - Advances in Computers, 1990 - books.google.com
`Protection of data in computer systems continues to pose challenges to designers,
`researchers and system managers. The amount of different types of data that are created,
`processed and maintained by computer systems keeps increasing with no foreseeable limit …
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` Related articles
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`https://scholar.google.com/scholar?cites=12828605588332510717&as_sdt=2005&sciodt=0,5&hl=en
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