IPR2021-00078, Declaration of Donald Alpert, Ph.D.
`In Support of Inter Partes Review of U.S. Patent 7,174,014
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`ORACLE CORPORATION and
`ORACLE AMERICA, INC.,
`Petitioners
`
`v.
`
`TELEPUTERS, LLC,
`Patent Owner
`
`U.S. Patent No. 7,174,014
`Issue Date: February 6, 2007
`Title: METHOD AND SYSTEM FOR PERFORMING
`PERMUTATION WITH BIT PERMUTATION
`INSTRUCTIONS
`
`Case No. IPR2021-00078
`
`DECLARATION OF DONALD ALPERT, PH.D. IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 7,174,014
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`United States Patent and Trademark Office
`PO Box 1450
`Alexandria, Virginia 22313–1450
`
`4152-0740-7912
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`IPR2021-00078, Declaration of Donald Alpert, Ph.D.
`In Support of Inter Partes Review of U.S. Patent 7,174,014
`
`TABLE OF CONTENTS
`
`Page
`INTRODUCTION .......................................................................................... 1
`I.
`II. QUALIFICATIONS ....................................................................................... 2
`III. MATERIALS RELIED UPON IN FORMING MY OPINIONS .................. 6
`IV. PRIORITY DATE AND LEVEL OF ORDINARY SKILL .......................... 8
`V. UNDERSTANDING OF GOVERNING LAW ........................................... 10
`VI. OVERVIEW OF THE TECHNOLOGY ...................................................... 14
`A.
`Instructions and Processors ................................................................ 14
`B.
`Permutation Instructions in Cryptography ......................................... 18
`C.
`Permutation Instructions in Digital Multimedia ................................ 20
`VII. THE ’014 PATENT ...................................................................................... 22
`A.
`Summary of the ’014 Patent and Its Prosecution History .................. 22
`B.
`Secondary Considerations of Non-Obviousness ................................ 28
`VIII. CLAIM CONSTRUCTIONS ....................................................................... 28
`A.
`PPERM ............................................................................................... 31
`B.
`PPERM3R .......................................................................................... 35
`IX. THE PRIOR ART ......................................................................................... 36
`A.
`“A Crypto-Engine” by Dr. George Davida (“Davida”) ..................... 36
`B. WIPO Patent Application No. WO 97/07451 (“Microunity”) ........... 40
`C. U.S. Patent No. 6,192,467 (“Abdallah”) ............................................ 43
`D. U.S. Patent No. 6,334,183 (“Blomgren”) ........................................... 45
`X. OBVIOUSNESS OF THE CHALLENGED CLAIMS ................................ 45
`A.
`Claim 33 (Independent): ..................................................................... 46
`1.
`[33.0] “A computer implemented method for performing
`an arbitrary permutation of a sequence of bits comprising
`the steps of:” ............................................................................. 46
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`IPR2021-00078, Declaration of Donald Alpert, Ph.D.
`In Support of Inter Partes Review of U.S. Patent 7,174,014
`
`2.
`
`3.
`
`4.
`
`[33.1] “inputting a source sequence of bits into a source
`register;” ................................................................................... 50
`[33.2] “defining bit positions in said source sequence of
`bits to be permuted in said source register for a group of
`bits in a destination register;” .................................................. 54
`[33.3] “in response to a PPERM instruction inserting bits
`from said source sequence into said destination register
`as determined by said bit positions.” ....................................... 56
`Claim 34 (Depends on Claim 33): ..................................................... 57
`1.
`[34.0] “The method of claim 33 wherein said PPERM
`instruction comprises a first parameter indicating which k
`bits in said destination register will change,” .......................... 58
`[34.1] “a reference to said source register which contains
`said source sequence of bits to be permuted,” ......................... 65
`[34.2] “a reference to a configuration register which
`contains configuration bits for indicating which said bits
`in said source register are assembled” ..................................... 65
`[34.3] “and a reference to said destination register. ” .............. 66
`4.
`Claim 35 (Depends on Claim 34): ..................................................... 66
`[35] “The method of claim 34 wherein in said destination
`register said k bits specified by said first parameter are
`updated and all other bits in said destination register are
`set to zero.” .............................................................................. 67
`Claim 36 (Depends on Claim 34): ..................................................... 69
`[36] “The method of claim 34 wherein each of said k bits
`in said final permutation is determined by lgn bits to
`specify which bit in said source register to change.” ............... 69
`Claim 37 (Independent): ..................................................................... 71
`1.
`[37.0] “A computer implemented method for performing
`an arbitrary permutation of a sequence of bits comprising
`the steps of:” ............................................................................. 72
`
`2.
`
`3.
`
`B.
`
`C.
`
`D.
`
`E.
`
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`IPR2021-00078, Declaration of Donald Alpert, Ph.D.
`In Support of Inter Partes Review of U.S. Patent 7,174,014
`
`2.
`
`3.
`
`4.
`
`[37.1] “inputting a source sequence of bits into a source
`register;” ................................................................................... 72
`[37.2] “defining bit positions in said source sequence of
`bits to be permuted in said source register for a group of
`bits in a destination register;” .................................................. 73
`[37.3] “in response to a PPERM3R instruction inserting
`bits from said source [into said] sequence destination
`register as determined by said bit positions.” .......................... 75
`Claim 38 (Depends on Claim 37): ..................................................... 81
`1.
`[38.0] “The method of claim 37 wherein said PPERM3R
`instruction comprises a first parameter indicating which k
`bits in said destination register will change,” .......................... 81
`[38.1] “a reference to said source register which contains
`said source sequence of bits to be permuted,” ......................... 82
`[38.2] “a reference to a configuration register which
`contains configuration bits for indicating which said bits
`in said source register are assembled” ..................................... 83
`[38.3] “and a reference to said destination register. ” .............. 83
`4.
`Claim 39 (Depends on Claim 38): ..................................................... 84
`1.
`[39.0] “The system of claim 38 wherein in said
`destination register said k bits permuted by said first
`parameter are updated.” ........................................................... 84
`Claim 40 (Depends on Claim 38): ..................................................... 84
`1.
`[40.0] “The method of claim 38 wherein each of said k
`bits in said final permutation is determined by lgn bits to
`specify which bit in said source register to change.” ............... 85
`Claim 41 (Independent): ..................................................................... 85
`1.
`[41.0] “A computer system for performing an arbitrary
`permutation comprising:” ........................................................ 85
`[41.1] “a source register;” ........................................................ 86
`[41.2] “a configuration register;” ............................................. 86
`
`2.
`
`3.
`
`2.
`3.
`
`F.
`
`G.
`
`H.
`
`I.
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`IPR2021-00078, Declaration of Donald Alpert, Ph.D.
`In Support of Inter Partes Review of U.S. Patent 7,174,014
`
`4.
`5.
`
`2.
`3.
`4.
`5.
`
`J.
`
`[41.3] “a destination register;” ................................................. 86
`[41.3] “in response to a PPERM instruction placing bits
`assembled from a sequence of bits from said source
`register to a position in a sequence of bits in said
`destination register based on a configuration of bits of
`said configuration register.” ..................................................... 86
`Claim 47 (Independent): ..................................................................... 87
`1.
`[47.0] “A computer system for performing an arbitrary
`permutation comprising:” ........................................................ 87
`[47.1] “a source register;” ........................................................ 88
`[47.2] “a configuration register;” ............................................. 88
`[47.3] “a destination register;” ................................................. 88
`[47.3] “in response to a PPERM3R instruction placing
`bits assembled from a sequence of bits from said source
`register to a position in a sequence of bits in said
`destination register based on a configuration of bits of
`said configuration register.” ..................................................... 88
`XI. OBVIOUSNESS COMBINATIONS – MOTIVATIONS TO
`COMBINE AND EXPECTATION OF SUCCESS ..................................... 89
`A.
`Partial-Width Results ......................................................................... 91
`B.
`Partial-Register Writes ....................................................................... 94
`C.
`Combination of Davida with Microunity ........................................... 96
`D.
`Combination of Davida with Abdallah .............................................. 99
`E.
`Combination of Davida with Blomgren ........................................... 101
`F.
`Combination of Davida with Abdallah and Microunity .................. 102
`XII. CONCLUSION ........................................................................................... 103
`XIII. DECLARATION ........................................................................................ 103
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`IPR2021-00078, Declaration of Donald Alpert, Ph.D.
`In Support of Inter Partes Review of U.S. Patent 7,174,014
`
`I, Donald Alpert, Ph.D., hereby declare as follows:
`I.
`INTRODUCTION
`1.
`My name is Donald Alpert and I have been retained by Petitioners
`
`Oracle Corporation and Oracle America, Inc. to provide my opinions regarding
`
`U.S. Patent No. 7,174,014 (“the ’014 Patent”). Specifically, I have been asked to
`
`consider the patentability of Claims 33-41, 47 of the ’014 Patent (“the Challenged
`
`Claims”) in view of prior art and the understanding of a person of ordinary skill in
`
`the art (“POSITA”) as it relates to the ’014 Patent. I have personal knowledge of
`
`the facts and opinions set forth in this declaration and believe them to be true. If
`
`called upon to do so, I would testify competently thereto. I have been warned that
`
`willful false statements and the like are punishable by fine or imprisonment, or
`
`both.
`
`2.
`
`I am being compensated for my time at my standard consulting rate. I
`
`am also being reimbursed for expenses that I incur during the course of this work.
`
`My compensation is not contingent upon the results of my study, the substance of
`
`my opinions, or the outcome of any proceeding involving the Challenged Claims.
`
`I have no financial interest in the outcome of this matter or in the pending litigation
`
`between Petitioner and the Patent Owner.
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`IPR2021-00078, Declaration of Donald Alpert, Ph.D.
`In Support of Inter Partes Review of U.S. Patent 7,174,014
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`3.
`
`My opinions are based on my years of education, research, and
`
`experience, as well as my investigation and study of relevant materials, including
`
`those cited herein.
`
`4.
`
`I may rely upon these materials, my knowledge and experience,
`
`and/or additional materials to rebut arguments raised by the Patent Owner.
`
`Further, I may also consider additional documents and information in forming any
`
`necessary opinions, including documents that may not yet have been provided to
`
`me.
`
`5.
`
`My analysis of the materials produced in this proceeding is ongoing
`
`and I will continue to review any new material as it is provided. This declaration
`
`represents only those opinions I have formed to date. I reserve the right to revise,
`
`supplement, and/or amend my opinions stated herein based on new information
`
`and on my continuing analysis of the materials already provided.
`
`II. QUALIFICATIONS
`6.
`I am an independent consultant with Camelback Computer
`
`Architecture, LLC. My residence and place of business is at 2020 21st Street,
`
`Sacramento, CA 95818. I am over the age of eighteen a citizen of the United
`
`States. Oracle-1004 is a copy of my current curriculum vitae (“CV”).
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`IPR2021-00078, Declaration of Donald Alpert, Ph.D.
`In Support of Inter Partes Review of U.S. Patent 7,174,014
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`7.
`
`I have 45 years of academic and industrial experience in applying,
`
`designing, studying, teaching, and writing about microprocessors, computer
`
`systems, and other electronic devices. I received an Electrical Engineering Ph.D.
`
`degree in 1984 from Stanford University. I earlier received an Electrical
`
`Engineering B.S. degree from MIT in 1973 and an Electrical Engineering M.S.
`
`degree from Stanford University in 1978. I have taught classes in computer
`
`architecture at Stanford University, Tel Aviv University, and Arizona State
`
`University, including graduate-level classes covering permutation networks for
`
`parallel processing.
`
`8.
`
`At Stanford I studied various topics related to data communications,
`
`including digital signal processing, information theory, cryptography, error-
`
`correcting codes, and stochastic processes, in addition to my focus on computer
`
`architecture. I studied principles of public key and symmetric cryptography with
`
`Professor Martin Hellman, a recognized leader in these fields. I also designed and
`
`built a circuit board that employed the first chipset to implement the Data
`
`Encryption Standard; the board was used for over a decade to conduct
`
`cryptographic research in conjunction with a PDP-11 computer system in
`
`Stanford’s Information System Laboratory. This circuit board implemented a
`
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`IPR2021-00078, Declaration of Donald Alpert, Ph.D.
`In Support of Inter Partes Review of U.S. Patent 7,174,014
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`variety of different permutations, used to perform the various steps of the DES
`
`algorithm.
`
`9.
`
`From 1976 to 1977, I worked at Burroughs Corporation, where I
`
`designed peripheral interface controllers, including those for serial data
`
`communications based on Intel 8080 microprocessor components. From 1980 to
`
`1989, I was the lead architect for the design of three high-performance
`
`microprocessors at Zilog and National Semiconductor. At National Semiconductor
`
`I led the definition of a coprocessor that accelerated computation for fax
`
`communication. Later, at Intel, I was the lead architect of the Pentium® Processor
`
`from 1989 to 1992 and of the 815 chipset from 1999 to 2000, both of which
`
`became the most widely used PC components of their time. The 815 chipset
`
`comprised two components: (1) a memory controller hub (MCH) that included a
`
`graphics controller and memory controller with interfaces to the CPU, 133 MHz
`
`SDRAM system memory modules, an optional, external graphics controller and (2)
`
`an I/O controller hub (ICH) that included various I/O controllers for system
`
`peripheral devices, including an IEEE-compatible LAN controller. Additionally, I
`
`served as co-manager for the Itanium processor design from 1993-1997, a
`
`component targeting high-performance, parallel processing systems, such as Intel’s
`
`supercomputer system products.
`
`4
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`IPR2021-00078, Declaration of Donald Alpert, Ph.D.
`In Support of Inter Partes Review of U.S. Patent 7,174,014
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`10. My responsibilities as a computer architect included evaluating
`
`performance for critical processing tasks on various processors from Intel and
`
`competitive companies. These tasks included media processing for video and
`
`audio, TCP processing, and cryptographic routines for AES, RSA, and elliptic
`
`curve algorithms.
`
`11.
`
`I am a Senior Member of the Institute of Electrical and Electronics
`
`Engineers (IEEE), and served as the chair of the IEEE Technical Committee on
`
`Microprocessors and Microcomputers from 1999 to 2000. I was the keynote
`
`speaker at the first Cool Chips conference, dedicated to the study of low-power
`
`microprocessors and systems. I have given invited lectures at several universities
`
`and published ten papers in various professional journals and conference
`
`proceedings. My paper entitled “Architecture of the Pentium Processor,” was
`
`selected as best paper in IEEE Micro for 1993. I am a named inventor on over 30
`
`U.S. patents that pertain to microprocessors, computer systems. and related
`
`technology.
`
`12.
`
`I have served as an expert witness in a variety of patent litigation
`
`matters in the areas of processor design, computer systems, parallel processing,
`
`secure communication and cryptographic processing for financial transactions, and
`
`others. I have been admitted and recognized in U.S. District Courts as a technical
`5
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`IPR2021-00078, Declaration of Donald Alpert, Ph.D.
`In Support of Inter Partes Review of U.S. Patent 7,174,014
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`expert in four separate District Court patent trials, as well as before the Patent Trial
`
`and Appeal Board (PTAB) and International Trade Commission (ITC).
`
`III. MATERIALS RELIED UPON IN FORMING MY OPINIONS
`13.
`In forming the opinions set forth in this declaration, I have considered
`
`and relied upon my education, knowledge of the relevant field, knowledge of the
`
`scientific and engineering principles, and my experience. I have also reviewed and
`
`considered the ’014 Patent (Oracle-1001), its prosecution history (Oracle-1002),
`
`and the following materials:
`
`Description
`Exhibit
`Oracle-1005 George Davida and Frank Dancs, A Crypto-Engine, Advances in
`Cryptology - CRYPTO ’87, LNCS 293, pp. 257-268, 1988
`(“Davida”) (annotated with line numbers)
`Oracle-1006 PCT Publication No. WO 97/07451 (“Microunity”)
`Oracle-1007 U.S. Patent No. 6,192,467 (“Abdallah”)
`Oracle-1008 U.S. Patent No. 6,334,183 (“Blomgren”)
`Oracle-1022 U.S. Patent No. 5,524,256 (“Turkowski”)
`Oracle-1023 U.S. Patent No. 6,865,272 (“Cole”)
`Oracle-1024 Excerpt of C.L. Liu, Elements of Discrete Mathematics (1977)
`Oracle-1025 Excerpt of Mark B. Wells, Elements of Combinatorial Computing
`(1971)
`Oracle-1026 Claude E. Shannon, Communication Theory of Secrecy Systems,
`Bell System Technical Journal (1949)
`Oracle-1027 Horst Feistel, Cryptography and Computer Privacy, Scientific
`American (May 1973)
`Oracle-1028 Ruby B. Lee, Subword parallelism with MAX-2, IEEE Micro Vol.
`16, No. 4 (Aug. 1996)
`
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`IPR2021-00078, Declaration of Donald Alpert, Ph.D.
`In Support of Inter Partes Review of U.S. Patent 7,174,014
`
`Description
`Exhibit
`Oracle-1029 U.S. Patent No. 5,101,371 (“Iobst”)
`Oracle-1030
`James J. Little et al., Algorithmic Techniques for Computer Vision
`on a Fine-Grained Parallel Machine, IEEE Transactions on
`Pattern Analysis and Machine Intelligence, Vol. 11, No. 3 (Mar.
`1989)
`Oracle-1031 Federal Information Processing Standards, Publication 46, Data
`Encryption Standard (Jan. 15, 1977), available at
`https://csrc.nist.gov/publications/ detail/fips/46/archive/1977-01-
`15.
`Oracle-1032 Robert V. Meushaw, The Standard Data Encryption Algorithm
`Part 1: An Overview, BYTE Magazine, Vol. 4, No. 3 (Mar. 1979)
`Oracle-1033 Keith Diefendorff, et al., AltiVec Extension to PowerPC
`Accelerates Media Processing, IEEE Micro (Apr. 2000)
`Oracle-1034 C. Hansen, Microunity’s media processor architecture, IEEE
`Micro, Vol. 16, No. 4 (Aug. 1996)
`Oracle-1035 Leslie Helm, John Moussouris has created a multimedia chip that
`could change the face of communications. Now he hopes the
`world will… Follow His MUSE, L.A. Times, Apr. 15, 1996
`Oracle-1036 Zhijie Shi, Bit Permutation Instructions: Architecture,
`Implementation, and Cryptographic Properties (June 2004)
`Oracle-1037 Declaration of Rachel J. Watters on Authentication of Publication
`regarding George Davida and Frank Dancs, A Crypto-Engine,
`Advances in Cryptology - CRYPTO '87
`Oracle-1038 Printout from DBLP Computer Science for the International
`Association for Cryptologic Research, Annual International
`Cryptology Conference (CRYPTO) from 1981 through 2020,
`including bibliography for Advances in Cryptology - CRYPTO '87,
`A Conference on the Theory and Applications of Cryptographic
`Techniques, Santa Barbara, California, USA, Aug. 16-20, 1987
`Oracle-1039 Google Scholar Citation Report regarding George Davida and
`Frank Dancs, A Crypto-Engine, Advances in Cryptology -
`CRYPTO '87
`John von Neuman, First Draft of a Report on the EDVAC, IEEE
`Annals of the History of Computing, Vol 15, No. 4 (1993)
`
`Oracle-1040
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`IPR2021-00078, Declaration of Donald Alpert, Ph.D.
`In Support of Inter Partes Review of U.S. Patent 7,174,014
`
`Description
`Exhibit
`Oracle-1041 Excerpt of David A. Patterson & John L. Hennessy, Computer
`Organization and Design: The Hardware/Software Interface,
`Third Edition, 27-29 (2005)
`Oracle-1042 Excerpt of John L. Hennessy & David A. Patterson, Computer
`Architecture: A Quantitative Approach, Third Edition, 151-154
`(2003)
`Oracle-1043 U.S. Patent No. 3,798,359 (“Feistel”)
`Oracle-1044 PA-RISC 2.0, Hewlett-Packard Company (1995)
`Oracle-1045
`IA-64 Application Developer's Architecture Guide, Intel
`Corporation, (May 1999)
`Oracle-1046 Excerpt of J. Crawford and P. Gelsinger, Programming the 80386,
`Sybex Books, Alameda, Calif. (1987)
`IV. PRIORITY DATE AND LEVEL OF ORDINARY SKILL
`14.
`In providing my opinions in this declaration, I was asked to consider
`
`the patent claims and the prior art standing in the shoes of a person of ordinary
`
`skill in the art (“POSITA”) at the time of the alleged invention, which I understand
`
`to be May 7, 2001, the filing date on the face of the patent.1 I understand that
`
`1 I understand that the file history for the ’014 Patent included a claim of priority to
`
`a provisional application filed on May 5, 2000, and that this priority claim was
`
`withdrawn during prosecution. In the event that the ’014 Patent is somehow allowed
`
`to claim priority to May 5, 2000 rather than May 7, 2001, my opinions expressed
`
`herein would not be affected.
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`IPR2021-00078, Declaration of Donald Alpert, Ph.D.
`In Support of Inter Partes Review of U.S. Patent 7,174,014
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`common factors considered in determining the ordinary level of skill in a field of
`
`art include the level of education and experience of persons working in the field,
`
`the types of problems encountered in the field, and the sophistication of the
`
`technology at the time of the invention. I also understand that a POSITA is not a
`
`specific or real individual. Rather, I understand a POSITA to be a hypothetical
`
`individual having the qualities reflected by the factors above. I understand that a
`
`POSITA also would have had knowledge from the teachings of the prior art,
`
`including the art cited below.
`
`15. My opinions are given from the perspective of a POSITA at or around
`
`May 7, 2001, the filing date of the application that became the ’014 Patent. This is
`
`because, as is seen on the face of the ’014 Patent, the ’014 Patent does not make a
`
`claim to any earlier application.
`
`16.
`
`In my opinion, a POSITA in the field of the ’014 Patent would have
`
`had, by May 7, 2001, a bachelor’s degree in computer science, electrical
`
`engineering, or a related discipline and two years of experience in the relevant
`
`technical field—computer design and instruction set architectures, including
`
`permutation instructions—or the equivalent. Additional graduate education could
`
`substitute for professional experience, or significant experience in the field could
`
`substitute for formal education. The skill and knowledge of a POSITA in the field
`9
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`IPR2021-00078, Declaration of Donald Alpert, Ph.D.
`In Support of Inter Partes Review of U.S. Patent 7,174,014
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`of the ’014 Patent would not change if the ’014 Patent were permitted to claim
`
`priority to a provisional application filed on May 5, 2000.
`
`17. Well before May 7, 2001, my level of skill in the art was at least the
`
`level of a POSITA as discussed in Section II above. Additionally, I was teaching,
`
`recruiting, and training such persons at the time of the patent’s filing. Thus, I am
`
`qualified to provide opinions regarding what a POSITA would have known and
`
`understood at the time, and my analysis and conclusions herein are from the
`
`perspective of a POSITA as of May 7, 2001.
`
`V.
`
`UNDERSTANDING OF GOVERNING LAW
`18.
`I am not an attorney, but have been instructed in and applied the law
`
`as described in this section.
`
`19.
`
`I understand that the first step in comparing an asserted claim to the
`
`prior art is for the claim to be properly construed. I address how a person of
`
`ordinary skill in the art would have understood the claims of the alleged invention
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`in Section VIII below
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`20.
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`I have been further instructed and understand that a patent claim is
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`unpatentable and invalid as obvious if the subject matter of the claim as a whole
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`would have been obvious to a person of ordinary skill in the art of the claimed
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`subject matter as of the time of the invention at issue. I understand that when
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`IPR2021-00078
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`IPR2021-00078, Declaration of Donald Alpert, Ph.D.
`In Support of Inter Partes Review of U.S. Patent 7,174,014
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`assessing the obviousness of claimed subject matter, the following factors are
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`evaluated: (1) the scope and content of the prior art; (2) the difference or
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`differences between each claim of the patent and the prior art; and (3) the level of
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`ordinary skill in the art at the time the patent was filed.
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`21.
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`I understand that claimed subject matter may be obvious in view of
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`more than one item of prior art. I understand, however, that it is not enough to
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`show simply that all the limitations of the claimed subject matter are spread
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`throughout the prior art. Instead, for claimed subject matter to be obvious over
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`multiple references, there must be some reason or motivation for one of ordinary
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`skill in the art to combine the prior art references to arrive at the claimed subject
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`matter.
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`22.
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`I have been informed that, in seeking to determine whether an
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`invention that is a combination of known elements would have been obvious to a
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`person of ordinary skill in the art at the time of the invention, one must consider
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`the references in their entirety to ascertain whether the disclosures in those
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`references render the combination obvious to such a person.
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`23.
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`I have been informed and understand that, while not required, the
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`prior art references themselves may provide a teaching, suggestion, motivation, or
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`reason to combine, but other times the motivation linking two or more prior art
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`IPR2021-00078, Declaration of Donald Alpert, Ph.D.
`In Support of Inter Partes Review of U.S. Patent 7,174,014
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`references is common sense to a person of ordinary skill in the art at the time of the
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`invention.
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`24.
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`I understand that a particular combination may be proven obvious
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`merely by showing that it was obvious to try the combination. I have been
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`informed that, if a technique has been used to improve one device, and a person of
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`ordinary skill in the art would recognize that it would improve similar devices in
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`the same way, using the technique is obvious unless its actual application is
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`beyond his or her skill. I have further been informed and understand that a
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`POSITA combines the teachings of the prior art references and does not
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`necessarily combine the embodiments of those teachings physically.
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`25.
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`I further understand that an obviousness analysis recognizes that
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`market demand, rather than scientific literature, often drives innovation, and that a
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`motivation to combine references also may be supplied by the direction of the
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`marketplace. For example, when there is a design need or market pressure to solve
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`a problem and there are a finite number of identified, predictable solutions, a
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`person of ordinary skill has good reason to pursue the known options within his or
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`her technical grasp because the result is likely the product not of innovation but of
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`ordinary skill and common sense.
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`IPR2021-00078
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`

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`IPR2021-00078, Declaration of Donald Alpert, Ph.D.
`In Support of Inter Partes Review of U.S. Patent 7,174,014
`
`26.
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`I have been informed that the combination of familiar elements
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`according to known methods is likely to be obvious when it does no more than
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`yield predictable results. Thus, where all of the elements of a claim are used in
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`substantially the same manner, in devices in the same field of endeavor, the claim
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`is likely obvious.
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`27. Additionally, I understand that a patent is likely to be invalid for
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`obviousness if a person of ordinary skill can implement a predictable variation or if
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`there existed at the time of the invention a known problem for which there was an
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`obvious solution encompassed by the patent’s claims. Therefore, when a work is
`
`available in one field of endeavor, design incentives and other market forces can
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`prompt variations of it, either in the same field or a different one.
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`28.
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`I further understand that combining embodiments related to each other
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`in a single prior art reference would not ordinarily require a leap of inventiveness.
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`29.
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`I also understand that one of ordinary skill in the art must have had a
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`reasonable expectation of success when combining references for claimed subject
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`matter to be obvious.
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`30.
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`I have been informed and I understand that factors referred to as
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`“objective indicia of non-obviousness” or “secondary considerations” are also to
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`be considered when assessing obviousness when such evidence is available. I
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`IPR2021-00078
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`

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`IPR2021-00078, Declaration of Donald Alpert, Ph.D.
`In Support of Inter Partes Review of U.S. Patent 7,174,014
`
`understand that these factors can include: (1) commercial success; (2) long-felt but
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`unresolved needs; (3) copying of the invention by others in the field; (4) initial
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`expressions of disbelief by experts in the field; (5) failure of others to solve the
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`problem the claimed subject matter solved; and (6) unexpected results.
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`31.
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`I also understand that evidence of objective indicia of nonobviousness
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`must be commensurate in scope with the claimed subject matter. I further
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`understand that there must be a relationship, sometimes referred to as a “nexus,”
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`between any such secondary indicia and the claimed invention.
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`32.
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`Finally, I have been informed that one cannot use hindsight to
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`determine that an invention was obvious.
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`33.
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`I provide my opinions in this declaration based on the guidelines set
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`forth above.
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`VI. OVERVIEW OF THE TECHNOLOGY
`A.
`Instructions and Processors
`34.
`In 1945, John von Neumann, in a First Draft of a Report on the
`
`EDVAC, introduced what became known as the von Neumann architecture, greatly
`
`influencing future generations of computer engineers. See Oracle-1040, John von
`
`Neuman, First Draft of a Report on the EDVAC, IEEE Annals of the History of
`
`Computing, Vol 15,