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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
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`APPLE INC.
`Petitioner
`
`v.
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`SOLAS OLED LTD.
`Patent Owner
`____________
`
`
`Case No. IPR2020-01546
`U.S. Patent No. 7,573,068
`____________
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`
`
`
`
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 7,573,068
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`
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`IPR2020-01546
`U.S. Patent No. 7,573,068
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`TABLE OF CONTENTS
`INTRODUCTION ...................................................................................... 1
`I.
`III. SUMMARY OF THE ’068 PATENT ........................................................ 1
`A.
`THE ’068 PATENT’S ALLEGED INVENTION ............................................ 1
`B.
`SUMMARY OF THE PROSECUTION HISTORY ........................................... 9
`C.
`SUMMARY OF THE PROPOSED GROUND ............................................... 11
`D. A PERSON HAVING ORDINARY SKILL IN THE ART ............................... 14
`IV. REQUIREMENTS FOR IPR UNDER 37 C.F.R. § 42.104 ..................... 14
`A.
`STANDING UNDER 37 C.F.R. § 42.104(A) .......................................... 14
`B.
`CHALLENGE UNDER 37 C.F.R. § 42.104(B) AND RELIEF
`REQUESTED ....................................................................................... 14
`CLAIM CONSTRUCTION UNDER 37 C.F.R. § 42.104(B)(3) ................... 15
`C.
`THE CHALLENGED CLAIMS ARE UNPATENTABLE .................... 24
`A. GROUND 1: SHIRASAKI IN VIEW OF CHILDS RENDERS OBVIOUS
`CLAIMS 1, 5, 6, 8-13, AND 17 ............................................................. 24
`VI. DISCRETION CONSIDERATIONS ...................................................... 59
`THE GENERAL PLASTICS FACTORS FAVOR INSTITUTION ....................... 59
`A.
`THE FINTIV FACTORS STRONGLY FAVOR INSTITUTION ........................ 63
`B.
`VII. CONCLUSION ......................................................................................... 68
`VIII. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8(A)(1) ................... 70
`A.
`REAL PARTY-IN-INTEREST ................................................................. 70
`B.
`RELATED MATTERS ........................................................................... 70
`C.
`LEAD AND BACK-UP COUNSEL .......................................................... 70
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`V.
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`i
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`I.
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`INTRODUCTION
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`IPR2020-01546
`U.S. Patent No. 7,573,068
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`Petitioner Apple Inc. (“Petitioner”) requests an Inter Partes Review (“IPR”)
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`of claims 1, 5, 6, 8-13, and 17 (the “Challenged Claims”) of U.S. Patent No.
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`7,573,068 (“the ’068 Patent”).
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`III. SUMMARY OF THE ’068 PATENT
`A.
`The ’068 Patent’s Alleged Invention
`The ’068 Patent generally describes a specific circuit arrangement and
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`manufacturing method for organic EL display panels. ’068 Patent (Ex. 1001),
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`Abstract, 1:16-20. The subject display panel is comprised of pixel circuits, each of
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`which is located at the intersection of perpendicular signal and scan lines. Id at 6:1-
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`2, 6:50-51. Figure 1 below illustrates the display panel array, comprising a plurality
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`of signal lines Yn (green) crossing a plurality of scan lines Xm (blue ) with a pixel
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`circuit Pm,n (red) at each intersection:
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`1
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`IPR2020-01546
`U.S. Patent No. 7,573,068
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`Id. at Fig. 1 (annotated).
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`Circuit Layout
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`Each pixel circuit is comprised of three transistors, a capacitor, and an organic
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`light-emitting element. Id. at 6:63-65. Figure 2 below illustrates the general
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`arrangement of the ’068 Patent’s pixel circuit:
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`2
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`IPR2020-01546
`U.S. Patent No. 7,573,068
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`Id. at Figure 2 (annotated). The circuit layout is designed to optimize current delivery
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`to each of the organic light-emitting elements across the display in accordance with
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`the driving method described below.
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`U.S. Patent No. 7,573,068
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`Circuit Operation
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`As set forth in detail below, the basic operating principle is current flows from
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`the supply line, through driving transistor 23, and through the light emitting element
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`20, which causes the light emitting element to emit light. The particular charge on
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`capacitor 24 dictates the amount of current that flows through driving transistor 23,
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`which, in turn, dictates the amount of light emitted.
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`The process is divided into two main time intervals—(1) a selection period in
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`which the capacitor is charged to a specific level and (2) a light emission period in
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`which current is supplied to the light emitting element through driving capacitor 23
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`causing it to emit an amount of light determined by the capacitor’s charge.
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`During the selection period, the scan lines (blue in the below annotated figure)
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`turn on transistors 21 and 22 by applying high/on voltage to their gates. Id. at 15:44-
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`47. Turning these transistors on allows current to flow between the sources and
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`drains of transistors 21 and 22. Id. at 16:5-8. With these current paths opened, as
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`depicted below, a data driver supplies a write current to the signal line Y, which
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`causes current to flow along path A (annotated green) from the supply line, through
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`the drain-to-source paths of transistors 23 and 21:
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`4
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`IPR2020-01546
`U.S. Patent No. 7,573,068
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`Id. at Fig. 2 (annotated), 15:60-64 (describing the data driver supplying a write
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`current to the signal lines), 16:14-21 (describing the current flow over path A). The
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`’068 Patent explains that the write current supplied by the data driver “forcibly
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`set[s]” a voltage differential between the gate and source of transistor 23. Id. at
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`16:25-34. Because capacitor 24 is connected to the gate and source of transistor 23,
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`this voltage level is “stored in the capacitor 24.” Id. at 16:34-38.
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`During the light emission period, the scan line stops applying voltage to the
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`gates of transistors 21 and 22, turning them off and effectively closing the source-
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`to-drain paths. Id. at 16:38-41. With the source-to-drain path of transistor 22 closed,
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`5
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`IPR2020-01546
`U.S. Patent No. 7,573,068
`the voltage stored in capacitor 24 during the selection period is applied to the gate
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`of transistor 23 as depicted in green below. Id. at 16:41-48. At the same time, a high-
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`level drive voltage is applied to the supply line which causes a drive current to flow
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`along path B—through the drain-to-source path of transistor 23 and through the light
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`emitting element as depicted in red below:
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`
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`Id. at Fig. 2 (annotated), 16:48-55. The amount of current that flows through the
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`light emitting element is dictated by the voltage applied to the gate of driving
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`transistor 23, which corresponds to the charge stored in capacitor 24. The ’068 Patent
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`explains that the driving current that causes the light emitting element to emit light
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`6
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`U.S. Patent No. 7,573,068
`equals the write current that was supplied to the signal lines during the selection
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`period. Id. at 16:43-61. Because the driving current dictates the brightness of emitted
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`light, the system controls brightness for a given pixel by adjusting the write current
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`supplied during the selection period.
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`Feed Interconnections
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`In a conventional organic EL display panel, voltage is applied to the circuits
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`directly through the thin-film supply lines that are patterned with the other pixel
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`circuit elements. Id. at 1:57-62. For example, supply lines Zi and Zi-1 (green) in the
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`following annotated Fig. 8 are patterns together with (i.e., fabricated using the same
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`thin-film metallization process step as) the source and drain of transistor 22 (yellow),
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`scan line Xi (red), and an electrode of capacitor 24 (blue):
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`Id. at Fig. 8 (annotated), 9:36-44 (noting “the drains 22d and sources 22s of the
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`holding transistors 22, the drains 23d and sources 23s of the driving transistors 23,
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`7
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`IPR2020-01546
`U.S. Patent No. 7,573,068
`and the lower electrodes 24A of the capacitors 24 . . ., the scan lines X1 to Xm, and
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`the supply lines Z1 to Zm are formed, using photolithography and etching, by
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`patterning a single conductive film formed on the entire surface of the gate insulating
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`film 31”).
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`The ’068 Patent identifies a problem with the conventional method of
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`fabricating supply lines from thin-film fabrication processes—the fabricated layers
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`are “thin literally,” which results in high electrical resistance and causes voltage
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`drops and signal delay when such supply lines are used to drive multiple arrayed
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`light emitting elements. Id. at 2:1-12. To decrease the resistance and eliminate the
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`issues of voltage drop and signal delay, the ’068 Patent proposes a thick feed
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`interconnection line connected to the supply line and fabricated on different layers
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`and from a different process step than the thin-film supply lines. Id. at 3:63-67. In
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`some embodiments, the thick feed interconnections are constructed on top of the
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`supply lines on the upper layer of the substrate. Id. at 2:58-60, 3:29-30, 7:31-34,
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`10:23-25. The same annotated Figure 8 from above, is reproduced below to further
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`highlight the structure of the thick interconnection 90 (purple) built on top of the
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`thin-film supply line Zi (green):
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`8
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`U.S. Patent No. 7,573,068
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`Id. at Fig. 8 (annotated), 10:17-33 (noting “feed interconnections 90 are formed by
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`electroplating and are therefore much thicker than the signal lines Y1 to Yn, scan
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`lines X1 to Xm, supply lines Z1 to Zm, and the gates, sources, and drains of the
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`transistors 21 to 23”).
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`During both the selection period and the light emission period, voltage is
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`applied to the pixel circuits via the thick feed interconnections. Id. at 15:47-52,
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`16:17-19. Using these thick feed interconnections as the voltage source for the
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`display panel limits the voltage drop across the display panel, improving
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`performance. Id. at 2:39-41, 3:60-4:35.
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`Summary of the Prosecution History
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`B.
`The Application that resulted in the ’068 Patent was filed on Sep. 21, 2005 as
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`U.S. App. No. 11/232,368 (“the ’368 Application”). ’068 Patent (Ex. 1001). The
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`IPR2020-01546
`U.S. Patent No. 7,573,068
`’368 Application claims priority to three Japanese priority filings—JP2004-273532,
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`dated Sep. 21, 2004; JP2004-273580, dated Sep. 21, 2004; and JP2005-269434,
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`dated Sep. 16, 2005. Id. For purposes of this petition and without waiving its right
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`to challenge priority in this or any other proceeding, Petitioner adopts the earliest
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`alleged priority filing (Sept. 21, 2004) as the invention date for the Challenged
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`Claims.
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`As originally filed, the ’368 Application recited claims 1-25. ’068 File History
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`(Ex. 1002), 94-101. No prior art-based rejections were issued during prosecution,
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`but the Examiner did require restriction/election of claims 1-17, drawn to a
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`semiconductor element, or claims 18-25, drawn to a method of making a
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`semiconductor element. Id. at 661-668. The Examiner further required a
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`restriction/election between patentably distinct embodiments directed to the
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`structure of the feed interconnections, finding the interconnections of Embodiment
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`I are in a different layer from the thin film components, which is mutually exclusive
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`from the Embodiment II interconnections that may be placed in the same layer as
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`the thin film components. Id.
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`On February 4, 2009, Applicant elected claims 1-17, elected Embodiment I,
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`and cancelled claims 18-25. Id. at 669. A Notice of Allowance issued on April 15,
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`2009 and purported “minor corrections” to the claims were entered by Examiner
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`Amendment shortly thereafter. Id. at 673-689.
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`10
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`Summary of the Proposed Ground
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`C.
`The single proposed ground presented herein relies on two references. The
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`IPR2020-01546
`U.S. Patent No. 7,573,068
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`first, PCT Publication WO 03/058328 to Shirasaki, et al. (“Shirasaki”) (Ex. 1005),
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`is a 102(b) prior art reference that shares an inventor and is assigned to the same
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`assignee as the ’068 Patent. Nearly identical to the ’068 Patent, Shirasaki teaches
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`the same three-transistor pixel circuit arrangement, the same selection period during
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`which a capacitor is charged to a specific level using a data driver current sink, and
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`the same light emitting period during which a light emitting element is driven to a
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`current dictated by the charged capacitor. The following figures illustrate the
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`similarities between Shirasaki (on the left) and the ’068 Patent (on the right):
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`11
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`IPR2020-01546
`U.S. Patent No. 7,573,068
`Shirasaki (Ex. 1005), Fig. 5A (illustrating the selection period in which capacitor 13
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`is charged using a data driver current sink), Fig. 5B (illustrating the light emitting
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`period), 10:25-11:3, 31:1-14 (describing the same); ’068 Patent (Ex. 1001), Fig. 2
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`(denoting current path A for the selection period, which aligns with Shirasaki’s Fig.
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`5A, and current path B for the light emitting period, which aligns with Shirasaki’s
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`Fig. 5B).
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`The key difference between Shirasaki and the ’068 Patent is Shirasaki does
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`not employ low resistance feed interconnections on a different layer from its supply
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`lines (referred to in Shirasaki as “voltage scan lines”). However, it was well known
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`before the ’068 Patent that supply lines formed from the same thin-film processes as
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`transistors suffered from resistivity-related issues such as voltage drop. For example,
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`PCT Publication WO 2004/090853 to Shin, et al. (“Shin”) (Ex. 1007)1 recognizes
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`that “current supply lines” in a “conventional organic electro luminescent panel” are
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`formed in the same layer as the sources and drains of a drive transistor, and, as a
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`result, the supply lines have a high resistance causing a “voltage drop of each of the
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`current supply lines (VDD lines).” Shin (Ex. 1007), 2:14-3:8. Similarly, U.S. Patent
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`No. 7,358,529 to Childs, et al. (“Childs”) (Ex. 1006) recognizes that it is desirable
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`1 Shin qualifies as prior art under 102(e) because it was filed on April 6, 2004,
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`designated the U.S., and was published in English.
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`12
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`IPR2020-01546
`U.S. Patent No. 7,573,068
`to “reduc[e] the resistance of (and hence the voltage drops across)” certain
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`conductive components in an active matrix display device. Childs (Ex. 1006), 1:4-
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`47. To accomplish this goal, Childs proposes low resistance conductive barriers that
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`“serve as a back-up or even as a replacement for at least part of a thin-film conductor
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`line of the circuit substance, for example . . . a supply line.” Id. at 2:27-44. As shown
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`below, conductive barrier 240 (green) provides a thick and low resistance
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`supplemental current path for supply line 140 (orange) (referred to by Childs as the
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`“drive line”):
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`Id. at Fig. 2 (annotated), 6:20-29 (describing the same).
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`As set forth in the proposed ground below, to remedy the known problems
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`with Shirasaki’s thin-film conductive paths, it would have been obvious to add
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`Childs’s supplemental conductive barriers along Shirasaki’s supply lines.
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`13
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`IPR2020-01546
`U.S. Patent No. 7,573,068
`D. A Person Having Ordinary Skill in the Art
`A person having ordinary skill in the art (“PHOSITA”) at the time of the ’068
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`Patent would have had at least a relevant technical degree in Electrical Engineering,
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`Computer Engineering, Physics, or the like, and 2 to 3 years’ experience in active
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`matrix display design and electroluminescence, with additional education
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`substituting for experience and vice versa. Fontecchio Decl. (Ex. 1003), ¶¶ 27-30.
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`IV. REQUIREMENTS FOR IPR UNDER 37 C.F.R. § 42.104
`A.
`Standing Under 37 C.F.R. § 42.104(A)
`Petitioner certifies that the ’068 Patent is available for IPR and that Petitioner
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`is not barred or estopped from requesting IPR challenging the claims of the ’068
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`Patent. Specifically, (1) Petitioner is not the owner of the ’068 Patent, (2) Petitioner
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`has not filed a civil action challenging the validity of any claim of the ’068 Patent,
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`and (3) this Petition is filed less than one year after the Petitioner was served with a
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`complaint alleging infringement of the ’068 Patent.
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`B. Challenge Under 37 C.F.R. § 42.104(B) and Relief Requested
`In view of the prior art and evidence presented, Claims 1, 5, 6, 8-13, and 17
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`of the ’068 Patent are unpatentable and should be cancelled. 37 C.F.R. §
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`42.104(b)(1). Further, based on the prior art references identified below, IPR of the
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`Challenged Claims should be granted. 37 C.F.R. § 42.104(b)(2).
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`14
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`Proposed Ground of Unpatentability
`Ground 1: Claims 1, 5, 6, 8-13, and 17 are obvious under pre-AIA
`35 U.S.C. § 103 over Shirasaki in view of Childs.
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`IPR2020-01546
`U.S. Patent No. 7,573,068
`Exhibits
`Ex. 1005,
`Ex. 1006
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`Section VII identifies where each element of the Challenged Claims is found
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`in the prior art. 37 C.F.R. § 42.104(b)(4). The exhibit numbers of the supporting
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`evidence relied upon to support the challenges are provided in the Appendix of
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`Exhibits below and the relevance of the evidence to the challenges raised are
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`provided in Section VI below. 37 C.F.R. § 42.104(b)(5). Exs. 1001-1021 are also
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`attached.
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`C. Claim Construction Under 37 C.F.R. § 42.104(B)(3)
`In this proceeding, claims are interpreted under the same standard applied by
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`Article III courts (i.e., the Phillips standard). See 37 C.F.R. § 42.100(b); see also 83
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`Fed. Reg. 197 (Oct. 11, 2018); Phillips v. AWH Corp., 415 F.3d 1303, 1312 (Fed.
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`Cir. 2005) (en banc). Under this standard, words in a claim are given their plain
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`meaning, which is the meaning understood by a person of ordinary skill in the art in
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`view of the patent and file history. Phillips, 415 F.3d 1303, 1312-13.
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`Patent Owner has now taken positions regarding the proper construction of
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`certain disputed terms multiple times. In a first co-pending litigation, Solas OLED
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`Ltd. v. LG Display Co., Ltd. et al., No. 6:19-cv-00236-ADA (W.D. Tex.) (“the LG
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`Case”), the court construed a number of claims based on the parties’ claim
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`15
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`U.S. Patent No. 7,573,068
`construction briefing and a Markman hearing. In a second co-pending litigation,
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`Solas OLED Ltd. v. Apple Inc., Case No. 6:19-cv-00537-ADA (W.D. Tex.) (“the
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`Apple Case”), the parties have fully briefed claim construction, and a Markman
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`Order recently issued. Petitioner has attempted to provide the most relevant context
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`from both cases below.
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`“feed interconnections”
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`In the LG case, the Court construed “feed interconnections” as “conductive
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`structures in a different layer or layers than the supply line that also provide
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`connections to a source that supplies voltage and/or current.” LG Markman Order
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`(Ex. 1008), 2. Petitioner and Patent Owner have agreed to apply this construction in
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`the Apple Case. Joint Statement (Ex. 1009), 3. Given this agreement, Petitioner has
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`applied this same construction herein.
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`“[formed on/connected to] said plurality of supply lines along said plurality of
`supply lines”
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`The challenged claims recite feed interconnections that are either “formed on”
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`or “connected to” a “plurality of supply lines along said plurality of supply lines.”
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`In the LG Case, the court sided with Patent Owner and replaced the term “along”
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`with “over the length or direction of.” LG Markman Order (Ex. 1008), 2. In the
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`Apple Case, Petitioner argues the limitations should be construed to mean “stacked
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`on or making multiple contacts with said plurality of supply lines over the length of
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`each supply line.” This construction recognizes the two feed interconnection
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`IPR2020-01546
`U.S. Patent No. 7,573,068
`embodiments. A first embodiment, depicted below in annotated Fig. 1, arranges the
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`feed interconnections (red) in parallel with the supply lines (blue), connects the two
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`in the middle of the panel (yellow) and runs the interconnections along the full
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`lengths of the supply lines:
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`’068 Patent (Ex. 1001), Fig. 1 (annotated). A second embodiment, depicted below
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`in annotated Fig. 20, arranges the feed interconnections (red) perpendicular to the
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`supply lines (blue) and connects the two at each intersection (yellow):
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`17
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`IPR2020-01546
`U.S. Patent No. 7,573,068
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`Id. at Fig. 20 (annotated). Although Patent Owner concedes its broader construction
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`“is consistent with every embodiment” in the ’068 Patent, it rejects Petitioner’s
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`proposal and advocates the broader construction from the LG Case: “[formed
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`on/connected to] said plurality of supply lines over the length or direction of said
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`plurality of supply lines.” Solas Reply Br. (Ex. 1010), 12-13. In its recent Markman
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`Order, the court in the Apple Case adopted Patent Owner’s broader construction.
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`Apple Markman Order (Ex. 1020), 2.
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`For purposes of the proposed ground herein, Petition has mapped the
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`combination of Shirasaki and Childs
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`to Petitioner’s correct construction,
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`demonstrating that the combination includes feed interconnections “stacked on or
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`making multiple contacts with [the] plurality of supply lines over the length of each
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`supply line.” However, the combination also satisfies the broader construction
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`proposed by Patent Owner and adopted by the court in the Apple Case. Accordingly,
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`it is not necessary for the Board to expressly construe this phrase in order to resolve
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`the controversy.
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`“patterned together”
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`Each asserted claim recites specific lines (e.g., supply lines or signal lines) are
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`“patterned together [with]” specific transistor electrodes (e.g., the gate, source,
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`and/or drain). In the LG Case, Solas disputed that the lines and electrodes must be
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`(1) in the same layer and (2) formed from the same process step. Solas Responsive
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`Br. (Ex. 1011), 27-30. The court in the LG Case and in the Apple Case accepted
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`Solas’s argument and construed this phrase to mean “‘patterned to fit together,’
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`wherein patterned may consist of one or more fabrication steps.” LG Markman
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`Order (Ex. 1008), 2; Apple Markman Order (Ex. 1020), 3. For purposes of the
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`proposed ground herein, Petition has mapped the combination of Shirasaki and
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`Childs to a narrower correct construction, demonstrating that the combination
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`includes lines and electrodes that are patterned together in the sense that they are
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`formed on the same layer from the same process step. However, the combination
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`also satisfies the broader construction proposed by Patent Owner and adopted by the
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`U.S. Patent No. 7,573,068
`court in the Apple Case. Accordingly, it is not necessary for the Board to expressly
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`construe this phrase in order to resolve the controversy.
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`“supply lines” and “signal lines”
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`As explained in Sec. II.A above, supply lines and signal lines are distinct
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`conductive lines in the ’068 Patent that serve distinct functions. Supply lines span
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`the length of the panel, supplying a power source current to drive the light emitting
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`elements in multiple pixel circuits. ’068 Patent (Ex. 1001), 16:38-61, Figs. 1, 20.
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`Signal lines, on the other hand, are connected to the “data driver” for supplying a
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`specific “write current” during the selection phase that sets the charge of each pixel’s
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`capacitor, which dictates the level of light emission during the light emission phase.
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`Id. at 15:60-16:38. To acknowledge these distinct roles, in the Apple Case, Petitioner
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`has proposed “supply lines” should be construed to mean “conductive lines, each
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`supplying a driving current or voltage to a plurality of pixel circuits” and “signal
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`lines” should be construed to mean “conductive lines carrying data.” Apple Br. (Ex.
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`1012), 33-34. Patent Owner disputes these correct constructions and instead
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`advocates that “supply lines” are any “conductive lines supplying current or voltage”
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`and that “signal lines” are any “conductive lines supplying signals.” Id. The court in
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`the Apple Case recently adopted Solas’s broader construction. Apple Markman
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`Order (Ex. 1020), 2.
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`U.S. Patent No. 7,573,068
`Because Shirasaki teaches the same circuit structure as the ’068 Patent and
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`ascribes the same functions to its supply lines and signal lines, Petitioner has applied
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`its narrower constructions herein. However, the combination also satisfies the
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`broader construction proposed by Patent Owner and adopted by the court in the
`
`Apple Case. Accordingly, it is not necessary for the Board to expressly construe this
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`phrase in order to resolve the controversy.
`
`“source” / “drain”
`
`As discussed above with regard to “patterned together,” the ’068 Patent
`
`describes supply lines that are patterned together with the sources and drains of the
`
`driving transistors and signal lines that are patterned together with the gates of the
`
`driving transistors, meaning they are formed on the same layer from the same
`
`process step. Annotated Fig. 8 below illustrates supply lines (green) on the same
`
`layer and formed from the same process step (depositing a conductive film) as the
`
`drain (yellow) and source (orange) of holding transistor 22:
`
`
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`21
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`IPR2020-01546
`U.S. Patent No. 7,573,068
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`
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`’068 Patent (Ex. 1001), Fig. 8 (annotated), 8:35-51 (describing the transistor
`
`structure). Similarly, annotated Fig. 5 below illustrates signal line (red) on the same
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`layer and formed from the same process step as the gate (blue) of driving transistor
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`23:
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`
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`22
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`
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`IPR2020-01546
`U.S. Patent No. 7,573,068
`Id. at Fig. 5 (annotated), 8:18-34 (describing the transistor structure). The ’068
`
`Patent explains that the drains (21d, 22d, 23d) and sources (21s, 22s, 23s) of the
`
`transistors and “the supply lines Z1 to Zm are formed . . . by patterning a single
`
`conductive film formed on the entire surface of the gate insulating film 31.” Id. at
`
`9:36-44. Similarly, the gates (21g, 22g, 23g) and “the signal lines Y1 to Yn are
`
`formed . . . by patterning a single conductive film formed on the entire surface of the
`
`insulating substrate 2.” Id. at 18-23.
`
`The ’068 Patent distinguishes the conductive film sources (orange) and drains
`
`(yellow) from the impurity-doped semiconductor films 23a (blue) and 23b (red)
`
`depicted in the below Fig. 5 excerpt, which, by nature of being made of different
`
`materials, were fabricated using different process steps and exist on different layers
`
`from the supply lines:
`
`Id. at Fig. 5 (excerpted and annotated), 8:52-66 (describing the transistor structure).
`
`
`
`
`
`23
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`IPR2020-01546
`U.S. Patent No. 7,573,068
`Recognizing this distinction between the source, drain, and the impurity-doped
`
`semiconductor films over which the source and drain are configured, Petitioner
`
`proposed construing “source” as “source electrode” and “drain” as “drain electrode.”
`
`Apple Resp. Br. (Ex. 1013), 36-38 (noting the common usage of “electrode”
`
`connotes a conductive structure, distinguishing impurity-doped semiconductor films
`
`and clarifying which portion of the transistor structure is claimed). Patent Owner
`
`does not advance a competing construction, arguing the plain and ordinary meaning
`
`should control. Presumably, this would capture either the conductive source and
`
`drain structures Petitioner’s construction
`
`targets or
`
`the
`
`impurity-doped
`
`semiconductor films. The court in the Apple Case recently adopted Patent owner’s
`
`broader “plain-and-ordinary meaning” construction. Apple Markman Order (Ex.
`
`1020), 2.
`
`Because Shirasaki teaches the transistor and conductive line structure as the
`
`’068 Patent, Petitioner has applied its narrower constructions herein. However, the
`
`combination also satisfies the broader construction proposed by Patent Owner and
`
`adopted by the court in the Apple Case. Accordingly, it is not necessary for the Board
`
`to expressly construe this phrase in order to resolve the controversy.
`
`V. THE CHALLENGED CLAIMS ARE UNPATENTABLE
`A. Ground 1: Shirasaki in View of Childs Renders Obvious Claims 1, 5,
`6, 8-13, and 17
`
`Overview of Shirasaki
`
`
`
`24
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`
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`IPR2020-01546
`U.S. Patent No. 7,573,068
`Shirasaki was published on July 17, 2003 and therefore qualifies as prior art
`
`to the ’068 Patent under at least 35 U.S.C. § 102(b) (Pre-AIA). Shirasaki was not
`
`considered during prosecution.
`
`As set forth above in Section III.C, Shirasaki is nearly identical to the ’068
`
`Patent, teaching the same three-transistor pixel circuit arrangement, the same
`
`selection period during which a capacitor is charged to a specific level using a data
`
`driver current sink, and the same light emitting period during which a light emitting
`
`element is driven to a current dictated by the charged capacitor.
`
`Because Shirasaki, like the ’068 Patent, is directed to a display panel having
`
`an active driving type optical element, Shirasaki is in the same field of endeavor as
`
`the ’068 Patent. Compare Shirasaki (Ex. 1005), Abstract (“A display panel includes
`
`an optical element . . . and a switch circuit which supplies a memory current having
`
`a predetermined current value to a current line during a selection period, and stops
`
`the supply of the memory current to the current line during a non-selection period”).
`
`with ’068 Patent (Ex. 1001), 1:16-20 (“The present invention relates to . . . a display
`
`panel using light-emitting elements which cause self emission when a current is
`
`supplied by the transistor array substrate.”), 16:5-61 (describing selection period and
`
`light emission period). Shirasaki is therefore analogous art to the ’068 Patent.
`
`Fontecchio Decl. (Ex. 1003), ¶¶ 57-58, 64-66.
`
`
`
`
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`25
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`
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`IPR2020-01546
`U.S. Patent No. 7,573,068
`
`Overview of Childs
`
`Childs issued on April 15, 2008 from a PCT application that was filed on
`
`February 21, 2003 and claims priority to three earlier filings. Because the PCT
`
`application was filed after November 29, 2000, designated the U.S., and was
`
`published in English, Childs qualifies as prior art to the ’068 Patent under 35 U.S.C.
`
`§ 102(e) (Pre-AIA) at least as of the February 21, 2003 international filing date.2
`
`Childs was not considered during prosecution.
`
`Teaching an active matrix display device like the ’068 Patent, Childs
`
`recognizes that it is desirable to “reduc[e] the resistance of (and hence the voltage
`
`drops across)” certain conductive components in an active matrix display device.
`
`Childs (Ex. 1006), 1:4-47. To accomplish this goal, Childs proposes low resistance
`
`conductive barriers that “serve as a back-up or even as a replacement for at least part
`
`of a thin-film conductor line of the circuit substance, for example . . . a supply line.”
`
`Id. at 2:27-44. As shown below, conductive barrier 240 (green) provides a thick and
`
`low resistance supplemental current path for supply line 140 (orange) (referred to by
`
`Childs as the “drive line”):
`
`
`2 If Patent Owner seeks to antedate Childs, Petitioner reserves its right to
`
`demonstrate Childs should be deemed 102(e) prior art as of its earlier priority filings.
`
`
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`26
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`
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`IPR2020-01546
`U.S. Patent No. 7,573,068
`
`
`
`Id. at Fig. 2 (annotated), 6:20-29 (describing the same).
`
`Because Childs, like the ’068 Patent, is directed to a display panel having an
`
`active driving type optical element, Childs is in the same field of endeavor as the
`
`’068 Patent. Compare Childs (Ex. 1006), 1:4-6 (“This invention relates to active-
`
`matrix display devices, particularly but not exclusively electroluminescent displays
`
`using light-emitting diodes”), 4:59-5:8 (describing selection period and light
`
`emission period) with ’068 Patent (Ex. 1001), 1:16-20, 16:5-61. Childs is further
`
`directed to solving the same problem as the ’068 Patent—providing low resistance
`
`supply feed interconnections to reduce voltage drop across the display panel array.
`
`Compare Childs (Ex. 1006), 1:32-47 (describing conductive barriers for “reducing
`
`the resistance of (and hence the voltage drops across)” conductive paths), 2:34-44
`
`(noting the conductive barriers “serve as a back-up or even as a replacement for . . .
`
`a supply line”) with ’068 Patent (Ex. 1001), 2:5-41 (noting object of invention is to
`
`
`
`27
`
`
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`IPR2020-01546
`U.S. Patent No. 7,573,068
`avoid voltage drops resulting from high resistivity supply lines), 4:4-26 (describing
`
`thick feed interconnections used to reduce voltage drop). Childs is therefore
`
`analogous art to the ’068 Patent. Fontecchio Decl. (Ex. 1003), ¶¶ 42-43, 55, 67.
`
`Motivation to Combine Shirasaki and Childs
`
`Shirasaki discloses a nearly identical display panel and driving method as the
`
`’068 Patent, including the three-transisto
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