I 1111111111111111 11111 1111111111 1111111111 11111 1111111111111111 IIII IIII IIII
`
`US007573068B2
`
`US 7,573,068 B2
`
`(IO) Patent No.:
`c12) United States Patent
`
`(45)Date of Patent:
`
`Aug. 11, 2009
`
`Shimoda et al.
`
`(54)TRANSISTORARRAYSUBSTRATE AND
`DISPLAY PANEL
`
`2004/0108978 Al* 6/2004 Matsueda et al. ............. 345/76
`
`6,864,639 B2 3/2005 Ito
`
`
`6,933,533 B2 8/2005 Yamazaki et al.
`
`
`7,317,429 B2 1/2008 Shirasaki et al.
`(75)Inventors: Satoru Shimoda, Fussa (JP); Tomoyuki
`
`
`
`
`
`
`
`Shirasaki, Higashiyamato (JP); Jun
`Ogura, Fussa (JP); Minoru Kumagai,
`Tokyo (JP)
`
`FOREIGN PATENT DOCUMENTS
`
`A
`
`1360350 7/2002
`
`
`8-330600 A 12/1996
`
`(Continued)
`
`OTHER PUBLICATIONS
`
`
`
`
`
`CN
`(73)Assignee: Casio Computer Co., Ltd., Tokyo (JP)
`JP
`
`( *) Notice: Subject to any disclaimer, the term ofthis
`
`
`
`
`
`patent is extended or adjusted under 35
`
`U.S.C. 154(b) by 769 days.
`
`(21)Appl. No.: 11/232,368
`
`(22)Filed:
`Sep.21,2005
`
`A Japanese Office Action ( and English translation thereof) dated Apr.
`
`
`
`
`
`
`
`
`30, 2008, issued in a counterpart Japanese Application.
`
`(65)
`
`
`
`US 2006/0098521 Al May 11, 2006
`
`Primary Examiner-Davienne Monbleau
`
`
`Prior Publication Data
`
`Assistant Examiner-Shweta Mulcare
`
`
`
`
`
`(7 4) Attorney, Agent, or Firm-Frishauf, Holtz, Goodman &
`
`Chick, P.C.
`Foreign Application Priority Data
`
`
`
`
`
`(30)
`
`(57)
`ABSTRACT
`
`(JP) ............................. 2004-273532
`Sep.21,2004
`
`(JP) ............................. 2004-273580
`Sep.21,2004
`
`(JP) ............................. 2005-269434
`Sep. 16,2005
`A transistor array substrate includes a plurality of driving
`
`
`
`
`
`
`
`transistors which are arrayed in a matrix on a substrate. The
`(51)Int. Cl.
`
`
`
`
`driving transistor has a gate, a source, a drain, and a gate
`H0JL 33/00 (2006.01)
`
`
`
`insulating film inserted between the gate, and the source and
`HOJL 27/32(2006.01)
`
`
`
`
`
`
`drain. A plurality of signal lines are patterned together with
`
`
`
`
`(52)U.S. Cl. .................. 257 / 72; 257/208; 257/E33.055
`
`
`
`
`the gates of the driving transistors and arrayed to run in a
`
`
`(58)Field of Classification Search ................... 257/59,
`
`
`
`
`
`predetermined direction on the substrate. A plurality of sup­
`
`
`
`257/72, 79, 81, 83, E33.064, E33.077, E27.131,
`
`
`
`
`ply lines are patterned together with the sources and drains of
`
`
`257/E27.132, 208, E33.055; 313/500, 505;
`
`
`
`
`via the driving transistors and arrayed to cross the sign al lines
`
`
`349/42, 139, 149, 73, 74; 345/44, 45, 87-92
`
`
`
`the gate insulating film. The supply line is electrically con­
`
`
`
`See application file for complete search history.
`
`
`nected to one of the source and the drain of the driving
`
`
`
`transistor. A plurality of feed interconnections are formed on
`
`
`
`
`the supply lines along the supply lines, respectively.
`
`
`
`References Cited
`
`(56)
`
`U.S. PATENT DOCUMENTS
`
`
`
`6,762,564 B2 7/2004 Noguchi et al.
`
`
`
`
`
`
`
`17 Claims, 27 Drawing Sheets
`
`90 _ _ -+- -- --.--��- - -
`
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`
`91
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`P;,J
`
`IPR2020-01546
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`
`

`

`US 7,573,068 B2
`
`Page 2
`
`FOREIGN PATENT DOCUMENTS
`
`JP
`
`JP
`
`
`
`2003-330387 A 11/2003
`
`
`
`
`
`2004-101948 A 4/2004
`
`JP
`
`JP
`
`JP
`
`
`
`
`
`2000-349298 A 12/2000
`
`
`
`2003-133079 A 5/2003
`
`
`
`
`
`2003-195810 A 7/2003
`
`
`
`WO WO 2004/019314 Al
`
`3/2004
`
`*cited by examiner
`
`IPR2020-01546
`Apple EX1001 Page 2
`
`

`

`2009 Sheet 1 of 27
`Aug. 11,
`U.S. Patent
`
`US 7,573,068
`B2
`
`1
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`91 2
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`FIG.1
`
`IPR2020-01546
`Apple EX1001 Page 3
`
`

`

`
`U.S. Patent Aug. 11,
`
`2009 Sheet 2 of 27 US 7,573,068 B2
`
`90 __ -----<---------�----------'--
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`
`Zi
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`Yj
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`FIG.2
`
`IPR2020-01546
`Apple EX1001 Page 4
`
`

`

`US 7,573,068
`B2
`U.S. Patent Aug. 11,
`2009
`Sheet 3 of 27
`
`Wp
`
`24
`
`90
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`FIG.3
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`95
`
`IPR2020-01546
`Apple EX1001 Page 5
`
`

`

`Aug. 11, 2009 Sheet 4 of 27 US 7,573,068
`B2
`U.S. Patent
`
`22
`
`90
`
`±= = �- --Zi-1
`Xi
`
`---,
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`IPR2020-01546
`Apple EX1001 Page 6
`
`

`

`N
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`IPR2020-01546
`Apple EX1001 Page 7
`
`

`

`Sheet 6 of 27 US 7,573,068
`B2
`U.S. Patent
`Aug. 11, 2009
`
`.c
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`IPR2020-01546
`Apple EX1001 Page 8
`
`

`

`
`2009 Sheet 7 of 27
`U.S. Patent Aug. 11,
`
`US 7,573,068 B2
`
`N
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`IPR2020-01546
`Apple EX1001 Page 9
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`

`

`N
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`IPR2020-01546
`Apple EX1001 Page 10
`
`

`

`
`U.S. Patent Aug. 11,
`
`2009 Sheet 9 of 27 US 7,573,068 B2
`
`92 22g
`
`94
`
`FIG.9
`
`IPR2020-01546
`Apple EX1001 Page 11
`
`

`

`U.S. Patent Aug. 11, 2009 Sheet 10 of 27 US 7,573,068
`B2
`
`94
`
`21s
`
`______ ,__ 2 3 d
`
`FIG.10
`
`IPR2020-01546
`Apple EX1001 Page 12
`
`

`

`
`2009 Sheet 11 of 27
`U.S. Patent Aug. 11,
`
`US 7,573,068 B2
`
`' '
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`
`IPR2020-01546
`Apple EX1001 Page 13
`
`

`

`
`
`U.S. Patent Aug. 11, 2009 Sheet 12 of 27 US 7,573,068 B2
`
`91a
`
`91 91 91 91 91 91
`
`FIG.12
`
`IPR2020-01546
`Apple EX1001 Page 14
`
`

`

`
`U.S. Patent Aug. 11,
`
`2009 Sheet 13 of 27 US 7,573,068 B2
`
`SELECTION PERIOD
`OF PIXEL CIRCUITS
`Pi,1 TO Pi,n
`LIGHT EMISSION
`LIGHT EMISSION
`PERIOD OF
`PERIOD OF PIXEL
`i, 1 TO Pi, n
`PRECEDING FRAME ! ! CIRCUITS P
`1
`
`VOLTAGE LEVEL
`OF SCAN LINE Xi
`
`VH
`VOLTAGE LEVEL OF FEED
`INTERCONNECTION 90
`AND SUPPLY LINE Zi
`VL
`
`-
`
`_11_
`I I
`
`VOLTAGE LEVEL OF
`TRANSISTOR 23 OF
`PIXEL CIRCUIT Pi, j
`
`CURRENT VALUE OF
`ORGANIC EL ELEMENT 20
`OF PIXEL CIRCUIT Pi, i
`
`LIGHT EMISSION
`SELECTION PERIOD
`OF PIXEL CIRCUITS
`Pi+1, 1 TO Pi+1, n
`
`LIGHT EMISSION
`; PERIOD OF PIXEL
`!CIRCUITS
`Pi+1 1 TO Pi+1 n
`
`I
`
`I
`
`'
`
`VOLTAGE LEVEL
`OF SCAN LINE Xi+1
`
`VOLTAGE LEVEL OF FEED
`INTERCONNECTION 90
`AND SUPPLY LINE Zi+1
`
`CURRENT VALUE OF
`ORGANIC EL ELEMENT 20
`OF PIXEL CIRCUIT Pi+1, j
`
`LIGHT EMISSION
`
`FIG.13
`
`IPR2020-01546
`Apple EX1001 Page 15
`
`

`

`
`U.S. Patent Aug. 11,
`
`2009 Sheet 14 of 27 US 7,573,068 B2
`
`j
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`VOLTAGE LEVEL
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`TRANSISTOR 23 OF
`PIXEL CIRCUIT Pi, j
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`CURRENT VALUE OF
`ORGANIC EL ELEMENT 20
`....____.
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`: CIRCUITS Pi+1, 1 TO
`OF PIXEL CIRCUITS
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`
`i
`
`1·
`
`FIG.14
`
`IPR2020-01546
`Apple EX1001 Page 16
`
`

`

`
`U.S. Patent
`
`
`Aug. 11, 2009 Sheet 15 of 27
`
`US 7,573,068 B2
`
`VP3vp3,
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`IPR2020-01546
`Apple EX1001 Page 17
`
`

`

`Sheet 16 of 27
`
`Aug. 11, 2009
`U.S. Patent
`
`
`
`US 7,573,068 B2
`
`5
`
`4
`
`MAXIMUM
`VOLTAGE
`DROP [V]
`
`2
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`
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`32-INCH PANEL
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`
`FIG.16
`
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`
`

`

`
`Aug. 11,
`U.S. Patent
`
`2009 Sheet 17 of 27 US 7,573,068 B2
`
`32-INCH PANEL
`
`1.0X107
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`1.ox106
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`
`FIG.17
`
`IPR2020-01546
`Apple EX1001 Page 19
`
`

`

`Sheet 18
`of 27
`Aug. 11,
`2009
`U.S. Patent
`
`US 7,573,068
`B2
`
`5
`
`4
`
`MAXIMUM
`VOLTAGE
`DROP [V]
`
`2
`
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`
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`8
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`
`FIG.18
`
`IPR2020-01546
`Apple EX1001 Page 20
`
`

`

`2009 Sheet 19 of 27 US 7,573,068
`B2
`Aug. 11,
`U.S. Patent
`
`40-INCH PANEL
`
`1.ox107
`
`1.0X106
`
`1.0X105 \
`CURRENT
`DENSITY
`[A/cm2]
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`SECTIONAL AREA S [µm2]
`
`FIG.19
`
`IPR2020-01546
`Apple EX1001 Page 21
`
`

`

`
`U.S. Patent
`
`
`Aug. 11, 2009 Sheet 20 of 27
`
`US 7,573,068 B2
`
`90
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`I I Xm-1
`
`I
`Pm-1 n-1
`Pm-1, n
`- '
`I - �
`I
`I T
`I I Xm
`
`--
`
`- -o
`
`Pm,1
`
`Pm,2
`
`t
`Pm, n-1
`
`I
`Pm,n
`
`r91a
`
`FIG.20
`
`IPR2020-01546
`Apple EX1001 Page 22
`
`

`

`
`U.S. Patent Aug. 11,
`
`2009 Sheet 21 of 27 US 7,573,068 B2
`
`90
`
`C2
`
`Zi
`
`Yj
`
`C1
`
`91
`
`F
`
`22d
`/ 22
`22g
`22s 23d
`/ 23
`23g
`24 23s
`
`C3
`
`21g
`
`24A 248
`21s 21d
`
`21
`
`f 20c
`
`P·.
`1,J
`
`FIG.21
`
`IPR2020-01546
`Apple EX1001 Page 23
`
`

`

`
`
`U.S. Patent Aug. 11, 2009 Sheet 22 of 27 US 7,573,068 B2
`
`90
`
`X\1V
`
`53 24 23
`
`24 23 53
`
`FIG.22
`
`IPR2020-01546
`Apple EX1001 Page 24
`
`

`

`U.S. Patent Aug. 11, 2009 Sheet 23 of 27
`
`US 7,573,068
`B2
`
`20{
`33 32
`23
`23a
`
`23d
`
`56
`20c
`20b
`20a
`
`23s
`
`23b
`23c 31 23P
`2
`
`FIG.23
`
`IPR2020-01546
`Apple EX1001 Page 25
`
`

`

`N
`=
`
`00
`= 0--,
`
`w
`-....l
`tit
`-....l
`
`r.,;_
`d
`
`0 ....
`
`-....J
`N
`
`.i;...
`N
`.....
`('D
`
`=-('D
`
`
`
`FIG.24
`
`/////✓/ //////////////Y //�r
`
`2oa/v /////////////77777
`
`20a
`
`1,0
`0
`0
`N
`
`
`........�
`
`�
`
`=�
`
`
`
`� ��
`�
`•
`00
`�
`
`20b
`
`z z z z �"--"-. "-. "-.�
`
`£ z z l z ,AZJh ffiW«/���z:z±zA�
`
`20b, � "-\_"-. "-. � z
`
`54 an
`
`55 n-t
`
`IPR2020-01546
`Apple EX1001 Page 26
`
`

`

`N
`=
`
`00
`= 0--,
`
`w
`-....l
`tit
`-....l
`
`r.,;_
`d
`
`0 ....
`
`-....J
`N
`
`Ul
`N
`('D .....
`
`=-('D
`
`
`
`1,0
`0
`0
`N
`
`....
`�
`
`
`....�
`
`=�
`
`
`
`
`00•
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`� ��
`�
`
`�
`
`/7777 �1----20a
`20b
`
`,\,,,, J,,,, J, h,,,, �"'-. "'-. "'-. "'-.�
`
`20b" � � "'-. �1 L.,, 2 J,,, i, ,,� , ffiU'.1///!Mm
`
`FIG.25
`
`20a/��777 OJ.//////7/////////
`
`54 on
`
`55 n-1
`
`IPR2020-01546
`Apple EX1001 Page 27
`
`

`

`
`
`U.S. Patent Aug. 11, 2009 Sheet 26 of 27 US 7,573,068 B2
`
`FIG.26
`
`90b 90 91 90 91 90 91
`
`90 91 90 91 90 91 90c
`
`FIG.27
`
`IPR2020-01546
`Apple EX1001 Page 28
`
`

`

`
`U.S. Patent Aug. 11, 2009 Sheet 27 of 27
`
`
`
`US 7,573,068 B2
`
`SELECTION PERIOD
`
`OF PIXEL CIRCUITS
`Pi, 1 TO Pi, n
`LIGHT EMISSION
`PERIOD OF
`PRECEDING FRAME
`OF PIXEL CIRCUITS
`Pi 1 TO Pin I
`
`'
`
`' '
`
`LIGHT EMISSION
`PERIOD OF PIXEL
`CIRCUITS Pi, 1 TO Pi, n
`
`VOLTAGE LEVEL
`OF SCAN LINE Xi
`
`VH
`VOLTAGE LEVEL OF FEED
`INTERCONNECTION 90
`AND SUPPLY LINES
`21 TO Zm
`VL
`
`VOLTAGE LEVEL OF
`TRANSISTOR 23 OF
`PIXEL CIRCUIT Pi, j
`
`CURRENT VALUE OF
`ORGANIC EL ELEMENT 20
`OF PIXEL CIRCUIT Pi, i
`
`_I
`I I
`
`SELECTION PERIOD
`OF PIXEL CIRCUITS
`Pi+1, 1 TO Pi+1, n
`
`OF SCAN LINE Xi+1 __ r �i-----1 _
`
`VOLTAGE LEVEL
`
`VOLTAGE LEVEL OF
`TRANSISTOR 23 OF
`PIXEL CIRCUIT Pi+1,j
`
`! !
`
`LIGHT EMISSION
`PERIOD OF
`PRECEDING FRAME
`OF PIXEL CIRCUITS
`Pi+1 1 TO Pi+1 n
`
`LIGHT EMISSION
`PERIOD OF PIXEL
`CIRCUITS P TO
`i+1 1
`Pi+1 n '
`
`CURRENT VALUE OF
`ORGANIC EL ELEMENT 20-----,
`OF PIXEL CIRCUIT Pi+1,i
`
`FIG.28
`
`IPR2020-01546
`Apple EX1001 Page 29
`
`

`

`
`
`DISPLAY PANEL
`
`BACKGROUND OF THE INVENTION
`
`A transistor array substrate according to a first aspect of the
`
`
`
`US 7,573,068 B2
`
`1
`
`CROSS-REFERENCE TO RELATED
`
`APPLICATIONS
`
`2
`TRANSISTOR ARRAY SUBSTRATE AND to the electrode is also formed. For this reason, when the
`
`
`
`
`
`
`
`interconnection is formed from the conductive thin film, the
`
`
`
`
`thickness of the interconnection equals that of the thin-film
`transistor.
`The electrode of the thin-film transistor is design ed assum­
`
`
`
`
`
`
`
`ing that it functions as a transistor. In other words, the elec­
`
`
`
`
`trode is not designed assuming that it supplies a current to a
`
`
`This application is based upon and claims the benefit of
`
`
`
`light-emitting element. Hence, the thin-film transistor is thin
`
`
`
`
`
`priority from prior Japanese Patent Applications No. 2004-
`
`
`
`
`literally. If a current is supplied from the interconnection to a
`
`273532, filed Sep. 21, 2004; No. 2004-273580, filed Sep. 21,
`
`
`
`
`
`10 plurality oflight-emitting elements, a voltage drop occurs, or
`
`2004; and No. 2005-269434, filed Sep. 16, 2005, the entire
`
`
`
`
`
`contents of all of which are incorporated herein by reference.
`
`
`
`the current flow through the interconnection delays due to the
`
`
`
`
`electrical resistance of the interconnection. To suppress the
`
`
`
`
`voltage drop or interconnection delay, the resistance of the
`
`
`
`interconnection is preferably low. If the resistance of the
`1.Field of the Invention
`
`
`
`
`
`15 interconnection is reduced by making a metal layer serving as
`
`
`
`
`The present invention relates to a transistor array substrate
`
`the source and drain of the transistor or a metal layer serving
`
`
`
`having a plurality of transistors and, more particularly, to a
`
`
`
`
`as the gate electrode thick, or patterning the metal layers
`
`
`
`display panel using light-emitting elements which cause self
`
`
`
`considerably wide to sufficiently flow the current through the
`
`
`
`emission when a current is supplied by the transistor array
`
`
`
`metal layers, the overlap area of the interconnection on
`substrate.
`
`
`
`20 another interconnection or conductor when viewed from the
`2. Description of the Related Art
`
`
`
`
`
`upper side increases, and a parasitic capacitance is generated
`Organic electroluminescent display panels can roughly be
`
`
`
`
`
`
`
`between them. This retards the flow of the current. Alterna­
`
`
`
`
`
`classified into passive driving types and active matrix driving
`
`
`
`
`tively, in a so-called bottom emission structure which emits
`
`
`
`
`
`types. Organic electroluminescent display panels of active
`
`
`
`
`EL light from the transistor array substrate side, light emitted
`
`
`
`
`matrix driving type are more excellent than those of passive
`
`
`
`
`from the EL elements is shielded by the interconnections,
`25
`
`
`
`
`driving type because of high contrast and high resolution. In
`
`
`
`
`
`resulting in a decrease in opening ratio, i.e., the ratio of the
`
`
`
`
`a conventional organic electroluminescent display panel of
`
`
`
`light emission area. If the gate electrode of the thin-film
`
`
`
`
`
`
`active matrix display type described in, e.g., Jpn. Pat. Appln.
`
`
`
`transistor is made thick to lower the resistance, a planariza­
`
`
`
`KOKAI Publication No. 8-330600, an organic electrolumi­
`
`
`tion film ( corresponding to a gate insulating film when the
`
`
`
`nescent element (to be referred to as an organic EL element
`
`
`
`
`
`
`thin-film transistor has, e.g., an inverted stagger structure) to
`30
`
`
`
`
`hereinafter), a driving transistor which supplies a current to
`
`
`
`
`eliminate the step of the gate electrode must also be formed
`
`
`
`the organic EL element when a voltage sign al corresponding
`
`
`
`thick. This may lead to a large change in transistor character­
`
`
`
`
`to image data is applied to the gate of the transistor, and a
`
`
`
`istic. When the source and drain are formed thick, the etching
`
`
`
`
`
`switching transistor which performs switching to supply the
`
`
`
`
`accuracy of the source and drain degrades. This may also
`
`
`
`
`
`voltage signal corresponding to image data to the gate of the 35
`
`
`
`adversely affect the transistor characteristic.
`
`
`
`
`
`driving transistor are arranged for each pixel. In this display
`BRIEF SUMMARY OF THE INVENTION
`
`
`
`panel, when a predetermined scan line is selected, the switch­
`
`
`ing transistor is turned on. At this time, a voltage of level
`It is an object of the present invention to satisfactorily drive
`
`
`
`
`
`
`
`representing the luminance is applied to the gate of the driv­
`
`
`
`
`a light-emitting element while suppressing any voltage drop
`
`
`
`ing transistor through a signal line. Thus, the driving transis-
`40
`
`and signal delay.
`
`
`
`
`tor is turned on. A driving current having a magnitude corre­
`
`
`
`
`
`
`
`
`sponding to the level of the gate voltage is supplied from the
`
`present invention comprises:
`
`
`
`
`power supply to the organic EL element through the source­
`a substrate;
`
`
`
`
`
`to-drain path of the driving transistor. Consequently, the EL
`a plurality of driving transistors which are arrayed in a
`
`
`
`
`
`
`
`element emits light at a luminance corresponding to the mag-
`45
`
`
`
`
`
`
`matrix on the substrate, each of the driving transistors having
`
`
`nitude of the current. During the period from the end of scan
`
`
`
`
`a gate, a source, a drain, and a gate insulating film inserted
`
`
`
`line selection to the next scan line selection, the level of the
`
`
`between the gate, and the source and drain;
`
`
`
`
`
`gate voltage of the driving transistor is continuously held even
`a plurality of signal lines which are patterned together with
`
`
`
`
`
`
`after the switching transistor is turned off. Hence, the organic
`
`
`
`
`
`the gates of the plurality of driving transistors and arrayed to
`
`
`
`EL element keeps emitting light at a luminance correspond-
`50
`
`
`run in a predetermined direction on the substrate;
`
`
`
`to ing to the magn itude of the driving current corresponding
`
`
`a plurality of supply lines which are patterned together
`the voltage.
`
`
`
`
`
`with the sources and drains of the plurality of driving transis­
`To drive the organic electroluminescent display panel, a
`
`
`
`
`
`
`
`tors and arrayed to cross the plurality of signal lines via the
`
`
`
`
`
`driving circuit is provided around the display panel to apply a
`
`
`
`gate insulating film, each of the supply lines being electrically
`
`
`
`
`
`voltage to the scan lines, signal lines, and power supply lines 55
`
`
`connected to one of the source and the drain of the driving
`
`laid on the display panel.
`
`transistor; and
`
`
`
`
`In the conventional organic electroluminescent display
`a plurality of feed interconnections which are formed on
`
`
`
`
`
`panel of active matrix driving type, interconnections such as
`
`
`
`
`the plurality of supply lines along the plurality of supply lines,
`
`a power supply line to supply a current to an organic EL
`respectively.
`
`
`
`element are patterned simultaneously in the thin-film transis-
`60
`
`
`
`Preferably, a substrate according to claim 1, further com­
`
`tor patterning step by using the material of a thin-film tran­
`
`
`
`prising a plurality of scan lines which are patterned together
`
`
`
`
`sistor such as a switching transistor or driving transistor.
`
`
`
`
`
`with the sources and drains of the plurality of driving transis­
`
`
`
`
`More specifically, in manufacturing the display panel, a con­
`
`
`tors and arrayed to cross the plurality of supply lines via the
`
`
`
`ductive thin film as a prospective electrode of a thin-film
`
`gate insulating film.
`
`
`
`
`transistor is subjected to photolithography and etching to 65
`
`
`
`Preferably, a substrate according to claim 2, which further
`
`
`form the electrode of a thin-film transistor from the conduc­
`
`
`
`comprises a plurality of switch transistors which are arrayed
`
`
`tive thin film. At the same time, an interconnection connected
`
`IPR2020-01546
`Apple EX1001 Page 30
`
`

`

`
`
`US 7,573,068 B2
`
`FIG. 7 is a sectional view taken along a line VII-VII in FIG.
`
`FIG. 8 is a sectional view taken along a line VIII-VIII in
`
`4
`3
`in a matrix on the substrate, each of the switch transistors to the driving transistor and pixel electrode through the feed
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`having the gate insulating film inserted between a gate and a
`
`
`
`interconnection, the voltage drop and signal delay can be
`
`
`source and drain, and
`suppressed.
`in which one of the source and drain of each of the plurality When the feed interconnections are to be formed by elec­
`
`
`
`
`
`
`
`
`
`
`
`
`of switch transistors is electrically connected to the other of troplating, the supply lines are formed on the signal lines.
`5
`
`
`
`
`the source and drain of a corresponding one of the plurality of
`
`
`
`When the structure is dipped in a plating solution while a
`
`driving transistors,
`
`
`
`
`voltage is applied to the supply lines in the manufacturing
`
`
`
`
`step of the transistor array substrate and the display panel, the
`
`
`
`
`
`the gate of each of the plurality of switch transistors is
`
`
`
`feed interconnections can be grown on the supply lines.
`
`
`
`
`electrically connected to the scan line through a contact hole
`
`
`formed in the gate insulating film, and
`
`
`
`
`According to this aspect, since the feed interconnections
`10
`
`
`
`
`can be made thick, the resistance of the feed interconnections
`
`
`
`
`the other of the source and drain of each of the plurality of
`
`
`
`can be reduced. When the resistance of the feed interconnec­
`
`
`
`
`
`
`switch transistors is electrically connected to the signal line
`
`
`
`tions decreases, the signal delay and voltage drop can be
`
`
`
`
`through a contact hole formed in the gate insulating film.
`suppressed.
`
`
`
`Preferably, a substrate according to claim 2, which further
`A display panel manufacturing method according to a dis­
`
`
`
`
`
`
`
`comprises a plurality of holding transistors which are arrayed 15
`
`
`play panel manufacturing method according to a fourth
`
`
`
`in a matrix on the substrate, each of the holding transistors
`
`
`
`
`aspect of the present invention comprises; patterning a plu­
`
`
`
`
`having the gate insulating film inserted between a gate and a
`
`
`
`rality of pixel electrodes on a panel to be arrayed in a matrix;
`
`
`source and drain, and
`
`
`
`forming an interconnection made of metal between the pixel
`
`
`in which one of the source and drain of each of the plurality
`
`
`
`
`
`electrodes; coating a surface of the interconnection with a
`20
`
`
`
`of holding transistors is electrically connected to the gate of a
`
`
`
`
`liquid repellent conductive layer; and forming an organic
`
`
`
`corresponding one of the plurality of driving transistors
`
`
`
`compound layer by applying an organic compound-contain­
`
`
`
`through a contact hole formed in the gate insulating film,
`
`ing solution to the electrode.
`
`
`
`
`the other of the source and drain of each of the plurality of
`A thick interconnection can suppress the voltage drop and
`
`
`
`holding transistors is electrically connected to one of the
`
`
`
`
`
`
`
`
`25 can also be used as a partition wall in forming an organic
`
`
`supply line and the scan line, and
`
`
`
`compound-containing solution. Since the liquid repellent
`
`
`
`
`the gate of each of the plurality of holding transistors is
`
`
`
`
`
`conductive layer exhibits liquid repellency, an organic com­
`
`
`
`
`electrically connected to the scan line through a contact hole
`
`
`
`pound layer can satisfactorily be patterned. A liquid repellent
`
`formed in the gate insulating film.
`
`
`
`
`
`conductive layer containing, e.g., a triazine compound can
`
`
`
`
`A display panel according to a second aspect of the present
`
`
`invention is a display panel comprising: 30
`
`
`
`
`selectively be formed on a metal surface so as to exhibit liquid
`
`
`
`repellency but carmot be formed on the surface of an insulator
`a substrate;
`
`
`
`
`
`or a metal oxide to exhibit liquid repellency. In addition, the
`a plurality of driving transistors which are arrayed in a
`
`
`
`
`
`
`
`
`liquid repellent conductive layer is formed on the metal sur­
`
`
`
`
`
`matrix on the substrate, each of the driving transistors having
`
`
`
`face very thin. Hence, the electrical conductivity on the metal
`
`
`
`
`a gate, a source, a drain, and a gate insulating film inserted
`35
`
`
`surface is not lost.
`
`
`between the gate, and the source and drain;
`a plurality of signal lines which are patterned together with
`
`
`
`BRIEF DESCRIPTION OF THE SEVERAL
`
`
`
`
`
`
`the gates of the plurality of driving transistors and arrayed to
`VIEWS OF THE DRAWING
`
`
`run in a predetermined direction on the substrate;
`
`
`a plurality of supply lines which are patterned together
`40
`FIG. 1 is a view showing the circuit arrangement of an EL
`
`
`
`
`
`
`
`
`
`with the sources and drains of the plurality of driving transis­
`
`
`
`display panel together with an insulating substrate;
`
`
`tors and arrayed to cross the plurality of sign al lines via the
`
`
`
`
`FIG. 2 is an equivalent circuit diagram of a pixel circuit of
`
`
`
`
`gate insulating film, each of the supply lines being electrically
`
`
`the EL display panel;
`
`
`
`
`connected to one of the source and the drain of the driving
`FIG. 3 is a plan view showing the electrode of the pixel
`
`
`
`
`transistor; and
`45
`
`circuit of the EL display panel;
`
`
`
`a plurality of feed interconnections which are connected to
`
`
`FIG. 4 is a plan view showing the electrode of the pixel
`
`
`
`
`
`the plurality of supply lines along the plurality of supply lines;
`
`circuit of the EL display panel;
`
`
`
`a plurality of pixel electrodes each of which is electrically
`
`
`FIG. 5 is a sectional view taken along a line V-V in FIG. 3;
`
`
`
`connected to the other of the source and the drain of each of
`
`
`FIG. 6 is a sectional view taken along a line VI-VI in FIG.
`
`
`the plurality of driving transistors;
`50 3;
`
`
`
`a plurality oflight-emitting layers which are formed on the
`
`
`
`
`
`plurality of pixel electrodes, respectively; and
`3;
`
`
`
`a counter electrode which covers the plurality of light­
`
`
`
`
`emitting layers.
`FIG. 3;
`Preferably, a panel according to claim 13, further compris-
`
`
`55
`
`
`
`
`
`
`ing a plurality of scan lines which are patterned together with
`is patterned;
`
`
`
`
`
`the sources and drains of the plurality of driving transistors
`
`
`
`
`
`
`
`and arrayed to cross the plurality of supply lines via the gate
`is patterned;
`insulating film.
`FIG. 11 is a plan view showing a state wherein the drain
`
`
`
`
`
`
`
`According to this aspect, the signal lines are patterned
`60
`
`
`
`layer is superposed on the patterned gate layer;
`
`
`
`
`together with the gates of the driving transistors. However,
`
`
`
`
`FIG. 12 is a schematic plan view showing the layout of an
`
`
`since the feed interconnections are stacked on the supply
`
`organic EL layer of the EL display panel;
`
`
`
`lines, the feed interconnections are formed separately for the
`
`
`
`FIG.13 is a timing chart for explaining a driving method of
`
`
`
`
`
`drains, sources, and gates of the driving transistors. For this
`
`
`the EL display panel;
`
`
`reason, the feed interconnection can be made thick without
`65
`
`
`
`
`
`
`increasing its width, and the resistance of the feed intercon­
`
`
`method of the EL display panel;
`
`
`
`nection can be reduced. Hence, even when a signal is output
`
`
`
`FIG. 9 is a plan view showing a state wherein a gate layer
`
`FIG.10 is a plan view showing a state wherein a drain layer
`
`FIG. 14 is a timing chart for explaining another driving
`
`IPR2020-01546
`Apple EX1001 Page 31
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`US 7,573,068 B2
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`First Embodiment
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`FIG. 15 is a graph showing the current vs. voltage charac­
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`arrayed on the insulating substrate 2 in a matrix along the
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`teristic of the driving transistor and organic EL element of
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`signal linesY1 to Yn and scan lines X1 to Xm. The feed inter­
`each pixel circuit;
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`connections 90 are provided in parallel to the supply lines Z
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`FIG. 16 is a graph showing the correlation between the
`to Zm when viewed from the upper side. The common inter-
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`maximum voltage drop and the interconnection resistivity
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`5 connections 91 are provided in parallel to the signal lines Y
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`p/sectional area S of the feed interconnection and common
`to Yn when viewed from the upper side.
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`interconnection of a 32-inch EL display panel;
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`In the following description, the direction in which the
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`FIG. 17 is a graph showing the correlation between the
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`direc­as the vertical run will be defined signal lines Y 1 to Y n
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`sectional area and the current density of the feed interconnec­
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`tion (colunm direction), and the direction in which the scan
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`tion and common interconnection of the 32-inch EL display
`10 lines X
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`1 to Xm run will be defined as the horizontal direction
`panel;
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`(row direction). In addition, m and n are natural numbers
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`FIG. 18 is a graph showing the correlation between the
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`(m�2, n�2). The subscript added to a scan line X represents
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`maximum voltage drop and the interconnection resistivity
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`the sequence from the top in FIG. 1. The subscript added to a
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`p/sectional area S of the feed interconnection and common
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`supply line Z represents the sequence from the top in FIG.
`1.
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`interconnection of a 40-inch EL display panel 1;
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`15 The subscript added to a signal line Y represents the sequence
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`FIG. 19 is a graph showing the correlation between the
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`from the left in FIG. 1. The first subscript added to a pixel
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`sectional area and the current density of the feed interconnec­
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`circuit P represents the sequence from the top, and the second
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`tion and common interconnection of the 40-inch EL display
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`subscript represents the sequence from the left. More specifi­
`panel;
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`cally, let i be an arbitrary natural number of 1 tom, and j be an
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`FIG. 20 is a view showing the circuit arrangement of an EL
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`20 arbitrary natural number of 1 ton, a scan line X, is the ith row
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`display panel together with an insulating substrate;
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`from the top, a supply line z, is the ith row from the top, a
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`FIG. 21 is an equivalent circuit diagram of a pixel circuit of
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`and a pixel circuit jth colunm from the left, signal line Y1 is the
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`the EL display panel;
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`P,,1 is located on the ith row from the top and the jth column
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`from the left. The pixel circuit P,,1 is connected to the scan line
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`FIG. 22 is a plan view showing the electrodes of pixel
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`25 X,, supply line z,, and signal line YJ"
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`display panel; circuits P,,1 and P,,1+l of the EL
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`The total number of feed interconnections 90 ism. A volt-
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`FIG. 23 is a sectional view taken along a plane perpendicu­
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`age VL to flow a write current and a voltage VH to flow a
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`lar to the channel width of a driving transistor;
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`driving current are applied from a left terminal 90b and right
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`FIG. 24 is a sectional view taken along a line XXIV-XXIV
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`terminal 90c on the insulating substrate 2 to each feed inter­
`in FIG.
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`connection 90. For this reason, the voltage drop of the feed
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`FIG. 25 is a sectional view taken along a line XXV-XXV in 30
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`interconnection 90 can be suppressed small as compared to
`FIG. 22;
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`when applying the voltages VL and VH from one of the left
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`FIG. 26 is a schematic view showing the coating structure
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`terminal 90b and right terminal 90c. The feed interconnec­
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`of a liquid repellent conductive film;
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`tions 90 are formed on the upper surfaces of the supply lines
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`FIG. 27 is a schematic plan view showing the layout of the
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`35 Z1 to Zm to be electrically connected to them.
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`organic EL layers of the EL display panel; and
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`The total number of common interconnections 91 is n+ 1.
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