`[11] Patent Number:
`[19]
`United States Patent
`Inagami
`[45] Date of Patent:
`Oct. 15, 1991‘
`
`
`[54] MOBILE TELEPHONE TERMINAL HAVING
`SELECTIVELY USED PROCESSOR UNIT
`FOR LOW POWER CONSUMPTION
`
`[75]
`
`Inventor:
`
`Fujio Inagami, Yokohama, Japan
`
`[73] Assignee:
`
`Fujitsu Limited, Kawasaki, Japan
`
`3/1984 Akahori etal. ..................... '455/343
`4,437,095
`4,562,307 12/1985 Bursztejin et al.
`.................... 379/61
`FOREIGN PATENT DOCUMENTS
`
`60-065317 4/1985 Japan.
`0232531
`9/1988 Japan ................................... 455/343
`
`[21] Appl. No.: 354,989
`
`[22] Filed:
`
`May 22, 1989
`
`Primary Examiner—Reinhard J. Eisenzopf
`Assistant Examiner-Andrew Faile
`
`Attorney, Agent, or Firm—Staas & Halsey
`
`[30]
`
`Foreign Application Priority Data
`
`[57]
`
`ABSTRACI‘
`
`Japan ................................ 63-123006
`May 21, 1988 [JP]
`[51]
`Int. c1.5 .......................... H0413 1/38; H04B 1/16
`[52] US. Cl. ...................................... 455/89; 455/343;
`379/61
`[58] Field of Search ............................ 455/343, 89—90,
`455/127; 379/61, 63; 320/31—32; 340/311.1,
`825.44, 825.48
`
`56
`
`]
`
`[
`
`R
`
`.
`eferences Cited
`_U-S- PATENT DOCUMENTS
`4,380,832 4/1983 Nagata et a1.
`....................... 455/343
`4,384,361
`5/1983 Masaki
`................................ 455/343
`
`A mobile telephone terminal powered by a battery,
`which terminal is mainly comprised of a processor unit
`and a logic LSI unit as a COerI part thereof. The Pro'
`cessor unit handles first control functions which are not
`used frequently but which are complicated and operate
`at a high clock speed. The logic LSI unit handles sec-
`ond control functions which are used constantly and
`frequently at a low clock speed. The processor unit is
`.
`.
`activated intermittently on demand by the logic LSI
`unit and thereby reduces power consumption.
`
`18 Claims, 11 Drawing Sheets
`
`31
`
`CONTROL
`P AR T
`
`I
`
`RADIO
`
`PART
`
`14
`
`
`
`ACTIVATION
`
`PROCESSOR
`
`
`(CPU)
`
`
`
`CLOCK
`
`L SI
`
`
`
`15
`
`BATTERY 15
`
`1
`
`APPLE 1020
`
`APPLE 1020
`
`1
`
`
`
`US. Patent
`
`Oct. 15, 1991 '
`
`Sheet 1 of 11
`
`5,058,203
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`
`Oct. 15, 1991 ~
`
`Sheet 2 of 11
`
`5,058,203
`
`Fig.2
`
`PROCESSOR
`UNIT I
`I
`
`LOGIC LSI
`UNIT 12
`
`TO CPU
`
`STOP SUPPLYING
`MASTER CLOCK
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`Sheet 4 of 11
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`5,058,203
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`Fig. A
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`US. Patent
`
`Oct. 15, 1991 ~
`
`Sheet 5 of 11
`
`5,058,203
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`Oct. 15, 1991 ‘
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`Sheet 6 of 11
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`Oct. 15, 1991 -
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`Sheet 7 of 11
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`5,058,203
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`US. Patent
`
`Oct. 15, 1991 '
`
`Sheet 8 of 11
`
`5,058,203
`
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`
`US. Patent
`
`Oct. 15, 1991
`
`Sheet 9 of 11
`
`5,058,203
`
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`
`US. Patent
`
`Oct. 15, 1991
`
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`
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`
`Oct. 15, 1991 ~
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`Sheet 11 of 11
`
`5,058,203
`
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`5,058,203
`
`MOBILE TELEPHONE TERMINAL HAVING
`SELECTIVELY USED PROCESSOR UNIT FOR
`LOW POWER CONSUMPTION
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to a mobile telephone
`terminal which is driven by a battery, particularly a
`mobile telephone terminal which can considerably re-
`duce power consumption in order to extend the life of
`the battery.
`The mobile telephone terminal of the present inven—
`tion can be applied to variety of mobile telephone termi-
`nals operated under a cellular system, such as a land
`mobile radio telephone, a shoulder type radio tele-
`phone, a portable type radio telephone and so on. The
`land mobile radio telephone and shoulder type radio
`telephone are substantially the same belonging to class
`I, producing a transmitting power of, for example, 3 W.
`The portable type radio telephone belongs to class III
`producing a transmitting power of, for example, 0.6 W.
`2. Description of the Related Art
`Especially, in the technical field of a battery feed type
`mobile telephone terminal, it is desired to reduce power
`consumption as much as possible to extend the life of
`the battery.
`In general, a mobile telephone terminal is constructed
`to use a microcomputer. This is because, the mobile
`telephone terminal requires a variety of complicated
`processes to be carried out therein. Further, it is prefer-
`able to use a microcomputer from the viewpoints of
`convenience in constructing the mobile telephone sys-
`tem, economy in building the system, and minimizing
`the scale thereof.
`
`As for the microcomputer, usually an 8 bit main cen-
`tral processing unit (CPU) and a 4 bit sub CPU are used.
`The main CPU handles terminal control, data reception
`processing, data transmission processing, timer manage-
`ment and so on. On the other hand, the sub CPU han-
`dles man-machine communication processes, such as a
`process of driving a display mounted on the mobile
`telephone terminal, a process of an operating of keys
`which are also mounted thereon. Further, the mobile
`telephone terminal requires, other than the above, base
`band processing, transmitting and receiving processing,
`and the like.
`
`As mentioned first, in the battery feed type mobile
`telephone terminal, it is desired to reduce power con-
`sumption as much as possible. For this, the circuits for
`constructing the mobile telephone terminal, including
`the above-mentioned main and sub CPU’s, are realized
`by
`complementary
`metal-oxide-semiconductor
`(CMOS) devices. As known, the CMOS device is a low
`power consumption device.
`The CMOS device is a low power consumption type
`device, but current flows therethrough every time an
`ON-OFF operation is performed therein, so that power
`supplied from the battery becomes large. As known, the
`frequency of the ON-OFF operations is proportional to
`an operating speed, or operating frequency of the
`CMOS device. Therefore, the power consumption is
`relatively large at the main CPU and memories, such as
`a read only memory (ROM) and a random access mem-
`ory (RAM), cooperating with the main CPU, since the
`main CPU and the memories work at a relatively high
`operating frequency, for example, 1 MHz or 2 MHz.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`65
`
`2
`Thus, a problem resides in that a large amount of ‘
`power supplied from the battery is needed by the main
`CPU, ROM, and RAM as long as these are operated at
`a high operating frequency. This apparently shortens
`the life of the battery.
`SUMMARY OF THE INVENTION
`
`Accordingly, an object of the present invention is to
`provide a mobile telephone terminal which operates
`with lower power consumption than that of the conven-
`tional mobile telephone terminal.
`the mobile telephone
`To attain the above object,
`terminal according to the present
`invention is con-
`structed such that a processor unit, corresponding to
`the aforesaid main CPU, performs first control func-
`tions, and a logic large scale integration (LSI) unit,
`corresponding to the peripheral units of the main CPU,
`performs second control functions. The first control
`functions used in the mobile telephone terminal are not
`used frequently but are complicated and operate at a
`high frequency. While, the second control functions are
`used constantly and frequently with a low speed clock.
`Further, the processor unit performs the first control
`functions intermittently each time a function is needed
`to be performed.
`Incidentally, the aforesaid first and second control
`functions have been both performed mainly by the pro-
`cessor unit
`(main CPU) and the memories (ROM,
`RAM).
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The above object and features of the present inven-
`tion will be more apparent from the following descrip-
`tion of the preferred embodiments with reference to the
`accompanying drawings, wherein:
`FIG. 1 is a block diagram showing principle con-
`struction of a mobile telephone terminal according to
`the present invention;
`FIG. 2 depicts a schematic flow chart for explaining
`the operation according to the present invention;
`FIG. 3 is a block diagram showing an example of a
`mobile telephone terminal according to the present
`invention;
`FIG. 4 is a brief circuit diagram of an example of a
`timing control circuit;
`FIG. 5 depicts a timing chart for explaining the cir-
`cuit of FIG. 4;
`FIG. 6 is a circuit diagram of a detailed example of
`the timing control circuit shown in FIG. 4;
`FIGS. 7A and 7B illustrate a block diagram showing
`a detailed example of the main LSI of FIG. 3;
`FIG. 8 illustrates a known data format of the control
`channel data;
`FIG. 9 illustrates a known data format of the voice
`channel data; and
`FIGS. 10A and 10B illustrate a block diagram show-
`ing a detailed example of the sub LSI of FIG. 3.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`FIG. 1 is a block diagram showing principle con—
`struction of a mobile telephone terminal according to
`the present invention. A mobile telephone terminal 10
`of FIG. 1 is primarily classified into two parts, i.e., a
`control part and a radio part. The radio part is mainly
`comprised of a transmitting and receiving (T/R) unit 13
`provided with an antenna 14. The control part is mainly
`comprised of a processor unit (CPU) 11 and a logic LSI
`
`13
`
`13
`
`
`
`3
`unit 12. All are driven by a battery 15. The present
`invention basically refers to the control part. The mem-
`bers in the control part, including the processor unit
`(CPU) 11 and the logic LSI unit 12, at least, perform a
`variety of control functions. The functions are classified
`into first control functions and second control func-
`trons.
`
`The processor unit 11 is provided to process the first
`control functions, with the cooperation of memories,
`which functions are not used frequently but are compli-
`cated and operate at a high clock speed.
`The logic LSI unit 12 is provided to process the sec-
`ond control functions which are used constantly and
`frequently with a low speed clock.
`Further, the logic LSI unit 12 is operative to activate
`the processor unit 11 every time the first control func-
`tions need to be handled by providing the high speed
`clock (CLOCK) to the processor unit 11.
`FIG. 2 depicts a schematic flow chart for explaining
`the operation according to the present invention. The
`words “ACTIVATION”, “CLOCK” and “HOLD-
`ING STATE”, used in FIG. 1 will be clarified with
`reference to FIG. 2.
`
`Referring to both FIGS. 2 and 1, suppose that the
`processor unit 11 finishes a certain process for perform-
`ing the first control functions, which is expressed as
`“FINISH PROCESSING” shown at the top left of
`FIG. 2. The processor unit 11 then enters by itself into
`a holding state
`(refer
`to “ENTER HOLDING
`STATE” in FIG. 2). The holding state is notified from
`the processor unit (CPU) 11 to the logic LSI unit 12 via
`a line 16 (shown in FIGS. 1 and 2). The logic LSI unit
`12 then operates to stop supplying a master clock (refer
`to “CLOCK” in FIG. 1) to the processor unit (CPU) 11.
`That is, no high speed clock is sent to the CPU 11 from
`the LSI 12. Soon after this, the CPU and the cooperat-
`ing memories stop operating (refer to corresponding
`block in the column of the CPU 11 in FIG. 2).
`Thus, the logic LSI unit 12 watches the status of the
`processor unit 11 and stops the supply of the high speed
`clock every time the logic LSI unit 12 detects that the
`processor unit 11 is in the holding state.
`It should be noted here that the power consumption
`of the CPU 11 and the corresponding memories be-
`comes very low due to the nature of the CMOS devices,
`after stoppage of the clock supplied to the CPU 11.
`The logic LSI unit 12 continuously supervises
`whether a processing to be achieved by the processor
`unit (CPU) 11 is generated in the telephone terminal
`(refer to the step “IS PROCESSING BY CPU GEN-
`ERATED?” in FIG. 2). If it is detected by the LSI 12
`that the related processing is generated, then the proces-
`sor unit (CPU) 11 is activated (refer to “ACTIVA-
`TION OF CPU” in FIG. 2 and line 17 in FIG. 1). At
`the same time, or preceding the activation of the CPU,
`the logic LSI unit 12 resupplies the high speed clock
`(master clock) (refer to “CLOCK” in FIG. 1) to the
`CPU 11. The CPU 11 then starts the related processing
`(refer to “START PROCESSING” in FIG. 2), which
`will finally end again at the step “FINISH PROCESS-
`ING”. The above-mentioned “ACTIVATION” is trig—
`gered preferably by issuing an interrupt request to the
`CPU 11 from the LSI 12.
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`4O
`
`45
`
`50
`
`55
`
`As understood from the above, the total power con—
`sumption in the mobile telephone terminal is greatly
`reduced, since the processor unit (CPU) 11 and the
`cooperating memories work intermittently,
`i.e., at a
`relatively low frequency, wherein the processor unit 11
`
`65
`
`5,058,203
`
`'
`
`4
`and the memories usually operate at a high speed clock
`and thereby are high power consumption members.
`FIG. 3 is a block diagram showing an example of a
`mobile telephone terminal according to the present.
`invention. In FIG. 3, reference numeral 11 represents
`the processor unit as shown in FIG. 1, which unit 11 is
`comprised of a main CPU having memories, i.e., ROM
`18 and RAM 19 cooperating therewith. The main CPU
`11 is, for example, an 8 bit microcomputer. The ROM
`18 stores therein a program to operate the processor
`unit (main CPU) 11. The RAM 19 stores therein data
`for read and write operations. As will be understood
`later, the program in the ROM 18 should not be autono-
`mous but subject to an external command issued from
`the logic LSI unit 12. Then CPU 11 and the memories
`operate at a frequency of, e.g.,
`1 MHz (or 2 MHz),
`which frequency is obtained by dividing in frequency
`the output signal from a master clock source 25 of 4
`MHz (or 8 MHz).
`The logic LSI unit 12 is, in FIG. 3, comprised of a
`main LSI 21 and a sub LSI 22 which are respectively
`provided with a memory (ROM) 23 and a memory
`(ROM) 24. The ROM 23 stores therein system informa-
`tion, for example, a telephone number allotted to this
`mobile telephone terminal and an area number of an
`area determined under a contract between a user and a
`dealer. The ROM 24 stores a serial number, for exam-
`ple, a production lot number of this mobile telephone
`terminal, which lot number is determined by its maker
`when making the mobile telephone number. It should
`be understood that the logic LSI unit 12 is divided into
`the main LSI 21 and the sub LSI 22 due merely to a
`factor in actual design. That is, even though it is possi-
`ble to construct the logic LSI unit 12 using a single LSI,
`the number of pins provided by the single LSI chip
`becomes extremely large. This being so, it is convenient
`to construct the logic LSI unit 12 with two general
`purpose LSI chips 21 and 22.
`The mobile telephone terminal has further members,
`other than the above recited members. Reference nu-
`meral 30 represents the aforesaid radio part, as in FIG.
`1, comprising the transmitting and receiving (T/R) unit
`13 and the antenna 14. Reference numeral 40 represents
`a base band part which is mainly comprised of a digital
`base band (D-BB) unit 41 and an analog base band
`(A—BB) unit 42. The analog base band unit 42 contains
`therein, for example, analog filters, and deals with ana-
`log voice signals. The voice signal
`is communicated
`through a microphone 44 and a speaker 45. A voice
`signal amplifier 43 is located therebetween.
`Reference numeral 50 represents a man-machine in-
`terface part which is mainly comprised of a sub CPU 51
`of, for example, a 4 bit type, a display (DSP) 52, and a
`key switch (KEY) 53. The display 52 acts as an indica-
`tor. The key switch 53 contains function keys, numeral
`buttons (“0” through “9”), volume switches, a send
`command button, an end indication button, and so on.
`All members are energized by the battery 15. For sav-
`ing the power of the battery 15, major members, such as
`11, 13, 18, 19, 21, 22, 23, 24, 41, 42, are fabricated using
`CMOS devices. The display 52, for example having a 16
`digit construction, is comprised of, for example, a liquid
`crystal device which is, as is known, a low power con-
`sumption device.
`The sub CPU 51 controls the display 52 and the key
`switch 53 periodically at 5 ms intervals. The man-
`machine interface part 50 is constructed exclusively, as
`
`14
`
`14
`
`
`
`5,058,203
`
`5
`in the prior art. The part 50 and also the parts 30 and 40
`are identical to those of the prior art.
`As mentioned above, the control functions performed
`in the control part, are shared by the logic LSI unit and
`the processor unit. This will further be clarified below.
`
`Logic LSI unit 12
`
`I. Data reception processing
`(a) Contents of the data reception processing
`1) Data reception processing
`The data reception rate is:
`10K Baud, when the Advance Movable Phone
`System (AMPS) is employed; and
`8K Baud, when the Total Access Communication
`System (TACS) is employed.
`2) Decision by majority for words
`Generally, the received data is composed of words
`repeated, for example, 5 times, so as to improve
`reliability of the data. In the example, a 3/5 major-
`ity is adopted. That is, if three normal bits among
`five bits that are located at the same position of
`each word are obtained, the non-normal bits can be
`corrected.
`3) Error correction of received data
`Generally, a Bose-Chaudhuri-Hocqueghem (BCH)
`code is utilized for the error correction of data.
`4) Decision by majority for B/I bit
`A busy/idle (B/I) bit is periodically monitored in the
`mobile telephone terminal so as to perform duplex
`communication. In the example, a § majority is
`adopted. That is, if two normal B/I bits among last
`three B/I bits of receiving data are obtained, the
`B/I state can be determined by noting the majority.
`5) B/I bit processing
`In the processing, it is checked whether it is possible
`to send data to the land station.
`(b) Operation timing
`The logic LSI unit 12 operates at each interrupt sent
`at 100 its intervals to the processor unit 11.
`(II) High speed timer management
`(a) Contents of the management
`Many functions are achieved at respective prescribed
`timings which are controlled by timers.
`1) For example, if three kinds of timers are managed,
`each of the timers has a resolution of 1 ms.
`2) As another example, if seven kinds of timers are
`managed, each of the timers has a resolution of 10
`ms.
`
`(b) Operation timing
`The logic LSI unit 12 operates at 1 ms intervals.
`To be specific, in FIG. 3, the main LSI 21 handles the
`above-recited data reception processing, while the sub
`LSI 22 handles the above-recited high speed timer man-
`agement.
`
`Main CPU 11
`
`(I) Terminal control
`A call origination, a call termination, and a registra-
`tion of the location of the mobile telephone terminal are
`subjected to terminal control.
`(II) Data transmission processing
`(a) Contents of the processing
`The data to be transmitted from the mobile telephone
`terminal is processed by the main CPU 11.
`(b) Operation timing
`The operation is started any time the data transmis-
`sion is required.
`(III) Low speed timer management
`
`10
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`15
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`20
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`25
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`30
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`35
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`45
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`50
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`55
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`65
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`6
`(a) Contents of the management
`As mentioned before, many functions are achieved at
`respective prescribed timings which are controlled by
`timers.
`’
`.
`1) For example, if six kinds of timers are managed,
`each of the timers has a resolution of 50 ms.
`‘
`2) As another example, if three kinds of timers are
`managed, each of the timers has a resolution of 2
`seconds.
`
`(b) Operation timing
`The main CPU is operated by receiving an interrupt
`given every 50 ms. To be specific, the related interrupt
`request is generated in the sub LSI 22.
`Referring again to FIG. 3, the received signal is input
`to the mobile telephone terminal by way of the antenna
`14 and the transmitting and receiving unit (T/R) 13.
`The received signal is first supplied to the analog base
`band (A-BB) unit 42 in which a filtering operation is
`applied to the received signal. The thus filtered signal is
`supplied, via the bus 20, to the digital base band (D-BB)
`unit 41. The data from the unit 41 is applied to the main
`LSI 21. As mentioned previously, the main LSI 21 and
`sub LSI 22 cooperate together.
`The main CPU 11 is operated on demand according
`to an activation by the logic LSI unit 12. When the main
`CPU 11 is operated, the ROM 18 and the RAM 19 also
`start operating in accordance with an access thereto by
`the CPU 11.
`The data to be transmitted from the CPU 11 is trans-
`
`ferred along a path opposite to the one mentioned
`above. That is, the transmission data is transferred from
`the CPU 11 to the antenna 14 through the main LSI 21,
`the digital base band unit 41, the analog base band unit
`42 and the transmitting and receiving unit 13.
`The logic LSI unit 12 watches a logic level on a bus
`available (BA) signal line 16 which is connected be-
`tween the logic LSI unit 12 and the processor unit (main
`CPU) 11 and, when the logic level on the BA signal line
`16 assumes first logic level, e.g., logic “H” (high), the
`logic LSI unit 12 detects that the processor unit 11 is in
`the holding state. The logic “H” on the line 16 is pro-
`duced by executing a “Wait for interrupt” instruction.
`In this case, the processor unit 11 enters by itself into
`said holding state by an execution therein of the “Wait
`for Interrupt” instruction generated for each process
`when the aforesaid first control functions are finished.
`Thus, the main LSI 21 supplies the master clock from
`the master clock source 25 or stops supplying the same
`according to logic “L” (low) or “H” of the signal BA
`(bus available) on the line 16 (a line for transferring the
`master clock is not illustrated in FIG. 3). The master
`clock is supplied together with an issuance of the inter-
`rupt request (IRQ). The logic LSI unit 12 issues the
`interrupt request IRQ relating to the aforesaid “Wait
`for Interrupt” instruction to the processor unit 11, every
`time an interrupt (IRQ-R) occurs in the logic LSI unit
`12, each of which interrupts require an activation of the
`processor unit (main CPU) 11.
`FIG. 4 is a brief circuit diagram of an example of a
`timing control circuit. The timing control circuit 60 is
`mounted in the logic LSI unit 12 and produces the
`aforesaid master clock M-CLK and the interrupt re-
`quest IRQ sent to the processor unit (main CPU) 11
`according to the input signals, i.e., the signal BA and the
`interrupt IRQ-R.
`FIG. 5 depicts a timing chart for explaining the cir-
`cuit of FIG. 4. The operation of the timing control
`circuit 60 will be explained below with reference to
`
`15
`
`15
`
`
`
`5,058,203
`
`7
`FIG. 5. The interrupt request IRQ is issued immediately
`after the occurrence of any one of the interrupts IRQ-R
`when the related interrupt occurs during a condition
`where the logic level on the BA signal line 16 assumes
`a second logic level, e.g., “L”, which indicates that the
`processor unit (main CPU) 11 is not in the holding state
`but in the operating state. The interrupt request IRQ is
`issued after a predetermined delay time from the occur-
`rence of anyone of the interrupts IRQ-R when the re-
`lated interrupt IRQ-R occurs during the holding state
`where the logic level on said BA signal line 16 assumes
`the first logic level, e.g., “H”.
`The aforesaid predetermined delay time is a time
`required for preparation of the high speed clock (1 MHz
`or 2 MHz) which can normally drive the processor unit
`11.
`
`The high speed clock is obtained by dividing in fre—
`quency the master clock M-CLK from the logic LSI
`unit 12, at the source 25.
`The logic LSI unit 12 contains therein a delay means
`62 which provides a delay conforming to the prepara-
`tion of the high speed clock which is lower than the
`speed of said master clock M-CLK (4 MHZ or 8 MHz)
`produced by the master clock source 25 provided by
`the logic LSI unit 12.
`The master clock M—CLK is given to the processor
`unit 11 via a first logic means 61 which receives two
`inputs, one of which is the logic level on the BA signal
`line 16, and the other of which is the interrupt IRQ-R.
`The first logic means 61 operates to produce the
`master clock M-CLK, regardless of an existence of the
`interrupt IRQ-R (“L”), when the logic level on the BA
`signal line 16 assumes the second logic level, e.g., “L”.
`The first logic means 61 operates to start producing the
`master clock M-CLK, when at the occurrence of the
`interrupt IRQ-R (“L”) during a condition where the
`logic level on the BA signal line 16 assumes the first
`logic level (“H"), i.e., during the holding state.
`The interrupt request IRQ is issued to the processor
`unit 11 via a second logic means (delay means) 62 which
`receives two inputs, one of which is the logic level on
`the BA signal line 16, and the other of which is the
`interrupt IRQ-R.
`The second logic means 62 operates to produce'the
`interrupt request IRQ immediately after the reception
`of the interrupt IRQ-R, when the logic level on the BA
`signal line 16 assumes the second logic level, e.g., “L”,
`and produces the interrupt request IRQ after the afore-
`said predetermined delay time, when the logic level on
`the BA signal line 16 assumes the first logic level, e.g.,
`
`In the first logic means 61, when the signal BA as-
`sumes a logic level “L”, and at the same, the interrupt
`IRQ-R is generated in the logic LSI unit 12, a NAND
`gate 63 produces an output of logic level “H”. There-
`fore,
`the master clock M-CLK is supplied from the
`clock source 25 to the processor unit (main CPU) 11 via
`an AND gate 64. The interrupt request IRQ is sent to
`the processor unit 11, in response to the interrupt IRQ-
`R, Via the second logic means, i.e., delay means 62, and
`a buffer gate 65. The processor unit 11 is then activated
`and starts operating at the speed of, for example, 1 MHz
`or 2 MHz. That is, the main CPU 11 divides in fre-
`quency the received master clock M-CLK (4 MHz or 8
`MHz).
`When the BA signal assumes an “H” level, the master
`clock M—CLK is stopped. The main CPU 11 is then
`
`8
`stopped from operating, as are the ROM 18 and the
`RAM 19.
`
`5
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`20
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`30
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`35
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`45
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`50
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`65
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`When the BA signal assumes an “H” level, and at the
`same time, the interrupt IRQ-R is generated in the logic.
`LSI unit 12, the interrupt request IRQ is issued after an
`elapse of a predetermined time from the generation of ~
`the interrupt IRQ-R. The reason why the IRQ is issued
`after a certain elapse of time is that, if the BA signal
`assumes a logic level “L”, the main CPU 11 is under
`operation (in an operating state), and therefore the main
`CPU 11 can be immediately responsive to the IRQ.
`However, if the BA signal assumes a logic “H”, the
`main CPU 11 is in the holding state, and therefore, a
`certain delay time is necessary before an actual genera-
`tion of the clock which drives the main CPU 11. The
`delay time is created by the delay means 62. According
`to FIG. 5, the delay time corresponds to four pulses of
`the master clock M—CLK, the first pulse rises at the
`second change of the IRQ-R. As mentioned before, in
`this embodiment, the clock used in the main CPU 11 has
`a frequency of 1 MHz (or 2 MHz) which is obtained by
`dividing the M-CLK of 4 MHz (or 8 MHz), by “4”.
`Thus, the aforesaid four pulses of the M-CLK corre-
`spond to the delay time.
`FIG. 6 is a circuit diagram of a detailed example of
`the timing control circuit shown in FIG. 4. The timing
`control circuit 60 of FIG. 4 has a construction as shown
`in FIG. 6 and is mounted in the logic LSI unit 12, partic-
`ularly in the main LSI 21. The members identical to
`those of FIG. 4 are referenced by the same reference
`numerals and characters. The logic part 71 determines
`the issuance of the interrupt request IRQ via an AND
`gate 72. The AND gate 72 is opened after the elapse of
`the aforesaid delay time. The AND gate 72 receives the
`output from a logic part 73 via a logic part 74. The logic
`part 74 holds the output from the preceding logic part
`73 by means of a flip-flop (FF). The logic part 73 pro-
`duces the aforesaid delay time by means of a counter
`which receives the master clock from the clock source
`25. When the higher 4 output bits in the counter all go
`to a logic level “H”, the output of the logic part changes
`the status of the flip—flop (FF) in the logic part 74 to
`open the AND gate 72. The aforesaid counter is reset
`by an IRQ-RESET pulse which is generated in the main
`LSI 22 so as to rapidly reset the level of the IRQ line 17.
`If the level is maintained at “L” for a long time, it is
`impossible to respond to the next IRQ. Accordingly,
`the level of the IRQ line 17 is returned to the usual state
`soon after the issuance of the IRQ.
`FIGS. 7A and 7B illustrate a block diagram showing
`a detailed example of the main LSI 21 in FIG. 3. The
`data bus 20 at the top left in FIG. 7A is connected by 8
`data lines DD through D7, with the processor unit (main
`CPU) 11. Below the data bus 20, an input address bus is
`shown. An internal address decoder 82 specifies internal
`registers 83 through 87 and also specifies, via an address
`decoder 81, the external memories, such as the ROM 18,
`the RAM 19 and so on (SUBLSIZZ, D-BB4l). The regis-
`ter 83 cooperates with a serial data out/in unit 91 which
`handles the input data or output data to be communi-
`cated with, via the sub CPU 51, the display 52 and the
`key switch 53. The main LSI 21 operates at the low
`clock speed, for example, 96 KHz. The clock of 96 KHz
`is used, on one hand, after division in frequency by a
`clock divider 92. On the other hand, the clock of 96
`KHZ is used for driving an internal interval timer 93
`which controls a timer processing unit 94 and an IRQ
`controller 95. The IRQ controller 95 also cooperates
`
`16
`
`16
`
`
`
`9
`with the IRQ processing register 84 which registers
`what interrupt (IRQ-R) is generated. The unit 94 han-
`dles the aforesaid high speed timer management. The
`corresponding register 85 for the timer registers a vari-
`ety of management times, written by CPU 11. The IRQ
`controller 95 receives a variety of interrupt IRQ-R. One
`important IRQ-R is given from a BCH decoder 97
`(FIG. 7B) which handles the aforesaid error correction
`of the received data in terms of a BCH code. If the data
`
`is received, the decoder 94 sends the IRQ-R to the
`controller 95. Another IRQ-R is generated when, for
`example, a battery problem occurs.
`In FIG. 7B, the above-mentioned BCH decoder 97
`receives data processed by members 101 through 105
`which commonly connect with a word synchronization
`detection unit 106. The unit 106 is provided with the
`received data (RDAT) and also the corresponding re-
`ceived clock (RCLK). The member 101 handles the
`aforesaid decision by majority for bits. The member 102
`handles the aforementioned decision by majority for the
`busy/idle (B/I) bit. The member 103 is a word synchro-
`nization protection unit which determines that word
`synchronization is established when the synchroniza-
`tion is detected two times successively, and on the other
`hand, determines that
`the word synchronization is
`maintained until the synchronization is not detected five
`times successively. The members 104 and 105 are timing
`generators for dealing with voice (V) channel data and
`control (C) channel data, respectively, both channel
`data will be explained later.
`The member 96 is a master cloc