[19]
`United States Patent
`6,163,721
`[11] Patent Number:
`[45] Date of Patent: Dec. 19, 2000
`Thompson
`
`
`
`US006163721A
`
`[54]
`
`POWER CONSUMPTION REDUCTION IN
`MEDICAL DEVICES BY EMPLOYING
`PIPELINE ARCHITECTURE
`
`[75]
`
`Inventor: David L. Thompson, Fridley, Minn.
`
`[73]
`
`Assignee: Medtronic, Inc., Minneapolis, Minn.
`
`[21]
`
`Appl. No.: 09/289,502
`
`[22]
`
`Filed:
`
`Apr. 9, 1999
`
`.
`
`3/1994 Blanchette et a1.
`5,292,343
`7/1994 Nichols et a1.
`.
`5,330,513
`2/1995 Yomtov et a1.
`.
`5,388,578
`9/1995 Peterson .
`5,447,519
`11/1995 Neumann .
`5,464,435
`3/1996 Plicchi et a1.
`5,496,351
`10/1996 Yerich et a1.
`5,562,711
`3/1997 Chan et al.
`.
`5,610,083
`5,683,432 11/1997 Goedeke et a1.
`5,730,142
`3/1998 Sun et al.
`.
`5,778,881
`7/1998 Sun et al.
`.
`5,782,888
`7/1998 Sun et al.
`.
`
`.
`
`.
`
`.
`
`Related US. Application Data
`
`OTHER PUBLICATIONS
`
`[63]
`
`r—ir—ir—iUIUIUI00l\.)>—k|_1|_1|_4
`
`[56]
`
`Continuation—in—part of application No. 09/067,881, Apr. 29,
`1998, abandoned, and a continuation—in—part of application
`No. 09/181,460, Oct. 28, 1998, and a continuation—in—part of
`application No. 09/181,459, Oct. 28, 1998, and a continua—
`tion—in—part of application No. 09/181,517, Oct. 28, 1998,
`and a continuation—in—part of application No. 09/181,523,
`Oct. 28, 1998.
`
`Int. Cl.7 ....................................................... A61N 1/36
`US. Cl.
`................................................................... 607/2
`Field of Search .................. 607/2, 9, 5; 395/750.03,
`395/750.04, 750.07, 800.32, 800.33, 800.34,
`556, 555, 557
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`.
`
`.
`
`6/1977 Renirie .
`4,031,899
`1/1984 Anderson et a1.
`4,428,378
`7/1984 Masuoka .
`4,460,835
`4,561,442 12/1985 Vollmann et a1.
`4,663,701
`5/1987 Stotts .
`.
`4,791,318 12/1988 Lewis et a1.
`4,791,935
`12/1988 Baudino et a1.
`5,022,395
`6/1991 Russie .
`.
`5,052,388 10/1991 Sivula et a1.
`5,154,170 10/1992 Bennett et a1.
`5,185,535
`2/1993 Farb et a1.
`.
`5,187,796
`2/1993 Wang et a1.
`
`.
`
`.
`
`.
`
`Jan Mulder et al., “Application of the Back Gate in MOS
`Weak Inversion Translinear Circuits,” IEEE Transactions on
`Circuits and Systems—I: Fundamental Theory and Appli-
`cations, vol. 42, No. 11, Nov. 1995.
`
`Primary Examiner—Scott M. Getzow
`Attorney, Agent, or Firm—Thomas F. Woods; Harold R.
`Patton; Girma Wolde-Michael
`
`[57]
`
`ABSTRACT
`
`Power consumption in medical and battery powered devices
`is reduced through the use and operation of pipeline archi-
`tecture in a digital signal processor, microcontroller or
`microprocessor by operating such devices at clock frequen-
`cies tailored to conserve power while preserving computa-
`tional and executional performance. The digital signal
`processor, microcontroller or microprocessor can be oper-
`ated at lower clock frequencies relative to those that would
`be required by one of such processors to complete the
`multiple functions within a predetermined time period but
`having no pipeline architecture. With reduced clock
`frequency, power consumption is reduced. Further, with
`reduced clock speed, supply voltages applied to such pro-
`cessors may also be reduced.
`
`63 Claims, 20 Drawing Sheets
`
`Back Gate
`Bias 8V1
`
`Back Gate
`Bias 8V2
`
`Voltage
`V1
`
`511990
`Voltage
`
`
`
`
`Back Gate
`Bias BVn
`
`1
`
`APPLE 1019
`
`1
`
`APPLE 1019
`
`

`

`US. Patent
`
`Dec. 19,2000
`
`Sheet 1 0f 20
`
`6,163,721
`
`Energy Delay
`
`' 1.0
`
`2.4
`
`3.5
`
`5.2
`
`6.6
`
`supply voltage (volts)
`
`FIG.
`
`I
`
`V00 /
`
`G 2
`
`G 1
`
`0 2 (PMOS)
`
` ;/ 12
`
`0 1 (mos)
`
`51\14
`
`2
`
`

`

`US. Patent
`
`Dec. 19, 2000
`
`Sheet 2 0f 20
`
`6,163,721
`
`
`
`FIG. 3
`
`3
`
`

`

`US. Patent
`
`Dec. 19,2000
`
`Sheet 3 0f 20
`
`6,163,721
`
`
`
` n cycles
`
`
`
` n cycles
`
`
`
`4
`
`

`

`US. Patent
`
`Dec. 19, 2000
`
`Sheet 4 0f 20
`
`6,163,721
`
`Back Gate
`Bios BV1
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`Bios BVn
`
`V°'t°9"
`
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`
`Back Gate
`Bias 8V2
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`
`5
`
`

`

`US. Patent
`
`Dec. 19,2000
`
`Sheet 5 0f 20
`
`6,163,721
`
`155
`
`
`
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`

`

`US. Patent
`
`Dec. 19,2000
`
`Sheet 6 0f 20
`
`6,163,721
`
`208
`
`Clock
`Control
`
`
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`
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`21 2
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`
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`Bias
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`
`
`
`214
`
`FIG. 7
`
`7
`
`

`

`US. Patent
`
`Dec. 19, 2000
`
`Sheet 7 0f 20
`
`6,163,721
`
`
`
`FIG. 8
`
`8
`
`

`

`US. Patent
`
`Dec. 19, 2000
`
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`6,163,721
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`US. Patent
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`Dec. 19, 2000
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`6,163,721
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`US. Patent
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`Dec. 19,2000
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`US. Patent
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`Dec. 19,2000
`
`Sheet 12 0f 20
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`6,163,721
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`US. Patent
`
`Dec. 19,2000
`
`Sheet 13 0f 20
`
`6,163,721
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`US. Patent
`
`Dec. 19,2000
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`Sheet 14 0f 20
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`6,163,721
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`US. Patent
`
`Dec. 19, 2000
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`Dec. 19,2000
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`6,163,721
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`Dec. 19, 2000
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`US. Patent
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`Dec. 19,2000
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`Sheet 20 0f 20
`
`6,163,721
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`

`

`1
`POWER CONSUMPTION REDUCTION IN
`MEDICAL DEVICES BY EMPLOYING
`PIPELINE ARCHITECTURE
`
`CLAIM TO PRIORITY AND REFERENCE TO
`RELATED APPLICATION
`
`This application is a Continuation-In-Part and claims
`priority and other benefits from the filing dates of the
`following patent applications: (1) US. patent appln. Ser. No.
`09/067,881 for “Power Consumption Reduction in Medical
`Devices Using Multiple Supply Voltages and Clock Fre-
`quency Control” to Thompson, filed Apr. 29, 1998, and now
`abandoned; (2) US. patent appln. Ser. No. 09/181,460 for
`“Power Consumption Reduction in Medical Devices
`Employing Multiple Digital Signal Processors” to
`Thompson, filed Oct. 28, 1998; (3) US. patent appln. Ser.
`No. 09/181,459 for “Power Consumption Reduction in
`Medical Devices By Employing Different Supply Voltages”
`to Thompson, filed Oct. 28, 1998; (4) US. patent appln. Ser.
`No. 09/181,517 for “Power Consumption Reduction in
`Medical Devices Employing Multiple Supply Voltages and
`Clock Frequency Control” to Thompson, filed Oct. 28, 1998;
`and (5) US. patent appln. Ser. No. 09/181,523 for “Power
`Consumption Reduction in Medical Devices Employing
`Multiple Digital Signal Processors and Different Supply
`Voltages” to Thompson, filed Oct. 28, 1998, all hereby
`incorporated by reference herein in their respective entire-
`ties.
`
`FIELD OF THE INVENTION
`
`The present invention relates to the reduction of power
`consumption in integrated circuit designs, such as integrated
`circuits employed in medical devices, particularly implant-
`able medical devices.
`
`BACKGROUND OF THE INVENTION
`
`Various devices require operation with low power con-
`sumption. For example, hand-held communication devices
`require such low power consumption and,
`in particular,
`implantable medical devices require low power capabilities.
`With respect to implantable medical devices, for example,
`microprocessor-based implantable cardiac devices, such as
`implantable pacemakers and defibrillators, are required to
`operate with a lower power consumption to increase battery
`life and device longevity.
`Generally, such low power devices are designed using
`complementary metal oxide semiconductor (CMOS) tech-
`nology. CMOS technology is generally used because such
`technology has the characteristic of substantially zero
`“static” power consumption.
`Power consumption of CMOS circuits consists generally
`of two power consumption factors, namely “dynamic”
`power consumption and static power consumption. Static
`power consumption is only due to current leakage as the
`quiescent current of such circuits is zero. Dynamic power
`consumption is the dominant factor of power consumption
`for CMOS technology. Dynamic power consumption is
`basically due to the current required to charge internal and
`load capacitances during switching, i.e., the charging and
`discharging of such capacitances. Dynamic power (P)
`equals: 1/2CVDD2F, where C is nodal capacitance, F is the
`clock or switching frequency, and VDD is the supply voltage
`for the CMOS circuit. As can be seen from the formula for
`
`calculating dynamic power (P), such dynamic power con-
`sumption of CMOS circuits is proportional to the square of
`
`6,163,721
`
`2
`
`5
`
`10
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`15
`
`20
`
`25
`
`30
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`35
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`40
`
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`60
`
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`
`the supply voltage (VDD). In addition, dynamic power (P) is
`proportional to switching or clock frequency (F).
`In accordance with the formula for dynamic power
`consumption, it has been effective in conventional CMOS
`integrated circuit designs to scale down the supply voltage
`for an entire device (e.g., hybrid) or integrated circuit (IC),
`i.e., operate the circuit at low supply voltages, to reduce
`power consumption for such designs. For example, in the
`MEDTRONIC SPECTRAX® device of circa 1979,
`IC
`circuitry was powered by one lithium iodine cell (as opposed
`to the two cells of the prior art). This reduced the supply
`voltage to 2.8 volts from 5.6 volts, thus reducing overhead
`current. Voltages required to be greater than 2.8 volts were
`generated by a voltage doubler, or alternatively by a charge
`pump (e.g., output pacing pulses). Further, for example, in
`the MEDTRONIC SYMBIOS® device of circa 1983, logic
`circuitry was powered by a voltage regulator controlling the
`IC supply voltage to a “sum of thresholds” supply. This
`regulator provided a supply to the IC (i.e., VDD) of several
`hundred millivolts above the sum of the n-channel and
`
`p-channel thresholds of the CMOS transistors making up the
`IC. This regulator was self calibrating regarding manufac-
`turing variations of the transistor thresholds.
`Other devices have reduced power consumption in other
`manners. For example, various device designs have shut-
`down analog blocks and/or shut-off clocks to logic blocks
`not being used at particular times, thereby reducing power.
`Further, for example, microprocessor based devices have
`historically used a “burst clock” design to operate a micro-
`processor at a very high clock rate (e.g., generally 500—1000
`Kilohertz (KHz)), for relatively short periods of time to gain
`the benefit of a “duty cycle” to reduce average current drain.
`A much lower frequency clock (e.g., generally 32 KHZ) is
`used for other circuitry and/or the processor when not in the
`high clock rate mode, i.e., burst clock mode. Many known
`processor based implanted devices utilize the burst clock
`technique. For example, implanted devices available from
`Medtronic, Vitatron, Biotronic, ELA,
`Intermedics,
`Pacesetters, InControl, Cordis, CPI, etc., utilize burst clock
`techniques. A few illustrative examples which describe the
`use of a burst clock are provided in US. Pat. No. 4,561,442
`to Vollmann et al., entitled “Implantable Cardiac Pacer With
`Discontinuous Microprocessor Programmable Anti Tachy-
`cardia Mechanisms and Patient Data Telemetry,” issued
`Dec. 31, 1985; US. Pat. No. 5,022,395 to Russie, entitled
`“Implantable Cardiac Device With Dual Clock Control of
`Microprocessor,” issued Jun. 11, 1991; US. Pat. No. 5,388,
`578 to Yomtov et al., entitled “Improved Electrode System
`For Use With An Implantable Cardiac Patient Monitor,”
`issued Feb. 14, 1995; and US. Pat. No. 5,154,170 to Bennett
`et al., entitled “Optimization for Rate Responsive Cardiac
`Pacemaker,” issued Oct. 13, 1992.
`FIG. 1 represents a graphical illustration of energy/delay
`versus supply voltage for CMOS circuits such as a CMOS
`inverter 10 shown in FIG. 2 for illustrative purposes. The
`inverter 10 is provided with a supply voltage, VDD, which is
`connected to the source of a PMOS field effect transistor
`
`(FET) 12. PMOS FET 12 has its drain connected to the drain
`of an NMOS FET 14 whose source is connected to ground.
`In this configuration, an input Vl- applied to both the gates of
`FETs 12, 14 is inverted to provide output V0. Simply stated,
`one clock cycle, or logic level change, is used to invert the
`input Vi to V0.
`As shown in FIG. 1, the circuit logic delay increases
`drastically as the supply voltage is reduced to near one volt,
`as represented by delay line 16 and energy/delay line 18. As
`such, reducing of the supply voltage (VDD) continuously to
`22
`
`22
`
`

`

`6,163,721
`
`3
`lower levels is impractical because of the need for higher
`supply voltages when higher frequency operation is
`required. For example, generally CMOS logic circuits must
`periodically provide functionality at a higher frequency, e.g.,
`burst clock frequency. However, as the supply voltage (VDD)
`is decreased, such energy consumption is reduced by the
`square of the supply voltage (VDD) as is shown by energy
`consumption line 20. Therefore, speed requires a higher
`supply voltage (VDD) which is in direct conflict with low
`power consumption.
`Other problems are also evident when lower supply
`voltages (VDD) are used for CMOS circuit designs. When a
`lower supply voltage is selected, static leakage current
`losses may arise, particularly at lower frequencies, due to
`increased static leakage current losses.
`Various techniques for reducing power consumption in
`devices are known in the art, some examples of which may
`be found in at least some of the references listed in Table 1
`below.
`
`TABLE 1
`
`Patent No.
`
`Inventor
`
`Issue Date
`
`4,031,899
`4,460,835
`4,561,442
`4,791,318
`5,022,395
`5,154,170
`5,185,535
`5,187,796
`5,388,578
`5,610,083
`
`Renirie
`Masuoka
`Vollmann et al.
`Lewis et al.
`Russie
`Bennett et al.
`Farb et al.
`Wang et al.
`Yomtov et al.
`Chan et al.
`
`Jun. 28, 1977
`Jul. 17, 1984
`Dec. 31, 1985
`Dec. 13, 1988
`Jun. 11, 1991
`Oct. 13, 1992
`Feb. 9, 1993
`Feb. 16, 1993
`Feb. 14, 1995
`Mar. 11, 1997
`
`All references listed in Table 1 above are hereby incor-
`porated by reference herein, each in its respective entirety.
`As those of ordinary skill in the art will appreciate readily
`upon reading the Summary of the Invention, Detailed
`Description of the Embodiments, and Claims set forth
`below, at least some of the devices and methods disclosed in
`the publications, patents or patent applications referenced in
`the present application,
`including those disclosed in the
`references listed in Table 1 above, may be modified advan-
`tageously in accordance with the teachings of the present
`invention.
`
`SUMMARY OF THE INVENTION
`
`The present invention has certain objects. That is, various
`embodiments of the present invention provide solutions to
`one or more problems existing in the prior art respecting
`circuitry design having lower power consumption, particu-
`larly with respect to implantable medical devices. Those
`problems include: CMOS, CML, SOS, SOI, BICMOS,
`PMOS and/or NMOS circuits having excessive dynamic
`power consumption which reduces battery life; the inability
`to utilize low voltage supply levels effectively;
`lack of
`ability to provide adequate processing capabilities such as
`high processing capabilities including telemetry uplink/
`downlink, morphology detection, initialization of devices,
`while still providing low processing capabilities such as
`sensing intrinsic beats, pacing, low speed telemetry, with the
`desired power consumption; and the inability to provide
`circuit designs that operate at lower frequencies and thus
`lower power consumption as opposed to the use of higher
`speed clocks such as burst clocks.
`In comparison to known techniques for reducing power
`consumption in circuit designs, various embodiments of the
`
`4
`present invention may provide one or more of the following
`advantages: reduced power consumption through the use of
`multiple digital signal processing (DSP) systems; reduced
`power consumption through the use of a lower voltage
`supply (VDD); reduced power consumption by decreased
`clock frequency for circuit designs; increased longevity of
`circuits, particularly implantable device circuitry; provide a
`potential reduction in product size; providing high perfor-
`mance processing designs with additional features or func-
`tions due to the ability to reduce power with respect to other
`“required” features and functions;
`reduced static power
`consumption; providing multi-processor designs and DSP
`designs having additional features or functions due to the
`ability to reduce power with respect to other “required”
`features and functions; reduced current drain for an overall
`design, even when operating analog circuitry at higher
`supply voltages relative to the supply voltages applied to
`digital circuitry of the design.
`Some embodiments of the invention include one or more
`
`of the following features: two or more digital signal pro-
`cessing systems; multiple processors, each performing func-
`tions at lower clock frequencies to reduce power consump-
`tion; a first and second digital signal processor operating on
`data representative of analog inputs to perform respective
`first and second functions at respective first and second
`clock frequencies during a predetermined time period with
`the first and second clock frequencies being such that the
`power consumed by the first and second digital signal
`processors during performance of such functions is less than
`the power that would be consumed if only one of the
`processors were to perform the functions within the time
`period; multiple digital signal processors having supply
`voltages that are reduced based on the reduction of clock
`frequency for such processors; providing analog inputs, e. g.,
`cardiac sense signals, to the multiple processors for use in
`performing functions such as T-wave, P-wave, and R-wave
`detection; one or more analog circuits of a medical device
`(e.g., an atrial sense amplifier, a ventricular sense amplifier,
`a T-wave amplifier, one or more bandpass filters, one or
`more detection circuits, one or more sensor amplification
`circuits, one or more physiological signal amplification
`circuits, one or more output circuits, a battery monitor
`circuit, and/or a power on reset circuit) and one or more
`digital circuits of the medical device (e.g., a processor, a
`controller and/or a memory) with the supply voltage applied
`to the analog circuits being greater than that applied to the
`digital circuits; a source for applying a first fixed supply
`voltage to digital circuits of a medical device and a voltage
`generation circuit (e.g., a charge pump circuit) having the
`first fixed supply voltage applied thereto for generating a
`second fixed supply voltage to be applied to analog circuits
`of the medical device; adjustment of back gate bias of digital
`circuits of the medical device; level shifting of signals being
`communicated between analog circuits and digital circuits
`having different supply voltages applied thereto; employing
`various ones or combinations of the foregoing features in
`CMOS, CML (Current Mode Logic), SOS (Silicon on
`Sapphire), SOI (Silicon on Insulator), BICMOS, PMOS
`and/or NMOS circuitry.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a graphical illustration showing energy/delay
`versus supply voltage for CMOS circuit operation.
`FIG. 2 shows a prior art CMOS inverter which is used as
`a building block in many CMOS circuit designs.
`FIG. 3 is a block diagram of a just-in-time clocking
`system according to the present invention.
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`FIGS. 4A—4C show timing illustrations for use in describ-
`ing the just-in-time clocking system of FIG. 3.
`FIG. 5 is a block diagram illustration of a multiple supply
`voltage system according to the present invention.
`FIG. 6 is a block diagram illustrating a variable supply
`voltage system according to the present invention.
`FIG. 7 is a block diagram of clock controlled processing
`circuitry according to the present invention.
`FIG. 8 is a diagram illustrating an implantable medical
`device in a body.
`FIG. 9 is a block diagram of the circuitry of a pacemaker
`for use in illustrating one or more embodiments of the
`present invention.
`FIG. 10 is a schematic block diagram of an implantable
`pacemaker/cardioverter/defibrillator (PCD) for illustrating
`one or more embodiments of the present invention.
`FIG. 11 is a schematic block diagram illustrating a vari-
`able clock/variable supply voltage digital signal processing
`system according to the present invention.
`FIG. 12 is a schematic block diagram generally illustrat-
`ing the system of FIG. 11.
`FIG. 13 is a schematic block diagram generally illustrat-
`ing reduction in power consumption using multiple digital
`signal processing systems according to the present inven-
`tion.
`
`FIG. 14 is a schematic block diagram of a portion of
`cardiac pacemaker including sense amplifiers for receiving
`cardiac sense signals.
`FIG. 15 is a two digital signal processing system embodi-
`ment of a system according to FIG. 13 illustrating imple-
`mentation of the sense amplifier functions illustrated in FIG.
`14 according to the present invention.
`FIG. 16 is a general schematic block diagram of a device
`according to the present invention using different supply
`voltages for analog and digital circuits of the device.
`FIG. 17 is a more detailed schematic block diagram of one
`embodiment of a pacemaker much like that shown in FIG.
`9 according to the present invention wherein a lower supply
`voltage is applied to the digital circuits of the pacemaker
`with a charge pump being used to generate a higher supply
`voltage to be applied to the analog circuits of the pacemaker.
`FIG. 18 is a block diagram illustrating the use of digital
`signal processor(s) in the embodiment shown in FIG. 17.
`FIG. 19 shows a block diagram of one embodiment of the
`present invention.
`FIG. 20 shows one embodiment of a rate adaptive algo-
`rithm of the present invention.
`FIG. 21 shows a modified version of the schematic block
`
`diagram of FIG. 11 according to one embodiment of the
`present invention.
`FIG. 22 shows conventional von Neumann microproces-
`sor architecture.
`
`FIG. 23 shows one embodiment of Harvard microproces-
`sor architecture of the present invention.
`FIG. 24 shows one embodiment of a pipeline architecture
`timing diagram of the present invention.
`FIG. 25 shows one embodiment of pipeline architecture
`of the present invention.
`DETAILED DESCRIPTION OF THE
`EMBODIMENTS
`
`One embodiment of the present invention is first generally
`described in reference to FIGS. 3—15. More particularly, at
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`least in part the use of multiple DSP systems to reduce power
`consumption is shown in those Figures.
`FIG. 3 shows a general block diagram of a just-in-time
`clock system 30. Just-in-time clock system 30 includes
`integrated circuit 32 and clock source 34. Integrated circuit
`32 includes a plurality of circuits Cl—Cn. Each circuit when
`operable is capable of performing one or more circuit
`functions. A function is defined herein as any operation
`performed on one or more inputs in a plurality of cycles that
`results in an output. Generally, the functions performed by
`the various circuits Cl—Cn are usually, although not neces-
`sarily always, performed in a predetermined number of
`clock cycles. Clock source 34 is operable for providing
`clock signals at a plurality of clock frequencies generally
`shown as clock1—clockn.
`
`Circuits Cl—Cn of integrated circuit 32 may include
`discrete function circuits (e.g., logic circuits for operating
`upon one or more inputs to implement a particular function
`to provide one or more outputs therefrom), such as circuits
`operating on one input from a sensor to provide a represen-
`tative signal
`to further functional circuitry,
`transceiver
`circuitry, conversion circuitry, etc. Moreover, circuits
`Cl—Cn may comprise data processing circuitry capable of
`performing multiple functions under program control.
`Alternatively, such circuits Cl—Cn may implement firmware
`(software) functions/routines that must complete prior to
`some succeeding event or prior to the start of the next
`function. For example, as described further herein with
`respect to illustrative embodiments of implantable medical
`devices, such circuits may include digital signal processing
`circuits,
`telemetry uplink/downlink circuitry, morphology
`detection circuitry, arrhythmia detection circuitry, monitor-
`ing circuitry, pacing circuitry, microprocessors, and so on.
`The functions performed by each of circuits Cl—Cn are
`typically required to be completed in a particular time period
`prior to a next functional process being undertaken. For
`example, one logic circuit may perform a function in a
`predetermined time period to provide an output required by
`another circuit, or for example, a function may need to be
`performed by processing circuitry during a particular period
`of time due to the need for other processing to be performed
`by such processing circuitry. In another example pertaining
`especially to an implantable medical device, processing to
`complete a particular function may need to be performed in
`a portion of a particular time interval such as a blanking
`interval, an upper rate interval, an escape interval, or refrac-
`tory interval of a cardiac cycle, or further, such as during a
`pulse generator/programmer handshake.
`Clock source 34 may be configured in any manner for
`providing clock signals at a plurality of frequencies. Such a
`clock source may include any number of clock circuits
`wherein each provides a single clock signal at a particular
`frequency, clock source 34 may include one or more adjust-
`able clock circuits for providing clock signals over a con-
`tinuous range of clock frequencies, and/or clock source 34
`may include a clock circuit that is operable to provide clock
`signals at discrete clock frequencies as opposed to over a
`continuous range. For example, the clock source 34 may
`include oscillators, clock dividers,
`timers, clock control
`circuitry or any other circuit elements required for providing
`clock signaling according to the present
`invention.
`Preferably, clock source 34 is configured as a continuously
`oscillating low frequency clock and a controllable on/off
`higher frequency clock.
`Just-in-time controllable clock operation of the just-in-
`time clocking system 30 of FIG. 3 is described herein in
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`time
`reference to FIGS. 4A—4C. As shown in FIG. 4A,
`period (X) represents the time period in which a circuit, e.g.,
`one of circuits C1—Cn, is required to complete one or more
`functions. The same time period (X) is shown in FIG. 4B.
`The time period X may be equated to any number of different
`time periods. For example,
`the time period may be the
`amount of time a processing circuit has to perform a
`particular detection function due to the need for a detection
`output by a certain point in time, may be a time period
`required to complete a particular function by a certain logic
`circuit so as to provide a timely output to a digital signal
`processing circuit, may be a time period to complete a
`firmware (software) routine, etc. Moreover, time period X
`may correspond to a cardiac cycle or a part thereof.
`As shown in FIG. 4B, and according to conventional
`processing, circuit functions were typically performed at a
`burst cycle frequency and, as such, the function performed
`required a time period 60. Therefore, only a small amount of
`time (e.g., time period 60) of the entire time period X was
`used to perform the one or more functions requiring n cycles
`of time to complete. In such a case, conventionally, such
`burst clocks were at a substantially high clock rate, e.g.,
`500—1000 KHZ, for such short periods of time to gain the
`benefit of a “duty cycle” to reduce average current drain.
`However, such high clock rates may not be required for
`carrying out such functions, or all functions.
`With just-in-time clocking according to the present
`invention, as shown in FIG. 4A, substantially the entire time
`period X is used to perform the one or more functions which
`are completed in n cycles.
`In other words,
`the clock
`frequency, e.g., one of clockl—clockn, for the circuit per-
`forming the one or more functions during the time period X
`is set such that the one or more functions are completed in
`the maximum time available for performing such functions,
`i.e., the clock frequency is at its lowest possible value. Stated
`another way, a lower frequency clock is employed such that
`the one or more functions are performed just-in-time for
`other circuit or routine functionality to be performed.
`In such a just-in-time manner, the clock frequency used to
`control the performance of such functions by the particular
`CMOS, CML, SOS, SOI, BICMOS, PMOS and/or NMOS
`circuitry is lowered resulting in reduced power consumption
`by such circuitry. According to calculations of dynamic
`power, the lower frequency results in proportional power
`reduction. With the lowering of the clock frequency,
`the
`integrated circuit 32 including the various circuits C1—Cn
`can be designed to operate at a lower frequency, e.g., as
`opposed to burst frequency, and also at various other fre-
`quencies depending upon need.
`It is preferred that use of substantially the entire prede-
`termined period of time result in completion of the one or
`more functions being performed prior to the end of the time
`period X as is represented by remainder time periods 55 in
`FIG. 4A. This remainder time period 55, for example, is
`preferably near or about 0 seconds.
`FIG. 4C shows an illustrative timing example for pro-
`cessing circuitry which performs multiple functions. For
`example, the cardiac cycle of a patient is represented in FIG.
`4C as time period x. During time period 71, i.e., during a
`QRS complex of the cardiac cycle, high speed processing is
`performed at a high clock frequency relative to a lower clock
`frequency used to control operation of the processing cir-
`cuitry during time period y. During the time period y, when
`the processing circuitry is operated at a lower clock
`frequency, such lower clock frequency may be set such that
`the functions performed during 2 cycles are performed in
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`substantially the entire maximum time period available for
`such processing, i.e., time period y. Once again, a small
`remainder time period 75 of the cardiac cycle time period X
`may exist. Such time period may be, for example, in the
`range of about 1.0 millisecond to about 10.0 milliseconds
`when the cardiac cycle is in the range of about 400 milli-
`seconds to about 1200 milliseconds.
`
`FIG. 5 shows a general block diagram of a multiple
`supply voltage system 100 wherein one or more supply
`voltages are available and tailored for application to various
`circuits in an IC. The multiple supply voltage system 100
`includes integrated circuit 102 and supply voltage source
`106. Integrated circuit 102 includes circuits C1—Cn. Supply
`voltage source 106 is operable for providing a plurality of
`supply voltages Vl—Vn. Each supply voltage from supply
`voltage source 106 is tailored to be applied to one or more
`circuits of circuits C1—Cn. As illustrated, supply voltage V1
`is applied to circuit C1, supply voltage V2 is applied to
`circuit C2 and C3, and so forth.
`The tailoring of the supply voltages Vl—Vn to the par-
`ticular circuits C1—Cn is dependent upon the frequency at
`which the circuits C1—Cn are required to be operated. For
`example, and as previously described, the logic delay of
`such CMOS, CML, SOS, SOI, BICMOS, PMOS and/or
`NMOS circuitry circuits C1—Cn increases drastically as the
`supply voltage is reduced to near 1 volt. If such logic delay
`is tolerable,
`the supply voltage provided to a particular
`circuit will drastically reduce the power consumption for
`that particular circuit as the energy is reduced in proportion
`to the square of the supply voltage (VDD). However, if such
`logic delay is not tolerable, for example, if the logic circuit
`performs a f