Case IPR2020-01492
`U.S. Patent No. 6,651,134
`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________________
`
`
`QUALCOMM INCORPORATED,
`Petitioner
`
`
`v.
`
`
`MONTEREY RESEARCH, LLC,
`Patent Owner
`
`__________________
`
`Case IPR2020-01492
`
`U.S. Patent No. 6,651,134
`
`__________________
`
`
`PATENT OWNER MONTEREY RESEARCH, LLC’S
`DEMONSTRATIVES
`
`
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`
`
`
`U.S. Patent No. 6,651,134
`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________________
`
`
`QUALCOMM INCORPORATED,
`Petitioner
`
`
`v.
`
`
`MONTEREY RESEARCH, LLC,
`Patent Owner
`
`__________________
`
`Case IPR2020-01492
`
`U.S. Patent No. 6,651,134
`
`__________________
`
`
`PATENT OWNER MONTEREY RESEARCH, LLC’S
`DEMONSTRATIVES
`
`
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`
`
`
`
`Monterey’s Demonstrative Exhibits
`
`Qualcomm Incorporated
`
`v.
`
`Monterey Research, LLC
`
`U.S. Patent No. 6,651,134
`
`Case IPR2020‐01492
`
`
`
`2
`
`37
`
`3
`
`Slide
`
`No Weight
`Mr. Murphy’s Declaration Should Be Given Little Or
`Interruptible Bursts
`All Grounds: Schaefer Does NotDisclose Non‐
`
`Topic
`
`A
`
`B
`
`Tab
`
`Table of Contents
`
`
`
`3
`
`POR at 29‐52; Surreply at 2‐19.
`
`All Grounds: Schaefer Does Not
`
`Disclose Non‐Interruptible
`
`Bursts.
`
`Tab A
`
`
`
`4
`
`POR at 14‐21, 29‐52; Surreply at 2‐19.
`
`•Schaefer Is Directed To Reducing Delays In
`
`BetweenBursts.
`
`Internal Address Signals Is Non‐interruptible.”
`Generation Of Said Predetermined Number Of
`
`•Schaefer Does Not Disclose “Wherein Said
`
`Overview of Disputes
`
`
`
`5
`
`Institution Decision (Paper 9) at 5.
`
`Ex. 1001 (’134 Patent) at claim 1.
`
`Schaefer Does Not Disclose “wherein said generation of said predetermined
`
`number of internal address signals is non‐interruptible”
`
`
`
`6
`
`Petition at 40; POR at 37; Surreply at 4‐5.
`Ex‐1017 (Schaefer) at Fig. 4.
`
`Patent Owner
`
`Petitioner
`
`Dispute: When Is Issuing Another Command Prohibited?
`
`
`
`7
`
`POR at 43‐45; Surreply at 4‐7.
`
`2)When the “precharge time (tRP) is completed.”
`1)The “earliest, valid stage within a burst cycle”; and
`Schaefer discloses:
`
`Ex‐1017 (Schaefer) at 7:38‐44.
`
`Defines when precharge is initiated
`
`Schaefer’s Plain Language Is Clear That Issuing Another Command Is Only
`
`Prohibited During The PRECHARGE Time (tRP)
`
`
`
`8
`
`POR at 30‐32.
`
`Ex‐1017 (Schaefer) at 5:15‐19.
`
`New READor WRITEburst command.
`PRECHARGEcommand;
`BURST TERMINATE command;
`
`Schaefer Discloses Multiple Means For Interrupting Bursts Before Completion
`
`
`
`9
`
`POR at 31.
`
`Ex. 2009 (Murphy Dep. Tr.) at 118:14‐22.
`
`auto-precharge.
`
`A.That’s correct, for the bursts that don't include an
`
`correct?
`precharge command or a second burst operation;
`terminate a burst, burst termination command, a
`
`Q.Schaefer discloses at least three ways to
`
`Mr. Murphy Admitted That Schaefer Discloses Interrupting A Burst Command
`
`
`
`10
`
`POR at 32.
`
`Ex. 2009 (Murphy Dep. Tr.) at 118:2‐12.
`
`A.Yes, it does.
`
`Q.Okay. Schaefer discloses ways to stop or
`A.
`
`That’s correct.
`
`terminate that burst; correct?
`
`data until it stops; fair enough?
`reached the 1,024th clock cycle will continue reading
`read data through 1,024 clock cycles and once it’s
`Q.The full page burst disclosed in Schaefer will
`
`Mr. Murphy Admitted That Schaefer Discloses Interrupting A Full‐Page Burst
`
`
`
`11
`
`POR at 32‐34.
`
`Ex. 2009 (Murphy Dep. Tr.) at 120:12‐121:1.
`
`A.Not the words "non-interruptible," no.”
`
`correct?
`explicitly says bursts are non-interruptible;
`You don't cite to anything in Schaefer that
`
`Q.
`
`. . .
`
`It doesn't use that exact phrase, no.
`
`A.
`
`correct?
`Schaefer never uses the phrase "non-interruptible";
`
`Q.
`
`Schaefer Does Not Describe Preventing Interruptions Of Bursts
`
`
`
`12
`
`POR at 18, 38‐40.
`
`Ex‐1017 (Schaefer) at 1:53‐54.
`
`Ex‐1017 (Schaefer) at 9:11‐15.
`
`Ex‐1017 (Schaefer) at 1:49‐52.
`
`Reducing The Time To Complete The PRECHARGE and ACTIVE Commands
`Schaefer Is Directed To Eliminating Wasted Cycles In Between Bursts By
`
`
`
`13
`
`POR at 17, 38.
`
`Ex‐1017 (Schaefer) at Fig. 2.
`
`Reducing The Time To Complete The PRECHARGE and ACTIVE Commands
`Schaefer Is Directed To Eliminating Wasted Cycles In Between Bursts By
`
`
`
`14
`
`POR at 18.
`
`Ex. 2009 (Murphy Dep. Tr.) at 118:14‐22.
`
`can be different.
`Yes, given the fact that the frequencies of operation
`command operations; correct?
`precharge command operations and the active
`wasted clock cycles necessary to perform the
`Schaefer is directed to eliminating the potential
`
`A.
`
`Q.
`
`Mr. Murphy Admitted That Schaefer is Directed To Eliminating Wasted Clock
`
`Cycles When Performing PRECHARGE And ACTIVE Commands
`
`
`
`15
`
`POR at 34‐35.
`
`Ex. 2009 (Murphy Dep. Tr.) at 112:3‐8.
`
`Yes.
`where a precharge is necessary; correct?
`cycles betweenreads and writes in an SDRAM
`Schaefer is directed to eliminating wasted clock
`
`Ex. 2009 (Murphy Dep. Tr.) at 94:25‐95:4.
`
`That’s correct.
`avoid wasting cycles within the device; correct?
`So one reason to allow interruptions of burst is to
`
`A.
`
`Q.
`
`A.
`
`Q.
`
`Mr. Murphy Admits That Interrupting Bursts Is Advantageous And Prevents
`
`Wasting Cycles In Between Bursts
`
`
`
`16
`
`POR at 38‐39.
`
`Ex‐1017 (Schaefer) at 9:54‐60.
`
`Schaefer Is Directed To Reducing The Time To Activate and Precharge A Row
`
`By Initiating ACTIVE and PRECHARGE Command Operations Early
`
`
`
`17
`
`POR at 40‐42.
`
`Ex. 2009 (Murphy Dep. Tr.) at 102:7‐17.
`
`That is correct.
`bit lines in an indeterminate state; correct?
`the precharge operation and leave the voltage on the
`precharge operation to finish, that would interrupt
`given amount of time TRP necessary for the
`If you were to issue an active command before the
`
`Ex. 2009 (Murphy Dep. Tr.) at 110:2‐8.
`
`Yes.
`for the SDRAM to work properly; correct?
`operation where applicable are necessary in order
`precharge operation where applicable and an active
`The given amount of time necessary to perform a
`
`A.
`
`Q.
`
`A.
`
`Q.
`
`Interruptions During The Precharge Command Operation In Between Bursts
`
`Initiating PRECHARGE Command Operations Early Requires Prohibiting
`
`
`
`18
`
`POR at 43‐44.
`
`Ex‐1017 (Schaefer) at 7:43‐48.
`
`Ex‐1017 (Schaefer) at 7:32‐37.
`
`Schaefer’s AUTO‐PRECHARGE Command Operation Necessitates Preventing
`
`Interruptions Of The Precharge Period tRP
`
`
`
`19
`
`POR at 37, 44‐45.
`
`Command
`Subsequent Active
`
`Ex‐1017 (Schaefer) at 7:47‐57, Fig. 4.
`
`Schaefer Must Ensure That A Subsequent Early ACTIVE Command Does Not
`
`Interrupt The Precharge Operation
`
`
`
`20
`
`POR at 37, 43‐45.
`
`Ex‐1017 (Schaefer) at 7:38‐57, Fig. 4.
`
`Command
`Subsequent Active
`
`Schaefer Must Ensure That A Subsequent Early ACTIVE Command Does Not
`
`Interrupt The Precharge Operation
`
`
`
`21
`
`POR at 45‐47.
`
`Ex‐1017 (Schaefer) at Fig. 2.
`
`NOP
`
`Burst Read Operation With Precharge
`
`Schaefer’s NOP Command Does Not Disclose Preventing User Commands
`
`Throughout The Burst Transfer Period
`
`
`
`22
`
`POR at 47.
`
`Ex. 2009 (Murphy Dep. Tr.) at 118:14‐22.
`
`auto-precharge.
`
`A.That’s correct, for the bursts that don't include an
`
`correct?
`precharge command or a second burst operation;
`terminate a burst, burst termination command, a
`
`Q.Schaefer discloses at least three ways to
`
`Mr. Murphy Admitted That A Burst Read With Precharge Is Interruptible
`
`
`
`23
`
`POR at 46‐47.
`
`Ex‐1017 (Schaefer) at Figs. 2, 4.
`
`4 Cycle Burst Read Operation With Auto‐Precharge
`
`4 Cycle Burst Read Operation With Precharge
`
`Ex‐1017 (Schaefer) at 8:8‐10.
`
`Schaefer’s NOP Command Does Not Disclose Preventing User Commands
`
`Throughout The Burst Transfer Period
`
`
`
`24
`
`Surreply at 7.
`
`Reply at 2.
`
`Qualcomm’s Argument That Figure 4 Shows No Commands Interrupting The
`
`Burst Is Beside The Point
`
`
`
`25
`
`Surreply at 7.
`
`Ex‐1017 (Schaefer) at Fig. 4.
`
`Figure 4 Of Schaefer Is Not An Example Of A Burst That Is Interrupted
`
`
`
`26
`
`Reply at 9; Surreply at 7‐12.
`
`Ex‐1015 (Murphy Decl.) at ¶ 83.
`
`Mr. Murphy’s Conclusory And Wavering Statements Should Be Given No
`
`Weight
`
`
`
`27
`
`Surreply at 8.
`
`Ex. 2009 (Murphy Dep. Tr.) at 118:14‐22.
`
`auto-precharge.
`
`A.That’s correct, for the bursts that don't include an
`
`correct?
`precharge command or a second burst operation;
`terminate a burst, burst termination command, a
`
`Q.Schaefer discloses at least three ways to
`
`Schafer Would NotRequire “More Circuitry” To Allow Interrupts Because
`
`Schaefer Already Includes Circuitry For Interrupting Bursts
`
`
`
`28
`
`Surreply at 10.
`
`Reply at 10.
`
`Qualcomm Mischaracterizes The AUTO‐PRECHARGE Advantage
`
`
`
`29
`
`POR at 18; Surreply at 11‐12.
`
`Ex‐1017 (Schaefer) at Fig. 4.
`
`Ex‐1017 (Schaefer) at 9:11‐15.
`
`Wasted Clock Cycles Schaefer Are A Result Of Performing—Not Of The
`
`Starting Time Of—The Precharge Command
`
`
`
`30
`
`Surreply at 12.
`
`Ex. 2009 (Murphy Dep. Tr.) at 94:25‐95:4.
`
`avoid wasting cycles within the device; correct?
`So one reason to allow interruptions of burst is to
`
`Q.
`
`That's correct.
`
`A.
`
`Ex. 2009 (Murphy Dep. Tr.) at 110:19‐111:1.
`
`can be different.
`Yes, given the fact that the frequencies of operation
`command operations; correct?
`precharge command operations and the active
`wasted clock cycles necessary to performthe
`Schaefer is directed to eliminating the potential
`
`A.
`
`Q.
`
`Interrupting Bursts Avoids Wasting Cycles That Is A Result Of PerformingThe
`
`Precharge And Active Commands
`
`
`
`31
`
`Surreply at 13.
`
`Ex. 2009 (Murphy Dep. Tr.) at 118:14‐22.
`
`A.That’s correct, for the bursts that don't include
`
`an auto-precharge.
`
`correct?
`precharge command or a second burst operation;
`terminate a burst, burst termination command, a
`
`Q.Schaefer discloses at least three ways to
`
`Qualcomm’s Attempt To Create Distance Between PRECHARGE And
`
`AUTO‐PRECHARGE Fails
`
`
`
`32
`
`POR at 39‐40; Surreply at 13‐14.
`
`Ex‐1017 (Schaefer) at 7:38‐40.
`
`Ex‐1017 (Schaefer) at 7:29‐32.
`
`Qualcomm’s Attempt To Create Distance Between PRECHARGE And
`
`AUTO‐PRECHARGE Fails
`
`
`
`33
`
`POR at 18; Surreply at 14‐15.
`
`Ex‐1017 (Schaefer) at 9:16‐21.
`
`Schaefer Discloses That Both PRECHARGE And AUTO‐PRECHARGE Commands
`
`May Result In A Wasted Cycle
`
`
`
`34
`
`Surreply at 15.
`
`Ex. 2009 (Murphy Dep. Tr.) at 112:3‐8.
`
`where a precharge is necessary; correct?
`cycles between reads and writes in an SDRAM
`Schaefer is directed to eliminating wasted clock
`
`Q.
`
`A.Yes.
`
`Mr. Murphy Admitted That Schaefer Is Directed To Eliminating Wasted Clock
`
`Cycles
`
`
`
`35
`
`POR at 30; Surreply at 16.
`
`Ex‐1017 (Schaefer) at 5:15‐19.
`
`Ex‐1017 (Schaefer) at 6:1‐2.
`
`Schaefer Defines A “Full Page” Burst As A Fixed‐Burst Of 1024 Cycles.
`
`
`
`36
`
`POR at 32.
`
`Ex. 2009 (Murphy Dep. Tr.) at 118:2‐12.
`
`A.Yes, it does.
`
`Q.Okay. Schaefer discloses ways to stop or
`A.
`
`That’s correct.
`
`terminate that burst; correct?
`
`data until it stops; fair enough?
`reached the 1,024th clock cycle will continue reading
`read data through 1,024 clock cycles and once it’s
`Q.The full page burst disclosed in Schaefer will
`
`Mr. Murphy Admitted That Schaefer Discloses Interrupting A Full‐Page Burst
`
`
`
`37
`
`POR at 23‐29; Surreply at 19‐20.
`
`Mr. Murphy’s Declaration Should
`
`Be Given Little Or No Weight.
`
`Tab B
`
`
`
`38
`
`POR at 23‐29; Surreply at 19‐20.
`
`38
`
`•Mr. Murphy’s Inconsistent Opinions
`
`Overview of Disputes
`
`
`
`39
`
`POR at 23‐25.
`
`Ex‐1015 (Murphy Decl.) at ¶ 48.
`
`Ex‐1015 (Murphy Decl.) at ¶ 85.
`
`Mr. Murphy’s Testimony In This Proceeding Is That A POSITA Does NOT Need
`
`Experience With Static RAM Design
`
`
`
`40
`
`POR at 24‐25.
`
`Ex. 2009 (Murphy Dep. Tr.) at 136:13‐21.
`
`It does not. And so I’ve said in Paragraph 48 and 49.
`with direct SRAM design; right?
`for the ’134 patent does not require experience
`In your opinion, the level of ordinary skill in the art
`
`A.
`
`Q.
`
`Ex. 2009 (Murphy Dep. Tr.) at 135:5‐25.
`
`believe it is.
`that you have SRAM design to do this, no, I don’t
`substituting education for experience. So is it required
`equivalent and also there’s equivalence as far as
`memory circuits, related hardware design could also be
`years of experience in design, development and/or testing
`degree in electrical or computer engineering and two
`just look at Paragraph 48, I talk about someone who had a
`I don’t believe it does. For example, someone --if you
`direct SRAM design?
`art for the ’134 patent require experience with
`In your opinion, does the level of ordinary skill in the
`
`A.
`
`Q.
`
`Mr. Murphy’s Testimony In This Proceeding Is That A POSITA Does NOT Need
`
`Experience With Static RAM Design
`
`
`
`41
`
`POR at 25‐26.
`
`Ex‐2008 (CGI Litigation‐Murphy Decl. ) at ¶ 17.
`
`Ex‐1016 (Murphy CV) at 3.
`
`Mr. Murphy’s Testimony In The CGI Litigation Was That A POSITA Needs
`
`Experience With Direct Static RAM Design
`
`
`
`Case IPR2020-01492
`U.S. Patent No. 6,651,134
`
`
`Dated: December 2, 2021
`
`Respectfully submitted,
`
`/Theodoros Konstantakopoulos/
`Theodoros Konstantakopoulos
`(Reg. No. 74,155)
`tkonstantakopoulos@desmaraisllp.com
`DESMARAIS LLP
`230 Park Avenue
`New York, NY 10169
`Telephone: 212-351-3400
`Facsimile: 212-351-3401
`
`Counsel for Patent Owner
`Monterey Research, LLC.
`
`
`1
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`Case IPR2020-01492
`U.S. Patent No. 6,651,134
`CERTIFICATE OF SERVICE
`
`Pursuant to 37 C.F.R. § 42.6(e), the undersigned certifies that on a complete
`copy of the foregoing was served on counsel of record for the Petitioner by filing
`this document through PTAB E2E and by sending this document via electronic mail
`to the following addresses:
`
`Eagle H. Robinson (Reg. No. 61,361)
` Daniel S. Leventhal (Reg. No. 59,576)
`Norton Rose Fulbright US LLP
`Norton Rose Fulbright US LLP
` Fulbright Tower
`98 San Jacinto Boulevard, Suite 1100
`Austin, Texas 78701
`1301 McKinney, Suite 5100
`Telephone: 512-536-3083
`Houston, TX 77010-3095
`Facsimile: 512-536-4598
`Telephone: 713-651-5151
`eagle.robinson@nortonrosefulbright.
`Facsimile: 713-651-5246
`com
`daniel.leventhal@nortonrosefulbright.com
`
`Richard S. Zembek (Reg. No. 43,306)
`Norton Rose Fulbright US LLP
`Fulbright Tower
`1301 McKinney, Suite 5100
`Houston, TX 77010-3095
`Telephone: 713-651-5151
`Facsimile: 713-651-5246
`richard.zembek@nortonrosefulbright.com
`
`Dated: December 2, 2021
`
`Respectfully submitted,
`
`/Theodoros Konstantakopoulos/
`Theodoros Konstantakopoulos
`(Reg. No. 74,155)
`
`Counsel for Patent Owner
`Monterey Research, LLC
`
`2
`
`
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