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` UNITED STATES PATENT AND TRADEMARK OFFICE
`
` BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
` _______________________________________________
`
` QUALCOMM INCORPORATED,
`
` Petitioner,
`
` vs.
`
` MONTEREY RESEARCH, LLC,,
`
` Patent Owner.
`
` _________________________________________________
`
` INTER PARTES REVIEW No. IPR2020-01492
`
` PATENT 6,651,134
`
` _________________________________________________
`
` THE DEPOSITION OF DR. MICHAEL BROGIOLI
`
` August 17, 2021
`
`Reported by:
`
`PATRICIA A. NILSEN, RMR, CRR, CRC
`
`Tennessee LCR 717
`
`25
`
`California CSR 13069
`
`Texas CSR 11813
`
`Veritext Legal Solutions
`346-293-7000
`
`Page 1
`
`Qualcomm Incorporated v. Monterey Research, LLC
`IPR2020-01492
`Qualcomm EX1029
`Page 1 of 73
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` UNITED STATES PATENT AND TRADEMARK OFFICE
`
` BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
` _______________________________________________
`
` QUALCOMM INCORPORATED,
`
` Petitioner,
`
` vs.
`
` MONTEREY RESEARCH, LLC,,
`
` Patent Owner.
`
` _________________________________________________
`
` INTER PARTES REVIEW No. IPR2020-01492
`
` PATENT 6,651,134
`
` _________________________________________________
`
` THE DEPOSITION OF DR. MICHAEL BROGIOLI
`
` August 17, 2021
`
`Reported by:
`
`PATRICIA A. NILSEN, RMR, CRR, CRC
`
`Tennessee LCR 717
`
`25
`
`California CSR 13069
`
`Texas CSR 11813
`
`Veritext Legal Solutions
`346-293-7000
`
`Page 1
`
`Qualcomm Incorporated v. Monterey Research, LLC
`IPR2020-01492
`Qualcomm EX1029
`Page 1 of 73
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` UNITED STATES PATENT AND TRADEMARK OFFICE
`
` BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
` _______________________________________________
`
` QUALCOMM INCORPORATED,
`
` Petitioner,
`
` vs.
`
` MONTEREY RESEARCH, LLC,,
`
` Patent Owner.
`
` _________________________________________________
`
` INTER PARTES REVIEW No. IPR2020-01492
`
` PATENT 6,651,134
`
` _________________________________________________
`
` THE DEPOSITION OF DR. MICHAEL BROGIOLI
`
` August 17, 2021
`
`Reported by:
`
`PATRICIA A. NILSEN, RMR, CRR, CRC
`
`Tennessee LCR 717
`
`25
`
`California CSR 13069
`
`Texas CSR 11813
`
`Veritext Legal Solutions
`346-293-7000
`
`Page 1
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`Page 1 of 73
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`
`
` APPEARANCES (via Zoom)
`
` For the Petitioner:
`
` DANIEL LEVENTHAL
` BRETT MCKEAN
` Attorneys at Law
` NORTON ROSE FULBRIGHT US LLP
` 1301 McKinney, Suite 5100
` Houston, TX 77010-3095
` 713-651-8360
` daniel.leventhal@nortonrosefulbright.com
` brett.mckean@nortonrosefulbright.com
`
` For the Patent Owner:
`
` THEODOROS KONSTANTAKOPOULOS
` Attorney at Law
` DESMARAIS LLP
` 230 Park Avenue
` New York, NY 10169
` 212-808-2969
` tkonstantakopoulos@desmaraisllp.com
`
` Stenographically Reported By:
`
` PATRICIA A. NILSEN, RMR, CRR, CRC
` Tennessee LCR 717
` California CSR 13069
` Texas CSR 11813
`
` Videotaped By: JASON ELY
`
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`
`
` INDEX
`
` WITNESS: PAGE
`
` DR. MICHAEL BROGIOLI
`
`Examination
`
` By Mr. Leventhal 5
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` VIDEOGRAPHER: Good morning.
`
` We are going on the record at 11:00 a.m. on
`
` August 17, 2021.
`
` This is media unit number one of the
`
` video-recorded deposition of Dr. Michael Brogioli,
`
` taken by counsel for the petitioner in the matter
`
` of Qualcomm Incorporated vs. Monterey Research,
`
` LLC, case number IPR-2020-01492.
`
` This deposition is being held
`
` remotely via Zoom. My name is Jason Ely, and I'm
`
` the videographer. The court reporter is Patricia
`
` Nilsen.
`
` Will counsel please identify
`
` themselves for the record.
`
` MR. KONSTANTAKOPOULOS: Theodoros
`
` Konstantakopoulos, from Desmarais LLP, on behalf of
`
` Monterey Research.
`
` MR. LEVENTHAL: Daniel Leventhal,
`
` Norton Rose Fulbright, US, LLP, on behalf of
`
` Qualcomm. And with me is my colleague, Brett
`
` McKean.
`
` VIDEOGRAPHER: Swear in the witness.
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` DR. MICHAEL BROGIOLI,
`
` having been first duly sworn, was examined
`
` and testified as follows:
`
` EXAMINATION
`
` BY MR. LEVENTHAL:
`
` Q. Good morning, Dr. Brogioli.
`
` A. Good morning.
`
` Q. I know you've been deposed before. I
`
` apologize; I will need to ask you a series of
`
` questions I always ask at the beginning of remote
`
` depositions.
`
` So is there any other person in the room
`
` or any electronic contact with you?
`
` A. No. No one's in the building.
`
` Q. And will you agree to let me know if
`
` anyone else enters the room while we're on record
`
` here today?
`
` A. Yes.
`
` Q. Okay. And will you agree to let me know
`
` if anyone tries to contact you by -- via any other
`
` means while we're on the record, such as calls,
`
` texts, Skype, e-mail?
`
` A. Sure. Yes.
`
` Q. Do you have access to Veritext's exhibit
`
` share website?
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` A. Yes. I do.
`
` Q. Okay. So on exhibit share, you're going
`
` to find a folder under your name that has two
`
` exclamation points and then says "Marked Exhibits."
`
` Do you see that?
`
` A. Yes, I do.
`
` Q. So there's four exhibits that have been
`
` marked, and they're all previously existing
`
` exhibits in the record. Exhibit 1001 is the '134
`
` patent. Exhibit 1017 is the Schaefer reference.
`
` Exhibit 2006 is your declaration. And Exhibit 2007
`
` is your CV.
`
` Can you see all four of those?
`
` A. I can.
`
` Q. And we'll go through each one as we get
`
` there.
`
` So do you have any documents -- let me
`
` start with paper documents -- in the room with you,
`
` right now with you?
`
` A. No.
`
` Q. Okay. Do you have any -- anything open on
`
` your computer other than Zoom and exhibit share?
`
` A. I shouldn't, but let me double-check for
`
` you.
`
` No, I don't.
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` Q. Okay. And will you agree to please let me
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` know if -- if you do -- you know, if something else
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` does -- does pop up?
`
` A. Will do.
`
` Q. Okay. Okay. So let me -- with that
`
` background, let me just ask you just a couple of
`
` background questions.
`
` What did you do to prepare for today's
`
` deposition?
`
` A. Sure. So, reviewed my declaration.
`
` Reviewed the patent, Schaefer, and then met with
`
` counsel. I think we maybe briefly spoke late last
`
` week and then met yesterday, which would have been
`
` Monday. And a little bit this morning.
`
` Q. And for approximately how long did you
`
` meet on Monday?
`
` A. Maybe half a day. Four hours or so.
`
` Q. Approximately how long did you meet this
`
` morning?
`
` A. About an hour.
`
` Q. And again, this one is a yes-or-no
`
` question: Did you review any documents during that
`
` meeting?
`
` A. Yes.
`
` Q. Okay. Had you seen all of them before?
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` A. Yes.
`
` Q. Okay. Did any of those documents refresh
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` your recollection?
`
` A. I would say generally. You know, I hadn't
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` read the -- parts of the declaration, maybe, in,
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` you know, the month or so, two months since
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` submitting it.
`
` Q. So your declaration refreshed your
`
` recollection; to your recollection as you sit here
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` today, none of the other ones that you looked at
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` did?
`
` A. Oh, I would say generally the documents I
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` reviewed, that was the goal, to refresh myself on
`
` the subject matter. So the patent, the prior art,
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` the declaration.
`
` Q. Okay. Anything other than those: the
`
` patent, the prior art, the declaration?
`
` A. That's largely what I remember reviewing.
`
` Q. Okay. And you mentioned counsel. Who is
`
` the counsel that you met with?
`
` A. Theodoros, who's present today.
`
` Q. Anyone else?
`
` A. No, I don't think so.
`
` Q. Okay. If you could, could you please --
`
` and I just orient you to the Veritext system.
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` You're able to either click on individual documents
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` or you can download them as PDFs. I'd recommend
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` downloading them as PDFs, because I may jump back
`
` and forth between your declaration and the patent.
`
` That way, you can have them both up.
`
` A. Do you want me to pull -- sorry.
`
` Q. So why don't you go ahead and pull all
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` four. And I'm going to start with Exhibit 2006,
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` your declaration.
`
` A. Okay.
`
` Q. Okay. In Exhibit 2006, if you could,
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` could you please turn to page -- there's a Bates
`
` number at the bottom that has some pagination, and
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` then you have separate pagination. I'm going to do
`
` the pagination and the Bates number. So if you
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` could turn to page 21, which has paragraph 48 at
`
` the top.
`
` A. Okay.
`
` Q. Okay. So I'm going to go through in kind
`
` of detail each of the experience items on your CV,
`
` but I just have a big-picture question that may
`
` help orient me.
`
` You graduated undergrad in 2000 -- excuse
`
` me, in 1999. And you state in paragraph 48 that
`
` you had education and two -- sufficient experience
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` by February 14, 2000.
`
` Do you see that?
`
` A. Yes.
`
` Q. So my question is, if you look further
`
` in -- up in paragraph 48, it talks about having at
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` least two years of experience.
`
` Can you please describe to me, are you
`
` saying that you had two years of experience after
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` school, which wasn't -- do you see what I'm saying?
`
` There's not two years from when you graduated
`
` undergrad to February 2000. So if you could kind
`
` of explain what you were thinking there, expand
`
` upon that.
`
` A. Sure. I -- I think I understand the
`
` question.
`
` So there's a little bit of overlap here in
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` my -- I guess my experience timeline. So I think I
`
` officially finished undergrad January of '99. I
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` had started working in '97 at a big fault tolerant
`
` computing company. I think I spent at least a year
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` there, overlapping with undergrad, and then was
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` also, I believe, while I was a senior in undergrad,
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` took a position as a -- on the teaching staff for
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` some digital electronics mixed-signal stuff, just
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` as another thing to do before grad school. That
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` probably would have been '98. And then finished in
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` '99 and spent time at a company that was doing
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` development for Nintendo. It ultimately was
`
` acquired by another company.
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` A lot of what I was doing was -- well, one
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` was publishing a title that was -- you could buy in
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` the store. The other work was building hardware
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` interfaces for PCs to connect to embedded systems
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` that -- basically your hand-held -- you know,
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` what -- what today is like a Nintendo Switch.
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` And then doing a lot of optimization work
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` on the memory side, so you could take these little
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` eight-bit double-A battery-powered computers and do
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` full-motion video and digital speech reproduction,
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` stuff like that.
`
` And then had -- I guess officially started
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` grad school in Houston, August of '99, and then I
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` guess up to this February 14 time frame was
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` working -- and beyond, but preliminarily working in
`
` a lot of large -- what we were calling at the time
`
` larger data set problems and optimizing from memory
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` systems. So everything from a CPU register file to
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` L1, L2 cache DRAM, things like that; blocking,
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` laying out the data, and -- and how to do big
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` problems on small -- smaller computers, I guess.
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` Q. All right. Let me start with the company
`
` that you said you were doing the -- the Nintendo
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` video game stuff. You mentioned optimization on
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` the memory side. Can you describe what you meant
`
` by that.
`
` A. Yeah. So maybe two different angles
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` there. One, I was building tools where you were
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` developing graphics and things on a desktop PC as
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` a -- let's just call it a developer. And then you
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` had this little kind of low-powered -- I'm probably
`
` even being generous, but a little 8-bit computer
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` with some SRAM and a little bit of DRAM and -- and
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` not a heck of a lot more.
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` And so built a way to connect through -- I
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` think it was the parallel port, and interface from
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` the memory on your desktop to put bits and bytes
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` and graphics in real time into the memory, and the
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` SRAM scratch pad stuff, and the rest of it. So you
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` could kind of mirror parts of your desktop PC on
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` this little LCD gaming console. And then -- so I
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` had to build, you know, custom breadboard hardware,
`
` and all of that good stuff.
`
` And then the other part was actually
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` building one into games and sort of these modular
`
` libraries other developers could use; where instead
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` of, you know, your little pixel graphics that we
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` probably all grew up with as kids, you could do
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` like PlayStation 1 quality, 30 frames per second --
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` I think it was 256 color, maybe more than that --
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` demos and segues. And you could also get the thing
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` to reproduce human digital speech, even though it
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` didn't have codecs for that in it, or voice
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` synthesizers, or things like that.
`
` Q. So you mentioned -- I want to go through
`
` the -- the SRAM and the DRAM you mentioned on the
`
` 8-bit computer.
`
` Let me start with the SRAM. Was that an
`
` external module?
`
` A. I'm not sure I would necessarily apply
`
` those words to it. The -- I mean, the console
`
` itself had its own SRAM. And then as I recall,
`
` there was building a sort of intermediate SRAM as
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` part of the hardware interface between the -- you
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` know, the computer to the -- to the console, as
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` part of moving things back and forth.
`
` Q. So -- okay. And same question for the
`
` DRAM: Was the DRAM an external module?
`
` A. I would say the DRAM, to my recollection,
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` it was internal to the console hardware that came
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` from -- probably from Nintendo of America.
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` Q. And how -- how would you write to that
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` DRAM?
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` A. There were a number of different ways. I
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` mean, one way was sort of -- so internal to the
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` device, you could do program CPU read/write
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` operations. You could use special direct memory
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` access hardware to remove the CPU from that
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` equation as much as possible.
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` And then there was probably proprietary
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` stuff external to the console that the PC and the
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` custom hardware was doing to kind of inject data
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` into the memory so you could ultimately view it,
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` you know, on the portable versus what you were
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` developing on your desktop.
`
` Q. Did your work in -- did your work for --
`
` in -- at that time involving DRAM, did it involve
`
` issuing commands to the -- to the DRAM module, in
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` terms of -- and let me -- strike that.
`
` Did it involve issuing an active command
`
` to the memory module?
`
` MR. KONSTANTAKOPOULOS: Objection.
`
` A. I would say that was probably part of it.
`
` I don't recall necessarily building a custom
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` solution to do that. I think that would have been
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` part of the -- the built-in hardware.
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` Q. So you would write a higher-level --
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` higher-level software in the CPU that then the
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` built-in hardware would convert to specific
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` commands issued to the memory?
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` A. I built custom software and custom
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` hardware that interfaced, you know, via hardware
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` ports to the console. I don't recall sort of
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` redesigning the commands at the hardware level that
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` the DRAM would have been getting.
`
` Q. Okay. And then you mentioned for your
`
` grad school program, same thing, optimizing from
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` memory systems.
`
` Can you expand upon what you -- what
`
` memory systems were -- were being used at that
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` time?
`
` A. So it would have been -- I'll go maybe --
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` maybe bottom up, lower parts of the hierarchy.
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` DRAM, probably Layer 2 cache, Layer 1 cache, maybe
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` Layer 3, depending on the platform.
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` And then some of the work having what we
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` called scratch-pad buffers, but you can think of
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` like a very small amount of SRAM. It's explicitly
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` managed. And then the register file. So -- sorry,
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` the internal registers within a CPU that's doing
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` computation.
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` Q. Okay. And as to the DRAM, same question:
`
` Do you have any recollection as to whether that was
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` an external module, the DRAM?
`
` A. I would say that for the various platforms
`
` that I was looking at at the time -- so things like
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` power PC variants, MIPS -- probably SGI; I don't
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` remember all that well -- the memory would have
`
` been -- for the DRAM would have been sort of I
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` guess -- I'm guessing off-the-shelf DRAM that was
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` in a given system that was set up in the lab.
`
` And then optimizing things like how long a
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` strip of memory should be, or what -- you know,
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` given the burst mode, what -- how things should be
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` blocked and chunked, or if there's DMA, direct
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` memory access, and if things are strided, how
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` should you set them up, and then kind of
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` recursively partition these big matrices into this
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` hierarchy of chunks so that you could try to move
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` them through the memory system as fast as possible.
`
` Q. Did any of your work involve, I guess,
`
` programming a memory controller to issue commands
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` to the DRAM?
`
` A. I don't recall in that work -- later in my
`
` career, but in that particular work, I don't
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` recall.
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` Q. Okay. I am going to switch to your CV,
`
` but while you're on that thought, can you tell me
`
` about the "later in your career" that you're
`
` talking about, where you did work --
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` A. Give me a -- yeah. So -- so fast-forward
`
` to my master's work, a lot of it was dynamic memory
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` systems. So you can think of having a cache
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` hierarchy, and having intelligent hardware that
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` says we can disable 25 percent or 55 percent --
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` 50 percent of this memory and still run the
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` application within certain tolerance parameters,
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` and building a custom framework to do the math to
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` figure that out, and then custom silicon models to
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` run the program, and then also kind of control
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` the -- I think this was largely SRAM-based cache,
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` to turn it into different power states at really
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` high frequency.
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` And then -- so that's roughly '02, '03.
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` And then '03, '04 was building network interfaces.
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` And as I recall -- sorry, network interface cards.
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` So think multiprocessor SRAM, DRAM, trying to move
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` packets in and out of the system as quickly as
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` possible. I think we were looking at Gigabit
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` Ethernet at the time. And we built our own
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` hardware and simulation tools, and I believe part
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` of that was memory controllers, as part of the
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` modeling.
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` And then just generally, later in my
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` career, working on various memory optimization
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` things or putting books out on it or white papers
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` as it kind of came up more in the embedded system
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` side of -- side of things that I got more and more
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` into.
`
` Q. Okay. Are you familiar with JEDEC,
`
` J-E-D-E-C?
`
` A. Yes.
`
` Q. Which JEDEC standards are you familiar
`
` with, off the top of your head?
`
` A. It's a memory test.
`
` Q. Yes.
`
` A. I've worked with a number of them, both
`
` from -- so sort of in like something like this, or
`
` a litigation, or how the standards works, as well
`
` as more generally into some optimization stuff;
`
` like I think JEDEC 3, JEDEC 4, and some of the
`
` memory controllers signaling some of the -- the
`
` remote buffer distribution and things like that.
`
` Probably a number of other ways, but I -- I
`
` probably don't recall.
`
` Q. Okay. I understand. That was -- that was
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` certainly a memory test.
`
` Can you turn, please, to -- to Schaefer,
`
` which is Exhibit 1017, please. What I'd like you
`
` to do is turn to Figure 1.
`
` A. Okay.
`
` Q. So Figure 1 shows some internal circuitry
`
` to a memory device. Is that fair?
`
` A. That looks correct.
`
` Q. Yeah, and I'll just represent to you that
`
` the Schaefer says Figure 1 is a block diagram of
`
` a SDRAM, according to the present invention.
`
` So I want to direct your attention to the
`
` left-hand side. And you see a number of open
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` circles with letters next to them. Do you see
`
` that?
`
` A. Yes.
`
` Q. And what -- what are those? What are
`
` those -- what looks like pins?
`
` A. Let's see how Schaefer describes --
`
` describes these.
`
` I think I'm going column three. Schaefer
`
` starts to introduce the A0 to A10 as -- effectively
`
` input pins. These are address inputs, or some set
`
` of address inputs. Here we see eleven of them.
`
` Q. Okay. And so -- that's good enough.
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` We'll go back to those pins in detail, but what I
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` wanted to -- wanted to get to is, what is your
`
` understanding as to what these pins would connect
`
` to?
`
` A. Well, based on the figure here, we can see
`
` that there is interconnects. So you see part of --
`
` I guess going from the top down, A10 has a
`
` connection that they sort of fork off to the -- the
`
` command controller block.
`
` Q. Yeah. I asked a bad question. I
`
` apologize. I asked a bad question.
`
` I actually meant, what does it connect to
`
` in the -- not shown in this figure, off to the
`
` left? My understanding is that these pins would
`
` connect to a bus, which would in turn connect to a
`
` memory controller. Is that fair?
`
` A. I would say that generally you would see
`
` these address in other -- perhaps other signals
`
` coming from something like a memory controller over
`
` some kind of interconnect here, showing the pins in
`
` parallel. So some high-speed interconnect.
`
` Q. Okay. Have you personally, in your
`
` career, worked on designing any of -- any internal
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` hardware to a memory device such as shown in
`
` Figure 1?
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` A. Parts of it, yes.
`
` Q. Which parts?
`
` A. So things like the memory bank or memory
`
` bank arrays. Things like the various buffers.
`
` I've certainly built various kinds of decoders or
`
` command decoder functionality, although probably
`
` directed to different types of silicon. But things
`
` like that.
`
` Q. Have you ever worked at designing the
`
` internal circuitry for a device intended to comply
`
` with a JEDEC standard?
`
` A. I don't recall. There may be parts of
`
` some of the network interface design work that were
`
` intended to be JEDEC-compliant, but I don't
`
` remember.
`
` Q. Have you ever worked on designing a memory
`
` controller to issue command signals to a
`
` JEDEC-compliant device?
`
` A. I -- that specifically, I don't believe
`
` so.
`
` Q. Have you ever worked on a memory
`
` controller to issue command signals to other types
`
` of memory devices?
`
` A. Specifically memory controller command
`
` issue, I don't think so, no.
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` Q. While we're still looking at this, I
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` have -- while we're still looking at Figure 1, I'm
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` going to -- I'm going to read to you -- and please,
`
` obviously, feel free to jump and put both on your
`
` screen, but I want to read -- let me get to the
`
` right page. I want to read a paragraph of your
`
` expert declaration, and again, just make sure we're
`
` on same page in terms of what we're labeling stuff.
`
` So I'm going to read from paragraph 122 of
`
` your declaration, which is page 66.
`
` And paragraph 122 of your declaration
`
` refers to external commands. And I just want to
`
` make sure we're on the same page on what is meant
`
` by an external command.
`
` A. Can you -- one second. You're actually --
`
` MR. KONSTANTAKOPOULOS: Hold on.
`
` A. Paragraph 122, you said?
`
` Q. Correct. And my question is just going to
`
` be about the second-to-last line, but please go
`
` ahead and read the whole thing.
`
` A. Okay.
`
` Q. Okay. So turning back to Figure --
`
` Figure 1, would external commands refer to signals
`
` sent to Command Controller 28, as shown in -- and
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` over the pins that are shown to the left of Command
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` Controller 28?
`
` A. So what I'm referring to in 122 --
`
` paragraph 122 are what we see in Figure 2 on the
`
` Command illustration, third line down. So things
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` like Active, Read, etc. And those are part of what
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` is coming in on the -- for instance, write enable,
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` column address strobe, etc., on the left of 28, and
`
` a part of what the command controller itself is
`
` doing.
`
` Q. Okay. So basically Command Controller 26
`
` in Figure 1 is taking the four input pins -- let me
`
` read this slowly for the record: CS*, WE*, CAS*,
`
` and RAS*, and interpreting those four pins to be
`
` making a particular external command?
`
` A. I would say that's at least part of it. I
`
` don't recall from memory all of the lines that are
`
` used to ultimately result in the commands we see
`
` in, for example, Figure 2. But those, as I recall,
`
` are part of it. You know, we also see things like
`
` the clock, and clock enable, on Block 28.
`
` Q. Understood. And let me actually -- on
`
` that note, do you see that the A10 pin also goes
`
` into the command controller, in addition to being
`
` an address pin?
`
` A. That looks correct, yes.
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` Q. And we can look at the -- the Figure 2
`
` that you have in your declaration, where we're
`
` looking. A10 is used to -- as part of -- as part
`
` of the control input, to determine whether in this
`
` case the read command is a read with auto
`
` precharge, or a read without auto precharge,
`
` correct?
`
` A. Get back to Schaefer.
`
` So I don't -- at least just going through
`
` the specification of Schaefer -- see that A10, the
`
` pin A10 you're asking about is discussed in all
`
` that much detail, unless I'm -- I'm missing
`
` something you want to point me to.
`
` Q. Let me see if I can -- I'm sorry, go
`
` ahead. Please continue.
`
` A. I'll stop there. We can -- we can discuss
`
` that first.
`
` Q. So if you look at Column 4, starting at
`
` line 53 -- why don't you -- actually, why don't you
`
` go ahead and read the whole paragraph to yourself,
`
` Column 4, starting at line 44, and then I'll ask
`
` the question.
`
` A. Okay.
`
` Okay. This one I think is maybe a little
`
` in Column 6, too, but go ahead with your question.
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` Q. So I just want to make sure that what
`
` we're looking at is -- is that A10 is used in
`
` combination with the command pins that we talked
`
` about to determine whether a command is a read
`
` without auto precharge or a read with auto
`
` precharge.
`
` A. So in this language, I guess starting
`
` around 53, it's talking about a read command. And
`
` it's -- as we see in the horizontal timing diagram,
`
` like Figure 2, it says "A10 provides an input path
`
` for a command signal," and that's -- I'm sorry,
`
` "which determines whether or not an auto-precharge
`
` command, described below, is to be initiated
`
` automatically after the read command."
`
` So it's a -- a signal we see coming in on
`
` that left-hand side in those timing diagrams.
`
` Q. Okay. And let me actually -- let's go
`
` back, because I want to make sure I forget, go
`
` to -- specifically back to paragraph 122.
`
` A. Okay.
`
` Q. So you have a -- a list of external
`
` commands. The first is "Active." So it's your
`
` opinion that "Active" is an external command as
`
` disclosed by Schaefer, correct?
`
` A. So, yes, I'm saying in 122, "a NOP command
`
`Veritext Legal Solutions
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