Case IPR2020-01492
`U.S. Patent No. 6,651,134
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`________________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`________________________________________________
`
`
`
`QUALCOMM INCORPORATED,
`Petitioner
`
`v.
`
`MONTEREY RESEARCH, LLC,
`Patent Owner
`__________________
`
`Case IPR2020-01492
`
`U.S. Patent No. 6,651,134
`__________________
`
`
`
`PATENT OWNER PRELIMINARY RESPONSE
`
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`

`

`I. 
`II. 
`
`V. 
`
`2. 
`
`3. 
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`Case IPR2020-01492
`U.S. Patent No. 6,651,134
`
`TABLE OF CONTENTS
`
`Page
`Introduction ...................................................................................................... 1 
`Background ...................................................................................................... 2 
`A.  Overview Of The ’134 Patent. .............................................................. 2 
`III.  Claim Construction ........................................................................................ 13 
`A.  All Challenged Claims: “non-interruptible”. ...................................... 14 
`B. 
`Claim 16: “means for reading data . . . / means for generating a
`predetermined number of said internal address signals in
`response to (i) an external address signal, (ii) a clock signal and
`(iii) one or more control signals”. ....................................................... 15 
`IV.  Summary Of Prior Art References ................................................................ 17 
`A. 
`Schaefer ............................................................................................... 18 
`1. 
`Schaefer Is Directed To Commands For Automatically
`Activating And Precharging Memory Banks In A
`SDRAM. ................................................................................... 18 
`Schaefer Describes Manually Precharging Bank Memory
`Arrays In A SDRAM After A Data Transfer Using A
`“PRECHARGE” Command...................................................... 20 
`Schaefer Alternatively Describes Automatically
`Precharging Memory Banks After A Burst Data Transfer
`Using An “AUTO-PRECHARGE” Command. ....................... 22 
`The Board Should Exercise Its Discretion To Deny Institution Of
`Qualcomm’s “Follow-On” Petition. .............................................................. 24 
`A. 
`The General Plastic Factors Favor Denial Of Institution. .................. 27 
`1. 
`
`Factor 1: whether the same petitioner previously filed a
`petition directed to the same claims of the same patent. .......... 27 
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`Case IPR2020-01492
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`U.S. Patent No. 6,651,134
`2. 
`Factor 2: whether at the time of filing of the first petition
`the petitioner knew of the prior art asserted in the second
`petition or should have known of it. .......................................... 29 
`
`Page
`
`3. 
`
`4. 
`
`Factor 3: whether at the time of filing of the second
`petition the petitioner already received the patent
`owner’s preliminary response to the first petition or
`received the Board’s decision on whether to institute
`review in the first petition. ........................................................ 29 
`
`Factors 4 and 5: the length of time that elapsed between
`the time the petitioner learned of the prior art asserted in
`the second petition and the filing of the second petition;
`and whether the petitioner provides adequate
`explanation for the time elapsed between the filings of
`multiple petitions directed to the same claims of the same
`patent. ........................................................................................ 31 
`
`5. 
`
`2. 
`
`Factors 6 and 7: the finite resources of the Board; and
`the requirement under 35 U.S.C. § 316(a)(11) to issue a
`final determination not later than 1 year after the date on
`which the Director notices institution of review. ...................... 32 
`VI.  Qualcomm Did Not Establish A Reasonable Likelihood Of Prevailing
`Against Any Claim In Ground 1A. ................................................................ 33 
`A. 
`The Board Should Deny Institution Of Qualcomm’s Ground 1A
`Because Qualcomm Concedes That Schaefer Does Not
`Anticipate Any Claim Of the ’134 Patent. .......................................... 33 
`Schaefer Does Not Disclose “wherein said generation of said
`predetermined number of internal address signals is non-
`interruptible”. ...................................................................................... 35 
`1. 
`Schaefer Does Not Disclose Prohibiting User Commands
`For An Entire Burst Operation. ................................................. 38 
`Schaefer Is Directed Towards Eliminating Wasted Cycles
`In Between Burst Transfer Operations, Not Preventing
`Interruptions Of Individual Bursts. ........................................... 42 
`
`B. 
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`Case IPR2020-01492
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`U.S. Patent No. 6,651,134
`3. 
`Schaefer Discloses Multiple Means of Terminating Burst
`Operations Including An “AUTO-PRECHARGE”
`Command. ................................................................................. 44 
`VII.  Qualcomm Did Not Establish A Reasonable Likelihood Of Prevailing
`Against Any Claim In Ground 1B. ................................................................ 45 
`A.  Qualcomm’s Proposed Combination Of Schaefer And Fujioka
`Does Not Meet Every Limitation Of Any Challenged Claim. ............ 45 
`VIII.  Qualcomm Did Not Establish A Reasonable Likelihood Of Prevailing
`Against Any Claim In Ground 2A. ................................................................ 45 
`A.  Qualcomm’s Proposed Combination Of Schaefer And Lysinger
`Does Not Meet Every Limitation Of Any Challenged Claim. ............ 45 
`IX.  Qualcomm Did Not Establish A Reasonable Likelihood Of Prevailing
`Against Any Claim In Ground 2B. ................................................................ 46 
`A.  Qualcomm’s Proposed Combination Of Schaefer, Lysinger, and
`Fujioka Does Not Meet Every Limitation Of Any Challenged
`Claim. .................................................................................................. 46 
`Conclusion ..................................................................................................... 46 
`
`X. 
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`Case IPR2020-01492
`U.S. Patent No. 6,651,134
`TABLE OF AUTHORITIES
`
`Page(s)
`
`Cases 
`Abbott Labs. v. Sandoz, Inc.,
`566 F.3d 1282 (Fed. Cir. 2009) ..................................................................... 33
`Ericsson Inc. v. Uniloc 2017, LLC,
`Case IPR2019-01550, Paper 8 (PTAB Mar. 17, 2020) .................... 26, 28, 31
`General Plastic Co., Ltd. v. Canon Kabushiki Kaisha,
`Case IPR2016-01357, Paper 19 (PTAB Sept. 6, 2017) (precedential) . passim
`Pers. Web Techs., LLC v. Apple, Inc.,
`848 F.3d 987 (Fed. Cir. 2017) ....................................................................... 17
`Scripps Clinic & Research Found. v. Genentech, Inc.,
`927 F.2d 1565 (Fed. Cir. 1991) ........................................................ 33, 34, 41
`Valve Corp. v. Elec. Scripting Prods., Inc.,
`Case IPR2019-00062, -00063, -00084, Paper 11 (PTAB Apr. 2, 2019)
`(precedential) ......................................................................................... passim
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc.,
`200 F.3d 795, 803 (Fed. Cir. 1999) ............................................................... 13
`Statutes 
`35 U.S.C. § 102(b) ................................................................................................... 33
`35 U.S.C. § 314(a) ........................................................................................ 1, 24, 33
`Regulations 
`37 C.F.R. § 42.104(b)(4) .......................................................................................... 17
`83 Fed. Reg. 39,989 (Aug. 13, 2018) ...................................................................... 32
`Other Authorities 
`Patent Trial and Appeal Board Consolidated Trial Practice Guide (Nov.
`2019) ....................................................................................................... 32, 33
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`Case IPR2020-01492
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`U.S. Patent No. 6,651,134
`All emphases are added unless otherwise indicated.
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`Page(s)
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`This paper includes color illustrations and should be viewed in color.
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`Case IPR2020-01492
`U.S. Patent No. 6,651,134
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`PATENT OWNER’S EXHIBIT LIST
`
`Exhibit No.
`2001
`
`2002
`
`2003
`
`DESCRIPTION
`Monterey’s First Amended Complaint in Monterey Research, LLC v.
`Advanced Micro Devices, Inc., C.A. No. 19-cv-2149-CFC, Dkt. 16
`(D. Del. Feb. 5, 2020)
`Scheduling Order in Monterey Research, LLC v. Qualcomm Inc. et
`al, C.A. No. 19-2083-NIQA-LAS (D. Del. Oct. 1, 2020); Monterey
`Research, LLC v. Nanya Tech. Corp. et al, C.A. No. 19-2090-NIQA-
`LAS (D. Del. Oct. 1, 2020); Monterey Research, LLC v. Advanced
`Micro Devices, Inc., C.A. No. 19-cv-2149-NIQA-LAS (D. Del. Oct.
`1, 2020); Monterey Research, LLC v. STMicroelectronics N.V. et al,
`C.A. No. 20-0089-NIQA-LAS (D. Del. Oct. 1, 2020); Monterey
`Research, LLC v. Marvell Tech. Grp. Ltd., et al, C.A. No. 20-0158-
`NIQA-LAS (D. Del. Oct. 1, 2020).
`Qualcomm’s Answer, Counterclaims and Defenses to the First
`Amended Complaint in Monterey Research, LLC v. Qualcomm Inc.
`et al, C.A. No. 19-2083-NIQA-LAS, Dkt. 22 (D. Del. Feb. 28, 2020)
`
`All citations to specific pages of exhibits follow the pagination added to those
`exhibits per 37 C.F.R. § 42.63(d)(2)(i).
`
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`Case IPR2020-01492
`U.S. Patent No. 6,651,134
`I.
`Introduction
`
`The Board should deny Qualcomm Incorporated’s (“Qualcomm” or
`
`“Petitioner”) petition against Claims 1-7 and 9-21 (collectively, “the Challenged
`
`Claims”) of U.S. Patent No. 6,651,134 (Ex-1001, the “’134 Patent”). The ’134
`
`Patent claims novel and non-obvious designs and procedures for improving the
`
`efficiency and speed of memory devices conducting “burst” operations to access
`
`multiple memory locations using a single address. The validity of the ’134 Patent
`
`has been repeatedly upheld—first by the United States Patent and Trademark Office
`
`(“PTO”) in issuing the ’134 Patent in 2000, and again by the International Trade
`
`Commission (“ITC”) in the course of an Investigation. Qualcomm’s Petition does
`
`not establish a reasonable likelihood that the Challenged Claims are anticipated or
`
`obvious and that they should be cancelled.
`
`First, the Board should exercise its discretion to deny institution under 35
`
`U.S.C. § 314(a). Qualcomm’s “follow-on” Petition was filed months after
`
`Advanced Micro Devices, Inc. (“AMD”), a defendant in a parallel district court
`
`litigation, filed a first inter partes review petition—IPR2020-00985—against claims
`
`1-21 of the ’134 Patent based in part on both Fujioka and Lysinger. The Board
`
`recently instituted trial on IPR2020-00985. IPR2020-00985, Paper 14 (PTAB Dec.
`
`2, 2020). Since Qualcomm’s Petition challenges the same claims of the ’134 Patent
`
`using the same art, granting its institution would place a substantial and unnecessary
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`U.S. Patent No. 6,651,134
`burden on the Board by ensnaring the Board’s resources in multiple, cumulative
`
`proceedings against the same patent, and would also prejudice Monterey.
`
`Second, Qualcomm’s Petition raises four grounds based primarily on one
`
`allegedly anticipatory reference: Schaefer (Ex-1017). But, among other things,
`
`Schaefer does not disclose (and Qualcomm has not shown that it does disclose) the
`
`“wherein said generation of said predetermined number of internal address signals
`
`is non-interruptible.” Qualcomm concedes that the burst operations that allegedly
`
`meet that limitation are in fact interruptible, and, at most, the alleged non-
`
`interruptible aspect of that operation last only a portion of that operation. None of
`
`Qualcomm’s alleged obviousness references—Fujioka (Ex-1006) and Lysinger (Ex-
`
`1009)—teach that limitation either.
`
`Accordingly, Patent Owner Monterey Research, LLC (“Monterey”)
`
`respectfully requests that the Board deny institution.
`
`II. Background
`
`A. Overview Of The ’134 Patent.
`
`The ’134 patent teaches a novel design and operation for memory devices,
`
`such as a Static Random Access Memory (SRAM) or a Dynamic Random Access
`
`Memory (DRAM), operating in burst mode. In burst mode, a memory device can
`
`provide data from multiple locations in the device using a single external address,
`
`thereby increasing efficiency and reducing activity on address and control buses
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`U.S. Patent No. 6,651,134
`connected to the device. (Ex-1001, 1:11-13.) Before the invention of the ’134
`
`Patent, burst mode in both conventional SRAMs and DRAMs had drawbacks,
`
`particularly a susceptibility to interruptions. In a conventional SRAM, burst mode
`
`could be “started and stopped in response to a control signal.” (Ex-1001, 1:15-18.)
`
`And using burst mode in a conventional DRAM was “difficult because of the need
`
`to refresh” data within the memory cell, which might necessitate interrupting the
`
`burst application and thus greatly lengthen the amount of time required for accessing
`
`data. (Ex-1001, 1:20-36.) Because burst mode data transfers in both conventional
`
`SRAMs and DRAMs could be interrupted, the availability of data, address, and
`
`control busses varied, which “complicate[d] the design of systems with shared data,
`
`address, and control busses.” (Ex-1001, 1:38-43.) As such, the ’134 Patent explains
`
`that it “would be desirable to have a memory device that has a fixed burst length.”
`
`(Ex-1001, 1:44-45.)
`
`To that end, the inventions of the ’134 Patent propose an integrated circuit
`
`comprising a memory and a logic circuit which fixes the length of the burst and
`
`renders it non-interruptible. (Ex-1001, Abstract, 1:44-45.) The inventions of the
`
`’134 Patent present a number of benefits and advantages, including to:
`
`(i) give network customers who typically burst large data lengths the
`
`ability to set a fixed burst length that suits particular needs; (ii) have
`
`non-interruptible bursts; (iii) free up the address bus and control bus for
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`U.S. Patent No. 6,651,134
`a number of cycles; (iv) provide programmability for setting the burst
`
`length by using DC levels [Vss or Vcc] on external pins; (v) hide
`
`required DRAM refreshes inside a known fixed burst length of data
`
`words; and/or (vi) operate at higher frequencies without needed
`
`interrupts to perform refreshes of data.
`
`(Ex-1001, 1:58-67.) Fixing the burst length permits the ’134 Patent’s novel circuit
`
`to “allow shared usage of data, address and control busses,” by “generally free[ing]
`
`up the address bus and control bus for a known number of cycles,” e.g., during the
`
`burst mode, and therefore “may provide a more reliable and/or accurate burst than
`
`is possible with multiple chips.” (Ex-1001, 3:54-61.)
`
`Among other things, the ’134 Patent provides a novel circuit integrating a
`
`memory device with a logic circuit, thereby providing a fixed burst length and
`
`ensuring non-interruptible generation of a predetermined number of internal
`
`addresses. Independent Claim 1 is illustrative:
`
`A circuit comprising:
`
`a memory comprising a plurality of storage elements each configured
`
`to read and write data in response to an internal address signal; and
`
`a logic circuit configured to generate a predetermined number of said
`
`internal address signals in response to (i) an external address signal,
`
`(ii) a clock signal and (iii) one or more control signals, wherein said
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`U.S. Patent No. 6,651,134
`generation of said predetermined number of internal address signals is
`
`non-interruptible.
`
`(Ex-1001, Claim 1.)
`
`The ’134 Patent illustrates aspects of the claims using four exemplary figures.
`
`For example, Figure 1, reproduced below, presents a circuit 100 comprising “a
`
`[logic] circuit 102 and a memory array” 104:
`
`Ex-1001, Figure 1 (annotated1)
`
`
`
`Circuit 102 includes inputs for receiving signals, including, for example, an
`
`external address signal (“ADDR_EXT” 106); an address load control signal
`
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`1 All annotations in drawings are added.
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`U.S. Patent No. 6,651,134
`(“LOAD” 108); a clock signal (“CLK” 110); a control signal (“ADV” 112); or a
`
`configuration signal (“BURST” 114), as shown in Fig. 1, reproduced below.
`
`(Ex-1001, Figure 1.)
`
`
`
`The external address signal ADDR_EXT may be “n-bits wide,” (Ex-1001,
`
`2:56-58), and presents an “initial address,” which “may determine the initial
`
`location where data transfers to and from the memory 104 will generally begin.”
`
`(Ex-1001, 3:1-4.) Circuit 100 loads the initial address presented by the external
`
`address signal ADDR_EXT in response to the address load control signal LOAD.
`
`(Ex-1001, 2:66-3:2.)
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`Circuit 100 “may be configured to transfer a fixed number of words to or
`
`from the memory 104 in response to signals ADV, CLK, and R/Wb.” (Ex-1001,
`
`3:6-8.) For example, the ’134 Patent states:
`
`When the signal ADV is asserted, the circuit 100 will generally begin
`
`transferring a predetermined number of words. The transfer is
`
`generally non-interruptible. In one example, the signal ADV may
`
`initiate the generation of a number of addresses for presentation as the
`
`signal ADDR_INT. (Ex-1001, 3:6-13.)
`
`
`
`Alternatively, the ’134 Patent notes that “signals ADV and LOAD may be, in
`
`one example, a single signal (e.g., ADV/LDb).” (Ex-1001, 3:14-15.) In that
`
`embodiment, when the signal ADV/LDb is in a first state, the “circuit 102 will
`
`generally load an address presented by the signal ADDR_EXT as an initial address.”
`
`(Ex-1001, 3:17-19.) Conversely, when the signal ADV/LDb is in a second state:
`
`[T]he circuit 102 may be configured to generate the signal ADDR_INT
`
`as a fixed number of addresses in response to the signal CLK. The
`
`signal ADDR_INT may be, in one example, an internal address signal.
`
`The signal ADDR_INT may be n-bits wide. Once the circuit 102 has
`
`started generating the fixed number of addresses, the circuit 102 will
`
`generally not stop until the fixed number of addresses has been
`
`generated (e.g., a non-interruptible burst). (Ex-1001, 3:20-28.)
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`The ’134 Patent states that the fixed number of addresses generated by the
`
`circuit 102 in response to the signals CLK and ADV/LDb may be programmed by,
`
`for example, the configuration signal BURST. (Ex-1001, 3:30-34.) The signal
`
`BURST may be generated, for example, by “(i) using bond options, (ii) voltage
`
`levels applied to external pins, or (iii) other appropriate signal generation means.”
`
`(Ex-1001, 3:34-36.) Figure 1, reproduced below, shows the generation of the signal
`
`ADDR_INT as a fixed number of addresses as programmed by the signal BURST.
`
`(Ex-1001, Figure 1.)
`
`
`
`In one embodiment, after receiving the initial starting address from
`
`ADDR_EXT, circuit 102 is configured to increment subsequent addresses a specific
`
`number of times—thereby generating a predetermined number of internal
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`U.S. Patent No. 6,651,134
`addresses—as programmed by the signal BURST. For example, Figure 2,
`
`reproduced below, presents a detailed block diagram of the circuit 102 embodied as
`
`an address counter register 126 and a burst counter 128.
`
`(Ex-1001, Figure 2.)
`
`
`
`In one embodiment of the ’134 Patent, the address counter register 126
`
`receives the signals ADDR_EXT, LOAD, and CLK, while the burst counter 128
`
`receives the signals ADV and BURST. (Ex-1001, 3:65 – 4:2.) The burst counter
`
`128 presents a signal BURST_CLK—which contains “a number of pulses that has
`
`been programmed by the signal BURST”—to the address counter 126 when the
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`signal ADV is asserted. (Ex-1001, 4:10-14.) The address counter register 126 loads
`
`an initial address—identifying the starting point for accessing the memory array—
`
`by receiving the external address signal ADDR_EXT and asserting the signal
`
`LOAD. (Ex-1001, 4:6-8.) The address counter register 126 then “increment[s] an
`
`address in response to the signal BURST_CLK,” for a number of times that equals
`
`the number of pulses in the signal BURST_CLK as programmed by the signal
`
`BURST. (Ex-1001, 4:8-10.) As such, the predetermined number of internal
`
`addresses is generated by incrementing the initial address based on the number of
`
`pulses from the signal BURST_CLK.
`
`In this way, this embodiment of the ’134 Patent generates a predetermined
`
`number of internal address signals. For example, when the signal ADV is asserted,
`
`the circuit 100 will “generate a number of address signals, for example, N, where N
`
`is an integer” which address signals “will generally continue to be generated until
`
`the Nth address signal is generated.” (Ex-1001, 4:42-48.)
`
`For example, Figure 5a, reproduced below, illustrates an operation for a four-
`
`word fixed burst memory. The circuit first loads an initial address (portions 150,
`
`154, and 158), and starting with that initial address, transfers a fixed number of
`
`words—4 words in Figure 5a—as shown in line DQ. (Ex-1001, 4:54-59.) During
`
`the transfer of the fixed number of words, the address and control buses, including
`
`ADDR, CEB, and R/WB, are “generally available to other devices” for a known
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`number of cycles, shown in in portions 152, 156, and 160 of Figure 5a. (Ex-1001,
`
`4:60-64.)
`
`(Ex-1001, Figure 5A.)
`
`
`
`The non-interruptible generation of internal address signals presents a
`
`significant advancement over the prior art. Specifically, fixing the burst length in
`
`advance and generating a predetermined number of internal address signals
`
`“generally frees up the address bus and control bus for a known number of cycles.”
`
`(Ex-1001, 3:56-58.) For memory devices that share the address and control buses,
`
`the invention of the ’134 Patent provides “a more reliable and/or accurate burst than
`
`is possible with multiple chips.” (Ex-1001, 3:58-61.) The’134 Patent, therefore,
`
`presents an advantage over prior art solutions that merely read or write a preset
`
`number of data words or presented options for continuously reading or writing data
`
`from the memory device.
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`For example, the United States Patent and Trademark Office (“PTO”) allowed
`
`the ’134 Patent over prior art such as US Patent No. 6,289,138 to Yip et al, (“Yip”),
`
`that prevent interrupting of read or write bursts until a preset number of data words
`
`has been transferred, which “is not the same as generating a predetermined number
`
`of internal address signals that is non-interruptible.” (Ex-1004, ¶ 0065.)
`
`Similarly, the ’134 Patent was allowed, and provides advantages, over prior
`
`art that merely presented methods for continuously bursting data in and/or out of the
`
`memory. For example, the PTO allowed the ’134 Patent over U.S. Patent No.
`
`5,729,504 to Cowles (“Cowles”), which was “directed to a continuous burst EDO
`
`memory device (Ex-1020, Title),” and specifically directed to “an ability to access a
`
`second row of memory while bursting data out of a first row (a so-called “continuous
`
`BEDO,” or “CBEDO” architecture . . .).” (Ex-1004, ¶¶ 0107-0108). But as the
`
`applicant argued, the “ability to access a second row of memory while bursting data
`
`out of a first row has little or nothing to do with whether a “burst” can be
`
`interrupted.” (Ex-1004, ¶¶ 0107-0108). Moreover, the examiner agreed that
`
`Cowles’ continuous burst architecture did not disclose the claim limitation “wherein
`
`said generation of said predetermined number of internal address signals is non-
`
`interruptible” in the Notice of Allowance:
`
`“[T]he prior art discloses an integrated circuit memory device which
`
`can operate at high data speeds. The integrated circuit memory can
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`U.S. Patent No. 6,651,134
`output data of a “fixed burst length” in a continuous stream while rows
`
`of the memory are accessed. However, to terminate a continuous burst
`
`read operation, the WE signal merely has to transition high prior to a
`
`falling edge of the CAS signal (see, for example, Cowles). [T]hus prior
`
`art of record does not teach or fairly suggest the non-interruptible
`
`generation of a predetermined number of internal address signals.”
`
`(Ex-1004, ¶ 0172 (emphasis in original).)
`
`III. Claim Construction
`
`The Board need only construe terms “that are in controversy, and only to the
`
`extent necessary to resolve the controversy.” Vivid Techs., Inc. v. Am. Sci. & Eng’g,
`
`Inc., 200 F.3d 795, 803 (Fed. Cir. 1999). Certain terms of the ʼ134 Patent, including
`
`“non-interruptible,” were previously construed or agreed upon by the parties in two
`
`separate actions: (1) Cypress Semiconductor Corp. v. GSI Tech., Inc., No. 3-13-cv-
`
`03757, ECF No. 57 (N.D. Cal. July 29, 2014) (“Cypress District Court litigation”);
`
`and (2) Investigation No. 337-TA-792 (“792 Investigation”), initiated by Cypress
`
`Semiconductor Corp., the previous assignee of the ’134 Patent. The prior
`
`constructions include:
`
`Term
`
`“burst”
`
`Construction
`
`“a number of words transferred as a group” (Ex-
`
`1011, 0016)
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`Case IPR2020-01492
`U.S. Patent No. 6,651,134
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`“internal address signal”
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`“external address signal”
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`“an address signal that is generated within the
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`circuit claimed by the preamble” (Ex-1011, 0018)
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`“an address signal that originates outside of the
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`circuit” (Ex-1011, 0015)
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`“a circuit that is designed to perform one or more
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`“logic circuit”
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`logic operations or to represent logic functions”
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`(Ex-1011, 0020)
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`“memory”
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`“addressable storage” (Ex-1012, 0004-0005)
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`“a signal for determining the address location in the
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`“address signal”
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`memory array from which data is read to or to
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`which data is written” (Ex-1012, 0005)
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`Nevertheless, the Board need consider only one term in independent Claims
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`1, 16, and 17 to deny institution: “non-interruptible.”
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`A. All Challenged Claims: “non-interruptible”.
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`In the 792 Investigation, the parties agreed that “non-interruptible” means
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`“cannot be stopped or terminated once initiated until the fixed number of internal
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`addresses has been generated.” (Ex-1011, 0012-0013.) Qualcomm adopts this
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`construction. (Petition, 21.) However, Qualcomm’s prior art does not disclose the
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`“non-interruptible” limitation under its proposed construction, as discussed below.
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`For purposes of this proceeding, Monterey adopts this construction as well.
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`Case IPR2020-01492
`U.S. Patent No. 6,651,134
`B. Claim 16: “means for reading data . . . / means for generating a
`predetermined number of said internal address signals in response
`to (i) an external address signal, (ii) a clock signal and (iii) one or
`more control signals”.
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`Claim 16 of the ’134 Patent includes two means-plus-function limitations:
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`“means for reading data from and writing data to a plurality of storage elements in
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`response to a plurality of internal address signals”; and “means for generating a
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`predetermined number of said internal address signals in response to (i) an external
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`address signal, (ii) a clock signal and (iii) one or more control signals.” (Ex-1001,
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`Claim 16.)
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`The function for the “means for reading data from and writing data to a
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`plurality of storage elements in response to a plurality of internal address signals”
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`limitation is “reading data from and writing data to a plurality of storage elements in
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`response to a plurality of internal address signals.” Monterey agrees with Qualcomm
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`that the corresponding structure is the memory array 104. (Petition, 25; Ex-1001,
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`Fig. 1, 2:34-38, 2:44-49.) This limitation is not in controversy.
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`The function for the “means for generating a predetermined number of said
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`internal address signals in response to (i) an external address signal, (ii) a clock
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`signal and (iii) one or more control signals” is “generating a predetermined number
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`of said internal address signals in response to (i) an external address signal, (ii) a
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`clock signal and (iii) one or more control signals.” Qualcomm alleges that the
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`corresponding structure is the “’burst address counter/register 102,’ including as
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`Case IPR2020-01492
`U.S. Patent No. 6,651,134
`implemented in Figure 2.” (Petition, 26.) Monterey agrees with Qualcomm that the
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`corresponding structure is the circuit 102, or its equivalents including, for example,
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`the circuit 102 as depicted in Figure 3. For example, Figure 2 discloses a circuit 102
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`comprising an address counter register 126 and burst counter 128. Similarly, Figure
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`3 discloses a circuit 102 comprising a counter 138 and latch 134. Both Figures are
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`reproduced below.
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`
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`
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`(Ex-1001, Figure 2.)
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`(Ex-1001, Figure 3.)
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`According to the ’134 Patent, the circuit 102 depicted in Fig. 2 “may comprise
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`an address counter register 126 and a burst counter 128.” (Ex-1001, 3:63-65.) The
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`address counter register 126 “generally receives the signals ADDR_EXT, LOAD,
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`and CLK” (Ex-1001, 3:65-66); “may be configured to present the signal
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`ADDR_INT” (Ex-1001, 3:67-4:1); and “may be configured to increment an address
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`in response to the signal BURST_CLK.” (Ex-1001, 4:9-10.) The burst counter 128
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`may present a signal BURST_CLK which “generally contains a number of pulses
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`U.S. Patent No. 6,651,134
`that has been programmed by the signal BURST.” (Ex-1001, 4:13-14.) Similarly,
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`the circuit 102 depicted in Fig. 3 “may comprise a latch 134, a multiplexer 136, and
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`a counter 138.” (Ex-1001, 4:16-18.) The counter 138 receives the “signals ADV,
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`CLK and BURST,” (Ex-1001, 4:28-29), and “may be configured to generate a
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`number of addresses in response to the signals CLK, BURST and ADV.” (Ex-1001,
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`4:30-31.) According to the ’134 Patent, the “number of addresses generated by the
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`counter 138 may be programmed by the signal BURST.” (Ex-1001, 4:31-33.) This
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`limitation is not in controversy.
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`IV. Summary Of Prior Art References
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`Qualcomm raises four grounds, all of which rely primarily upon Schaefer:
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`Ground
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`Reference(s)
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`Challenged Claims
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`1A
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`1B
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`2A
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`2B
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`Schaefer
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`1-5, 7, 9-10, 12-18, 20, 21
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`Schaefer + Fujioka
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`1-7, 9-10, 12-21
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`Schaefer + Lysinger
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`11
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`Schaefer + Lysinger + Fujioka 11
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`Qualcomm must demonstrate that every limitation of the challenged claims is
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`in the prior art, and that a person of ordinary skill in the art would have combined
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`Schaefer with Fujioka and Lysinger. Pers. Web Techs., LLC v. Apple, Inc., 848 F.3d
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`987, 991 (Fed. Cir. 2017); 37 C.F.R. § 42.104(b)(4).
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`Case IPR2020-01492
`U.S. Patent No. 6,651,134
`Qualcomm does not satisfy its burdens. Schaefer does not anticipate the
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`“wherein said generation of said predetermined number of internal address signals
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`is non-interruptible” limitation recited in independent Claims 1 and 17, from which
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`all other challenged claims depend. And none of Qualcomm’s references alone or
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`in combination disclose the “wherein said generation of said predetermined number
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`of internal address signals is non-interruptible” limitation. For at least these reasons,
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`Qualcomm has not established a reasonable likelihood of success on any of its
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`grounds.
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`A.
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`Schaefer
`1.
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`Schaefer Is Directed To Commands For Automatically
`Activating And Precharging Memory Banks In A SDRAM.
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`Unlike the ’134 Patent, which describes and claims novel methods and
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`structures for ensuring a burst is non-interruptible, Schaefer is directed to
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`automatically activating and precharging memory banks in a SDRAM. (See, e.g.,
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`Ex-1017, Title: “Auto-Activate on Synchronous Dynamic Random Access
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`Memory.”) Schaefer notes that in an SDRAM, a transfer operation requires three
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`separate steps: (1) “performing a PRECHARGE command operation to deactivate
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`and precharge a previously accessed bank memory array;” (2) “performing an
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`ACTIVE command operation to register the row address and activate the bank
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`memory array to be accessed in the transfer operation;” and (3) “performing the
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`transfer READ or WRITE command to register the column address and initiate a
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`Case IPR2020-01492
`U.S. Patent No. 6,651,134
`burst cycle.” (Ex-1017, 1:42-49.) However, S