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`..
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`IEEE Press
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`

`

`CMOS
`Circuit Design, Layout, and Simulation
`
`R. Jacob Baker, Harry W. Li and David E. Boyce
`Department ofElectrical Engineering
`Microelectronics Research Center
`The University of Idaho
`
`IEEE Press Series on Microelectronic Systems
`Stuart K. Tewksbury, Series Editor
`
`IEEE Circuits & Systems Society, Sponsor
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`

`

`:1
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`(\
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`i L
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`I -
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`This book and other books may be purchased at a discount
`from the publisher when ordered in bulk quantities. Contact:
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`© 1998 by the Institute of Electrical and Electronics Engineers, Inc.
`345 East 47th Street, New York, NY 10017-2394
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`All rights reserved. No part ofthis book may be reproduced in any form,
`nor may it be stored in a retrieval system or transmitted in any form,
`without written permission from the publisher.
`
`Printed in the United States of America
`10
`9
`8
`7
`6
`5
`4
`3
`
`ISBN 0·7803·3416·7
`IEEE Order Number: PC5689
`
`Library of Congress Cataloging-in-Publication Data
`
`Baker, R. Jacob (date)
`CMOS circuit design, layout, and simulation I R. Jacob Baker,
`Harry W. Li, and David E. Boyce.
`p.
`em. -- (IEEE Press series on microelectronic systems)
`Includes bibliographical references and index.
`ISBN 0-7803-3416-7
`I. Metal oxide semiconductors, Complementary-Design and
`construction.
`2. Integrated circuits--Design and construction.
`3. Metal oxide semiconductor field-effect transistors.
`I. Li,
`Harry W.
`II. Boyce, David E.
`III. Title.
`IV. Series
`TK7871.99.M44B35
`1997
`621.3815--DC21
`
`97-21906
`CIP
`
`Page 4 of 7
`
`

`

`xii
`
`Contents
`
`Chapter 15 VLSI Layout
`15.1 Chip Layout
`,
`15.2 Layout Steps
`Chapter 16 BiCMOS Logic Gates
`16.1 Layout of the Junction-Isolated BIT
`16.2 Modeling the NPN
`16.3 The BiCMOS Inverter
`16.4 Other BiCMOS Logic Gates
`16.5 CMOS and ECL Conversions Using BiCMOS
`Chapter 17 Memory Circuits
`17.1 RAM Memory Cells
`17.1.1 The DRAM Cell
`17.1.2 The SRAM cell
`17.2 The Sense Amplifier
`17.3 Row/Column Decoders
`17.4 Timing Requirements for DRAMs
`17.5 Modern DRAM Circuits
`17.5.1 DRAM Memory Cell Layout
`17.5.2 Folded/Open Architectures
`17.6 Other Memory Cells
`Chapter 18 Special-Purpose Digital Circuits
`18.1 The Schmitt Trigger
`18.1.1 Design of the Schmitt Trigger
`18.1.2 Switching Characteristics
`18.1.3 Applications of the Schmitt Trigger
`18.1.4 High-Speed Schmitt Trigger
`18.2 Multivibrator Circuits
`18.2.1 The Monostable Multivibrator
`18.2.2 The Astable Multivibrator
`18.3 Voltage Generators
`18.3.1 Improving the Efficiency
`18.3.2 Generating Higher Voltages
`18.3.3 Example
`
`289
`290
`301
`313
`314
`316
`320
`323
`326
`331
`332
`333
`337
`338
`341
`343
`345
`345
`347
`350
`355
`355
`356
`359
`359
`361
`362
`362
`363
`364
`366
`367
`368
`
`Page 5 of 7
`
`

`

`Chapter
`
`17
`
`Memory Circuits
`
`In this chapter we look into the design of semiconductor memory circuits [1, 2], in
`particular static random access memory (SRAM) and dynamic random access memory
`(DRAM). These types of memories are termed random access because any bit of data
`can be accessed at any time. A block diagram of a RAM is shown in Fig. 17.1.
`
`Row/word
`Latches,
`decoder,
`buffer
`
`'MemOrycell
`intersection of
`row and column
`lines
`
`Exte
`inpu
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`•
`Control
`•
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`I - -
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`-
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`Column\bit\digit lines
`Sense amplifiers, decoder
`Output buffers
`
`Figure 17.1 Block diagram of random access memory.
`
`Page 6 of 7
`
`

`

`332
`
`Part II CMOS Digital Circuits
`
`External to the memory array are the row and column logic. The row lines are
`sometimes called word lines, while the column lines are sometimes called bit or digit
`lines. Referring to the row lines, the row address is latched, decoded, and then buffered.
`A particular row line will, when selected, go high. This selects the entire row of the
`array. Since the row line may be long and loaded periodically with the capacitive
`memory cells, a buffer is needed to drive the line. The address is latched with signals
`from the control logic. After a particular row line is selected, the column address is
`used to decode which of the bits from the row are the addressed information. At this
`point, data can be read into or out of the array through the column decoder. The
`majority of this chapter will concentrate on the circuits used to implement a RAM.
`
`17.1 RAM Memory Cells
`
`The memory array is at the center of the RAM design. Examples of DRAM and SRAM
`memory cells are shown in Fig. 17.2. The DRAM memory cell is made up of a pass
`transistor and a storage capacitor, while the CMOS SRAM memory cell
`is a
`cross-coupled connection of inverters. The cross-coupled inverters form a positive
`feedback circuit, forcing the outputs in opposite directions. The basic operation of the
`DRAM memory cell was discussed in Ch. 14.
`
`For the SRAM cell shown in Fig. 17.2, consider the case when the row line
`(word line) is low. Both pass transistors are off, and the datum in the cell is latched, as
`long as power is applied to the cell. When the row line goes high, the pass transistors
`turn on. If the pass transistors, width/length ratio is approximately four times that of
`the SRAM cell transistors' width/length ratio, the data on the bit lines (column lines)
`are written to the cell. If the widths are comparable in size, the effective resistance of
`the pass transistor is too large to allow overwriting the cell.
`
`VDD
`
`Row line
`(word line)
`
`Word line
`
`DRAM
`
`Column line
`(bit line)
`
`Bit
`
`SRAM
`
`Bit
`
`Figure 17.2 Schematic diagrams of RAM memory cells.
`
`Page 7 of 7
`
`