`1. My name is Robert Murphy. I am over the age of twenty-one (21)
`
`years, of sound mind, and capable of making the statements set forth in this
`
`Declaration. I am competent to testify about the matters set forth herein. All the
`
`facts and statements contained herein are within my personal knowledge and they
`
`are, in all things, true and correct.
`
`2.
`
`I have been asked by Qualcomm Incorporated (“Qualcomm”) to
`
`submit this declaration in support of its challenge to the validity of certain claims
`
`of U.S. Patent No. 6,651,134 (“the ’134 Patent”).
`
`I.
`
`EDUCATION AND EXPERIENCE
` I have over forty-five years of experience in the semiconductor
`3.
`
`industry, and have experience in the design of high speed, high complexity
`
`semiconductor products, including Full Custom Microprocessors, E2CMOS and
`
`BiCMOS PALs, CMOS and NMOS SRAMs (Static Random Access Memory),
`
`CCDs, DRAMs (Conventional and Pseudo-Static), and RAD Hard SOS CMOS.
`
`4.
`
`I earned a Bachelor of Science Degree in Electrical Engineering in
`
`1974 from Drexel University, in Philadelphia, Pennsylvania. I earned a Master of
`
`Science Degree in Electrical Engineering in 1976 from the University of
`
`California, Los Angeles.
`
`Qualcomm Incorporated
`EX1015
`Page 1 of 94
`
`
`
`5.
`
`From June 1974 to February 1978, I worked for Hughes Aircraft Co.
`
`in El Segundo, California. This began as a part-time position, where I worked as a
`
`Test Engineer testing space flight sub-assemblies, and later became an integrated
`
`circuit designer, all while obtaining my Master’s Degree. While at Hughes Aircraft
`
`Co., in addition to other circuit designs, I designed charged coupled device (CCD)
`
`based memories that included the control circuitry, addressing scheme and related
`
`circuitry, as well as data input and data output paths. The CCD based memories
`
`used a CCD device as a memory cell to store data in a different manner than is
`
`done with a DRAM memory. In memories that use either a CCD memory cell or a
`
`single transistor based memory cell, such as is used in a DRAM memory, the
`
`memories must be addressed to either read or write data into the memory, must
`
`have the other usual control circuitry, and must have read data paths and write data
`
`paths to get the data into or out from the memory. As a result, the control circuitry,
`
`addressing scheme and related circuitry, and data input and data output paths for
`
`the CCD based memories are very similar to the control circuitry, addressing
`
`scheme and circuitry, data input and data output paths used in other semiconductor
`
`memories.
`
`6.
`
`From February 1978 to April 1982, I was a design manager with
`
`National Semiconductor Corp. in Santa Clara, California and West Jordan, Utah.
`
`My work during this time involved designing pseudo-static dynamic random
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`Page 2 of 94
`
`
`
`access memory (DRAM) that included sense amplifiers for the device. The
`
`pseudo-static DRAM used CCD devices for the memory cells, but used the same
`
`manufacturing processes and circuitry as typical DRAM.
`
`7.
`
`About a year after my hire at National Semiconductor Corp., I
`
`transferred over to the static random access memory (SRAM) group where I
`
`learned about various SRAM operations including addressing, data outputting and
`
`controlling of the SRAM. As part of the work, I designed a four transistor (4T) cell
`
`4K SRAM product. After the 4T cell 4K SRAM product was built, I was promoted
`
`to SRAM design manager. As the SRAM design manager, I was responsible for all
`
`SRAM designs. As part of my role as SRAM design manager, I resolved a SRAM
`
`yield crash in 62 days. I was responsible for the SRAM designs in production in
`
`the amount of 30,000 4 inch wafers per month.
`
`8.
`
`From April 1982 to October 1983, I worked with RCA in
`
`Sommerville, New Jersey. There, I led an inter-divisional program to develop 2
`
`micron CMOS technology, and also helped design a 64K SRAM (Static Random
`
`Access Memory).
`
`9.
`
`From October 1985 through February 1989, I was again employed by
`
`National Semiconductor Corporation in Santa Clara, California. There, I achieved
`
`the position of design manager and chief technical contributor for their E2CMOS
`
`Page 3 of 94
`
`
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`PAL group. Significant design projects included the world’s first BiCMOS PAL,
`
`and improved Ti-W fuse blowing circuitry.
`
`10. From February 1989 to June 1992, I worked with Weitek Corporation
`
`in Sunnyvale, California, achieving the position of Director of Engineering in
`
`1990. While at Weitek, I was charged with, among other things, the responsibility
`
`for designing circuitry to implement high performance memory, output drivers,
`
`and electrostatic discharge (ESD) devices. Examples include a 40 MHz SPARC
`
`combined IU/FPU product and a floating point coprocessor compatible with the
`
`Intel i486.
`
`11. From June 1992 through April 1998, I was Director of Engineering at
`
`Silicon Graphics, Inc. (“SGI”) in Mountain View, California. There, I was
`
`involved in the hiring, management, and direction of circuit engineers in processor
`
`and floating point chip designs. I also assisted in the design of phase locked loops
`
`(“PLL”).
`
`12.
`
`In 1998, I founded a company, Firenza, LLC., that develops and
`
`licenses high performance building blocks for semi-custom and ASIC designs. A
`
`part of those designs that I have built are memory blocks. For example, I was hired
`
`to build memory blocks for a DVD controller chip that included a MIPs processor
`
`core. The memories included i-cache, d-cache, i-tag, d-tag and 22 dual port register
`
`Page 4 of 94
`
`
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`files. I have been self-employed in my own consulting business since founding
`
`Firenza, LLC.
`
`13. My curriculum vitae is attached as EX1016.
`
`II. COMPENSATION
`In consideration for my services, my work on this case is being billed
`14.
`
`to Qualcomm at an hourly rate of $600 per hour, independent of the outcome of
`
`this proceeding. I am also being reimbursed for reasonable expenses I incur in
`
`relation to my services provided for this proceeding.
`
`III. LEGAL CONSIDERATIONS
`15. My understanding of the law is based on information provided by
`
`counsel for Qualcomm.
`
`16.
`
`I understand that a reference anticipates a claim if it discloses each
`
`and every element recited in the claim, arranged as in the claim, so as to enable a
`
`person of ordinary skill in the art (POSITA) to make and use the claimed invention
`
`without the need for undue experimentation in light of the general knowledge
`
`available in the art. I understand that a U.S. Patent document is presumed to have
`
`sufficient description to include sufficient detail for a person of ordinary skill in the
`
`art to make and use the subject matter that document describes.
`
`17.
`
`I understand that a claimed invention is obvious and, therefore, not
`
`patentable if the subject matter claimed would have been obvious to a POSITA at
`
`Page 5 of 94
`
`
`
`the time that the invention was made. I understand that a claim can be obvious in
`
`view of a single prior art reference (e.g., via modification of that prior art
`
`reference) or multiple prior art references (e.g., via a combination of two or more
`
`prior art references), if such a modification or combination was within the skill of a
`
`POSITA. I understand that there must be some articulated reasoning with some
`
`rational underpinning to support a conclusion of obviousness. I further understand
`
`that exemplary rationales that may support a conclusion of obviousness include:
`
`(1) simply arranging old elements in a way in which each element performs the
`
`same function it was known to perform, and the arrangement yields expected
`
`results, (2) merely substituting one element for another known element in the field,
`
`if the substitution yields no more than a predictable result, (3) combining elements
`
`in a way that was “obvious to try” because of a design need or market pressure,
`
`where there was a finite number of identified, predictable solutions, (4) that design
`
`incentives or other market forces in a field would have prompted variations in a
`
`work that were predictable to a person of ordinary skill in the art, and (5) that there
`
`was some teaching, suggestion, or motivation in the prior art that would have led a
`
`POSITA to modify or combine prior art references to arrive at the claimed
`
`invention.
`
`18.
`
` I understand that a claim term is interpreted according to its ordinary
`
`and customary meaning as a POSITA would have understood the term in light of
`
`Page 6 of 94
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`
`
`the surrounding claim language, other claims, the specification, and the patent’s
`
`prosecution history, which are referred to as intrinsic evidence. I also understand
`
`that prior art references cited in the patent’s prosecution history are considered
`
`intrinsic evidence. I further understand that evidence outside the patent and its
`
`prosecution history (e.g., dictionaries and technical articles), may inform the
`
`context in which a POSITA would have understood the claims of a patent. I
`
`understand
`
`this ordinary and customary meaning applies absent unique
`
`circumstances, such as where a patent clearly expresses an intent to set forth a
`
`special meaning for a term, or a claim term does not convey any particular
`
`structure to a POSITA (e.g., “means”).
`
`19.
`
`It is my understanding that it is not reasonable to interpret individual
`
`words of a claim without considering the context in which those words appear. It is
`
`also my understanding that it is the use of a particular claim term in the context of
`
`the written description and by those of skill in the art that correctly reflects both the
`
`“ordinary” and “customary” meaning of the term in the claims.
`
`IV. TASK SUMMARY
`I have been asked to review the challenged ’134 Patent. I have been
`20.
`
`asked to provide my opinions from the perspective of a person of ordinary skill,
`
`having knowledge of the relevant art, as of February 14, 2000, and the opinions
`
`Page 7 of 94
`
`
`
`stated in this declaration are from that perspective. The qualifications and abilities
`
`of such a person are described in Section VI below.
`
`21.
`
`In preparing this declaration, I have considered this patent in its
`
`entirety and the general knowledge of those familiar with the field of random
`
`access memory circuits, and specifically synchronous random access memory
`
`circuits for burst operations, as of February 14, 2000.
`
`22.
`
`I have also reviewed the references in their entirety that form the basis
`
`for Qualcomm’s challenge to the ’134 Patent, including the references and
`
`publications that are listed in the following table:
`
`Exhibit
`1001
`1002
`1003
`1004
`
`Shorthand
`’134 Patent
`
`
`’134 File History
`
`1005
`1006
`1007
`1008
`1009
`1010
`1011
`
`1012
`
`1013
`
`1014
`1015
`
`
`Fujioka
`Tiede
`
`Lysinger
`
`U.S.I.T.C Claim
`Construction Order
`N.D. Cal Claim
`Construction Order
`
`Commission
`Opinion
`Lowrey
`Murphy
`
`Description
`U.S. Patent No. 6,651,134
`Omitted
`Omitted
`Prosecution History of U.S. Patent No.
`6,651,134
`Omitted
`U.S. Patent No. 6,185,149
`U.S. Patent No. 5,900,021
`Omitted
`U.S. Patent No. 5,784,331
`Omitted
`Order 29 Construing Claims, Inv. No. 337-TA-
`792, U.S.I.T.C (February 9, 2012)
`Cypress
`Order
`Construing
`Claims,
`Semiconductor Corp. v. GSU Tech., Inc., 13-cv-
`02013-JST (N.D. Cal.) (July 29, 2014)
`Commission Opinion, Inv. No. 337-TA-792,
`U.S.I.T.C. (June 28, 2013)
`U.S. Patent No. 5,360,992
`Declaration of Robert Murphy
`
`Page 8 of 94
`
`
`
`1016
`1017
`1018
`
`1019
`
`1020
`1021
`
`1022
`
`1023
`
`
`
`Curriculum Vitae of Robert Murphy
`Murphy CV
`U.S. Patent No. 5,600,605
`Schaefer
`Cypress Whitepaper Cypress Semiconductor, Understanding Burst
`Modes in Synchronous SRAMs (June 30, 1999)
`Cypress Response Complainant
`Cypress
`Semiconductor
`Corporation's Response to Respondents' Petition
`for Review of the Remand Initial Determination
`on Validity and Enforceability (April 3, 2013)
`U.S. Patent No. 5,729,504
`Baker et al, CMOS Circuit Design, Layout, and
`Simulation (First Ed. 1998)
`in Monterey
`First Amended Complaint
`Research, LLC v. Qualcomm Incorporated, et.
`al, No. 19-cv-2083-CFC (D. Del. Feb. 14, 2020)
`Petition for Inter Partes Review, IPR2020-
`00985, Paper 1, filed May 26, 2020.
`
`Cowles
`CMOS Circuit
`Design
`Monterey FAC
`
`IPR2020-00985
`
`V. BACKGROUND OF TECHNOLOGY
`Integrated Circuit Memories
`A.
`23. Since 1969, integrated circuit memories have been manufactured for
`
`the electronics industry. Originally as Static Random Access Memories (SRAM),
`
`they were quickly followed in 1970 by Dynamic Random Access Memories
`
`(DRAM). DRAM stores data on the basis of the presence or absence of charges
`
`stored in capacitors, while SRAM retains data in flip-flop circuits.
`
`24. DRAM architectures include asynchronous DRAM and synchronous
`
`DRAM. Synchronous DRAM is similar to asynchronous DRAM, except that it
`
`uses a clocked interface and often includes a multiple bank architecture.
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`Page 9 of 94
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`
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`25. At the most basic level, a DRAM memory cell is simply a capacitor
`
`that is charged or discharged to produce a 1 or a 0. This type of memory
`
`architecture is less costly per bit (~ 4x) since it only requires a single capacitor and
`
`transistor (as shown in the representative figure below) to store the charge unlike
`
`SRAM counterparts which may require many more transistors and thus more chip
`
`space.
`
`
`
`Baker et al, CMOS Circuit Design, Layout, and Simulation (First Ed. 1998)
`
`(“CMOS Circuit Design”) Figure 17.2
`
`B. DRAM Architecture
`26. A DRAM memory device is typically a stand-alone chip that includes
`
`
`
`two primary functional components: The core memory [shaded in blue] and
`
`accompanying control circuitry that operates the memory based on received
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`Page 10 of 94
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`
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`external inputs from command, address, and data lines [yellow]. The core memory
`
`architecture includes large rectangular arrays of memory cells, with each cell
`
`connected to a row (word) line and column (bit) line. Rows are selected by a row
`
`decoder responding to a received row address (corresponding to a word line). An
`
`entire row of memory is read to or written from the sense amplifiers, with the
`
`column decoder selecting a specific sense amplifier corresponding to a column
`
`address (corresponding to a bit line).
`
`CMOS Circuit Design Figure 17.1
`
`27. Figure 1 of Schaefer illustrates an example of a complete DRAM
`
`device with control circuitry surrounding the core memory [blue]. The control
`
`circuitry connects to external command, address, and data lines [yellow] used to
`
`control operations and transfer data. In a synchronous DRAM, the command and
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`Page 11 of 94
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`
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`address lines are read on a clock transition. The control circuitry includes a
`
`command decoder [grey] that converts combinations of control signals into control
`
`commands. Additionally, the control circuitry may include a mode register [red]
`
`for storing configuration settings for configurable aspects of the chip functionality.
`
`
`
`C. DRAM Operations
`28. To accomplish an operation such as reading a piece of data, typically,
`
`an external memory controller will issue one or more external commands to the
`
`memory device. In response to an external command, the memory device will
`
`perform one or more internal procedures accessing the memory array. For
`
`example, a DRAM read operation includes several steps. First, an external
`
`ACTIVE command is used to activate or select a row in the array of DRAM cells.
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`Page 12 of 94
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`
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`As part of this command, an address signal is input to a row decoder to specify a
`
`row address. This address is then used to select and activate the row so that all data
`
`on a word line corresponding to the specified row address are read through the bit
`
`lines to sense amplifiers. Next an external READ command is used to “read” a
`
`specific column of the row that corresponds to an address. As part of this
`
`command, an address signal is input to a column decoder so as to specify a column
`
`address. Then, among the data having been read to the sense amplifiers, data on a
`
`bit line corresponding to the specified column address is selected for output.
`
`Finally, a manual PRECHARGE command is used to close the row. For writing,
`
`the operation is reversed in that data is received from the external world via the
`
`input pins, sent to the sense amplifiers and then written into the selected cells.
`
`29.
`
`In DRAM, because of the small size and dynamic architecture of the
`
`cell (electrical charge just stored on a capacitor), reading of the data is destructive.
`
`This necessarily requires the data just read to be rewritten back (writeback) into the
`
`same memory cell row before leaving it to go to another memory cell on a different
`
`row.
`
`30. When data on the same word line (namely, having the same row
`
`address) are to be continuously read, since the target data is already read to the
`
`sense amplifiers, there is no need to read the data on this word line to the sense
`
`amplifiers again. Accordingly, in this case, multiple locations along the word line
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`Page 13 of 94
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`
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`may be accessed continuously. As further discussed below, this type of memory
`
`access (generally referred to as a burst operation), allows the memory device to
`
`transmit data repeatedly without going through row activation and sense
`
`amplifying steps required to transmit each piece of data in a separate transaction.
`
`31. A typical DRAM write operation also includes several steps based on
`
`a similar series of external commands (with a WRITE command instead of the
`
`READ command). First, an external ACTIVE command is used to activate or
`
`select a row in the array of DRAM cells. As part of this command, an address
`
`signal is input to a row decoder to specify a row address. This address is then used
`
`to select and “activate” the row so that all data on a word line corresponding to the
`
`specified row address are read through the bit lines to sense amplifiers. Next, an
`
`external WRITE command is used to “write” a specific column of the row. As part
`
`of this command, an address signal is input to a column decoder so as to specify a
`
`column address. Then, among the data having been read to the sense amplifiers,
`
`the write driver “overdrives” the sense amplifier corresponding to the specified
`
`column address to match the data. Then, a writeback is conducted with the
`
`updated data and all other memory cell values are restored without change. Finally,
`
`a manual PRECHARGE command, as further discussed below, is used to close the
`
`row.
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`Page 14 of 94
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`
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`32. Once all desired operations for a row are completed, the row must be
`
`closed to protect the just written data. In other words, the bit lines must be prepared
`
`to enable the reading/writing of the next wordline. The preparation of the bit lines
`
`to enable the next operation is called precharging. A precharge operation
`
`essentially normalizes the voltage on the bit lines (bit & bit/) to a reference voltage
`
`so that the reading operation can sense a very small amount of charge contained
`
`within the memory cell. Like a teeter-totter or mechanical scale, the two bit lines
`
`(the two sides of the scale) are electrically forced to be equal such that a very small
`
`amount of charge can be sensed by the sense amplifier.
`
`33. Due to the imperfections in the formation of the capacitors in the
`
`manufacturing process, DRAM memory cells eventually lose all of their stored
`
`charge due to leakage. If the charge is lost, then so is the data. To prevent this from
`
`happening, DRAMs must be refreshed so that the charge on the individual memory
`
`cells is restored periodically. The frequency with which refresh must occur
`
`depends on the silicon technology used to manufacture the memory chip and the
`
`design of the memory cell itself. In most cases, refresh cycles involve restoring the
`
`charge along an entire row. Over the course of the entire interval, every row is
`
`accessed and restored and at the end of the interval, the process begins again.
`
`Reading or writing a memory cell has the effect of refreshing the selected cell.
`
`Unfortunately, during normal accesses (regular reads/writes by the processor) not
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`Page 15 of 94
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`
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`all cells are read or written within the time limitations. Thus, as further discussed
`
`below, each cell in the array must be accessed and restored during the refresh
`
`interval.
`
`34. There are several different ways to refresh a memory array. Three
`
`common refresh options include (i) system refresh, which involves refreshing one
`
`row at a time, based on a system supplied row address, such that all rows are
`
`refreshed within a required time interval, (ii) self-refresh, also referred to as auto
`
`refresh, which uses an on-chip oscillator to determine the refresh frequency and a
`
`counter to keep track of addressing, and (iii) hidden refresh, in which a read or
`
`write operation and a refresh cycle are performed during a single CAS active
`
`period.
`
`D. External Commands v. Internal Operations
`35. There is not always a one-to-one correspondence between a complete
`
`operation, external commands, and internal chip operation. As can be seen from
`
`the examples above, in some cases a single complete operation requires issuance of
`
`a series of external commands such as “active,” “read,” and “precharge” to perform
`
`a read. Likewise, a single complete write operation may require issuance of a
`
`series of external commands such as “active,” “write,” and “precharge” to perform
`
`a write. In other cases, the memory device conducts a series of operations in
`
`response to a single external read or write command. For example, the device
`
`Page 16 of 94
`
`
`
`moving a row of data to sense amplifiers, serially exporting one or more pieces of
`
`data from the sense amplifiers to the data line, and writing back from the sense
`
`amplifiers to a row—all in response to a single read command.
`
`36. Each internal operation takes a set period of time and occupies certain
`
`portions of the circuitry. Some operations, including writeback, refresh, and
`
`precharge, are essential to maintaining the integrity of the data stored in the
`
`memory and must be allowed to complete. Accordingly, the device will not permit
`
`other operations to interrupt those operations.
`
`37. Prior to the ’134 Patent, memory designers developed additional
`
`external commands that combine and optimize what was previously accomplished
`
`with multiple external commands with a single external command. For example,
`
`burst READ and WRITE commands, are discussed below. Another example
`
`disclosed in Schaefer is a READ or WRITE burst “with AUTO-PRECHARGE”
`
`command in which “a manual PRECHARGE command does not need to be issued
`
`during the functional operation of SDRAM 20” but instead, “the precharge is
`
`initiated at the earliest, valid stage within a burst cycle.” EX1017, 7:38-43.
`
`Burst Operation and Interruption/Termination
`E.
`38. Well before the ’134 Patent, the concept of locality was discovered
`
`and it was shown that the data required from/to memory by the central processing
`
`unit (CPU) often resided very near (in address space) to previous data accessed.
`
`Page 17 of 94
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`
`
`This knowledge allowed the data to be accessed in a “burst” (many bits in a tight
`
`efficient group) using only a starting address and a size of the block of data to be
`
`accessed. The memory device itself would calculate the other needed addresses
`
`and deliver the block of data in a burst.
`
`39.
`
`In known burst operations, an initial address is provided with the
`
`external command. The memory device reads/writes from/to that initial location as
`
`well as additional locations within the burst, internally generating the addresses of
`
`the additional locations within the burst. In this case, by specifying read start
`
`addresses (row and column addresses) and a bank, data can be continuously output
`
`in synchronization with a clock. In this manner, since the memory outputs data
`
`every clock, the data can be more rapidly output. This discovery allowed the
`
`memory system to achieve greater efficiency and more throughput. A prior art
`
`paper, from the original assignee of the ’134 Patent cited on the face of the patent,
`
`illustrates exemplary hardware and a flowchart for generating these addresses.
`
`Page 18 of 94
`
`
`
`Address_
`
`.'
`
`Clk —*
`
`
`
`Address Latch
`
`
`
`U
`Aggress
`bits
`
`Lower
`2 Address
`bits
`
`Mode __.,
`
`
`A0
`A1
`
`2
`
`2
`
`ADV
`
`—>
`
`2-Bit Counter
`
`Figure 1. Key Signals for Burst Feature on Typical
`SRAMs
`
`EX1018, Figure 1.
`EX1018, Figure 1.
`
`
`
`Figure Z. Burst Mode Address Update
`EX1018, Figure 2.
`EX1018, Figure 2.
`
`
`
`
`
`Page 19 of 94
`
`Page 19 of 94
`
`
`
`40. The length of a data burst may be defined in a number of ways. A
`
`system may be designed to operate with only a single burst length. Additionally, as
`
`in Schaefer, the burst length may be programmable through programming a mode
`
`register. EX1017, 6:1-3.
`
`41. Additionally, in some systems, the burst can be interrupted or
`
`terminated.
`
` This may be accomplished by using a dedicated “BURST
`
`TERMINATE” command or, in some systems, by issuing a command for a new
`
`“read,” “write,” or “precharge” operation. Terminating, or interrupting, a burst
`
`allows the user to create a burst of an arbitrary length. For example, if a user
`
`desires to read six consecutive pieces of data, a burst operation would be more
`
`efficient than issuing six “read” commands, but a burst of length eight would still
`
`result in two wasted cycles outputting data for the seventh and eighth memory
`
`locations. Therefore, terminating the burst to have six outputs would be
`
`advantageous.
`
`42. While supporting burst termination/interruption can be advantageous,
`
`a chip designer may choose not to offer such functionality where the necessary
`
`internal operations of the particular burst would conflict with terminating the burst.
`
`In such a case, the chip design can indicate that termination/interruption is not
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`permitted by specifying that additional commands during a given period of time
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`are “not allowed” or “illegal.”
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`43. Schaefer demonstrates such design choices. For one type of burst, a
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`“full page burst,” Schaefer explains that the device “will wrap around and continue
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`writing data until terminated by the BURST TERMINATION command,
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`PRECHARGE command, or until interrupted with another burst operation.
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`EX1017, 5:59-62. However, for another type of burst, a READ burst with AUTO-
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`PRECHARGE, which is a burst of length 2, 4, or 8 in which “precharge is initiated
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`at the earliest, valid stage within a burst cycle,” “[t]he user is not allowed to issue
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`another command until the precharged time (tRP) is completed.” Id., 7:38-44.
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`VI. A PERSON OF ORDINARY SKILL IN THE ART
`I have been asked to offer an opinion on the level of skill of a person
`44.
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`of ordinary skill in the art (POSITA) for the ’134 Patent as of February 14, 2000,
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`which I understand is the earliest claimed priority date to which the ’134 Patent
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`claims priority.
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`45.
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`I understand that the level of ordinary skill may be reflected by the
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`prior art of record, and that a POSITA to which the claimed subject matter pertains
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`would have the capability of understanding the scientific and engineering
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`principles applicable to the pertinent art.
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`46.
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`I understand there are multiple factors relevant to determining the
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`level of ordinary skill in the pertinent art, including (1) the levels of education and
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`experience of persons working in the field at the time of the invention; (2) the
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`Page 21 of 94
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`sophistication of the technology; (3) the types of problems encountered in the field;
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`(4) the prior art solutions to those problems; and (5) the rapidity with which
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`innovations are made.
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`47. The ’134 Patent relates to “memory devices generally and, more
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`particularly, to a memory device that transfers a fixed number of words of data
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`with each access.” EX1001, 1:6-8. It discloses “an integrated circuit comprising a
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`memory and a logic circuit.” Id., 1:48-49. It further discloses that the “memory
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`may comprise a plurality of storage elements each configured to read and write
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`data in response to an internal address signal. The logic circuit may be configured
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`to generate a predetermined number of the internal address signals in response to
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`(i) an external address signal, (ii) a clock signal and (iii) one or more control
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`signals. The generation of the predetermined number of internal address signals
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`may be non-interruptible.” Id., 1:49-56. A POSITA would thus have been familiar
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`with random access memory circuits, and specifically synchronous random access
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`memory circuits for burst operations.
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`48.
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`In light of the specification, file history, and claims of the ’134 Patent,
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`in my opinion, a POSITA as of the priority date would have had at least a degree in
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`electrical or computer engineering, and at least two years of experience in design,
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`development, and/or testing of memory circuits, related hardware design, or the
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`equivalent, with additional education substituting for experience and vice versa.
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`All of the opinions that I offer herein are from the perspective of a POSITA as of
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`the priority date.
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`49.
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`I am familiar with the knowledge and capabilities that a POSITA of
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`random access memory devices would have possessed in February 2000. My
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`experience in the field of random access memory in relation to both academia and
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`industry up to and including February 2000 allowed me to become personally
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`familiar with the knowledge and capabilities of a POSITA in the area of random
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`access memory devices. In February 2000, my expertise met or exceeded that of a
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`POSITA.
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`VII. THE ’134 PATENT
`A. Overview of the ’134 Patent
`50. The ’134 Patent describes a memory circuit that allows for “non-
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`interruptible” data bursts where “refresh activity (e.g., writeback, read for refresh,
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`and writeback for refresh) may be completed within the time of the burst transfer.”
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`EX1001, 1:55-56, 5:10-13. This allows the memory circuit to “operate at higher
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`frequencies without needing interrupts to perform refreshes of data”. Id., 1:66-67.
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`51.
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`In addition, according to the ’134 Patent, a “fixed length non-
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`interruptible burst generally frees up the address bus and control bus for a known
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`number of cycles.” Id., 3:56-58.
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`Page 23 of 94
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`52. As shown in Figure 1 of the ’134 patent (annotated below), the circuit
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`(100) has a logic circuit (102) [yellow] that generates multiple internal address
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`signals (ADDR_INT) that are fed into a memory (104) [blue] to write/read burst
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`data to/from the memory (104). The memory (104), which is sometimes referred to
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`as the “memory array,” is where data is stored (a “write” operation) or accessed (a
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`“read” operation). Id., 5:23-25 (claim 1), 2:26-30, 61-65, 3:2-4.
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`53. As further depicted in Figure 2 (annotated below), an embodiment of
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`the logic circuit includes an address counter register (126) [yellow] and a burst
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`counter (130) [green]. The logic circuit may generate the predetermined number of
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`internal address signals when the address counter register (126) receives (i) an
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`Page 24 of 94
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`external address signal (ADDR_EXT), (ii) a clock signal (CLK) and (iii) one or
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`more control signals (e.g. LOAD/ADV) Id., 5:26-29 (claim 1); 3:65-4:1.
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`54. For example, the address counter register (126) latches in external
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`address ADDR_EXT when the LOAD signal (108) is asserted to generate an initial
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`internal address. Id., 4:6-8. Subsequent internal addresses are generated when the
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`ADV is asserted, which causes the burst counter (128) to output the BURST_CLK
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`signal in response to each CLK signal. Upon receipt of the BURST_CLK signal,
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`the address counter register (126) increments the latched address to generate and
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`output the next internal address. Id., 4:8-14. Further, “[o]nce the circuit (102) has
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`started generating the fixed number of addresses, the circuit (102) will generally
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`not stop until the fixed number of addresses has been generated (e.g., a non-
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`interruptible burst).” Id., 3:25-29.
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`55. A second embodiment of the logic circuit depicted in Figure 3
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`(annotated below) includes a latch (134) [yellow], counter (138) [green] and
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`multiplexer (136) [purple]. This embodiment substantially matches prior art
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`EX1018, discussed above. Compare EX1001, Figure 1. To perform the addressing
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`for the burst operation, an external address (ADDR_EXT) is divided into an m-bit
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`portion and a k-bit portion