l|||||||||l|||l||||||lIllll|||l|lllll||||||||||||||||||l|||l||l|||Illllllll
`
`USOOS784331A
`
`Unlted States Patent
`
`[19]
`
`[11] Patent Number:
`
`5,784,331
`
`
`Lysinger
`[45] Date of Patent:
`Jul. 21, 1998
`
`[54] MULTIPLE ACCESS MEMORY DEVICE
`
`5,526,320
`
`6/1996 Zagar et a1.
`
`......................... 365/2335
`
`[75]
`Inventor: Mark A. Lysinger. Carrollton. Tex.
`.
`.
`.
`[73] Ass1gnee: SGS-Thomson Microelectronics, Inc..
`Carrollton. Tex.
`
`[21] APp1‘ No.2 775’664
`[22]
`Filed:
`Dec. 31, 1996
`
`
`..................... G11C 8/00
`Int. C1.6
`[51]
`[52] US. Cl. ................................ 365/230.06: 365/189.05;
`365/230-08
`[58] Field of Search ......................... 365/230.06. 230.08.
`355/13905
`
`[56]
`
`.
`References Cited
`US. PATENT DOCUMENTS
`
`.................. 365030.06
`6/19% Slemmer et al.
`5,124,951
`
`5,261,064 11/1993 Wyland .................... 395/400
`528“” “1994 Miyaji 6‘ a“
`ggggggg
`
`5.315548
`5/1994 001m eta].
`..
`5,319,759
`6/1994 Chan ........................ 395/400
`
`5,453,957
`9/1995 Norris et a].
`365030.04
`11/1995 Haraguchi .......................... 365/230.06
`5,469,391
`
`Primary Examiner—-Son T. Dinh
`Att
`, A
`t,
`F'rm—D Vid V. C lson; Th 0d
`Gafa’i’iztfiyay; {1:3 I? Jolrgensona
`ar
`e
`[57]
`ABSTRACT
`
`E.
`
`ore
`
`A memory circuit has a plurality of data storage locations
`and an address associated with each data storage location. A
`first decoded address storage circuit stores a first decoded
`memory amass and outputs the stored first decoded
`memory address. A second decoded address storage circuit
`stores a second decoded memory address and outputs the
`stored second decoded memory address. An address access
`circuit is coupled to the output of the first decoded address
`storage circuit and accesses the data storage location asso-
`ciated with the first decoded memory address in response to
`the first decoded memory address being output from the first
`decoded address storage c1rcu1t. A control elrcuit is coupled
`to the first decoded address storage circuit fof controlling the
`transfer of decoded memory address information from the
`second decoded address storage circuit to the first decoded
`.
`.
`address Storage ““3““
`
`13 Claims, 22 Drawing Sheets
`
`FROM MEMORY BLC<0sy>
`05115
`
`80
`
`—
`
`94
`
`27
`\
`
`0 (x)
`
`69\‘
`
`DATA
`INPUT
`BUFFER
`
`_DR[VER
`WRITE
`mac
`COLUMN
`WDPC -— mun
`44 WW
`I
`SELECT
`45
`CIRCUIT
`(FIG. 22)
`
`BLT<0.y>
`
`75
`
`88
`
`ISO
`
`cor. 5a.
`
`SENSE
`mp
`
`“KL—J5,15” 95
`(67
`
`96
`K
`
`L
`
`SECURE?
`
`OUTPUT
`
`or
`
`I
`
`K
`95
`
`
`RESET
`BLOCK
`WRITER
`
`
`READ/WRITE
`.95
`
`53f CONTROL
`
`
`
`Qualcomm Incorporated
`EX1009
`
`Page 1 of 38
`
`31mg
`
`48 BSBTB
`
`1
`45
`
`g7
`
`RESET
`
`955’ B
`
`RESET
`CONTROL
`55/
`l
`34 may
`313%ng
`(FIG 3)
`
`7'5
`SAENB 1’
`
`110
`
`COLUMN
`ADDRESS BURST
`COUNTER
`
`[0
`31“
`
`40
`
`
`
`Qualcomm Incorporated
`EX1009
`Page 1 of 38
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 1 of 22
`
`5,784,331
`
`an
`
`.IIIi-IIEI.
`
`Ilaa'.IIEIIE-nglH-Imm".
`
`IEEI-IIIII-_
`
`a$8
`
`v.0
`
`Page 2 of 38
`
`Page 2 of 38
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 2 of 22
`
`5,784,331
`
`vm
`
`9mm
`
`umme
`
`a2<
`
`Km
`
`Mm
`
`Kw
`
`Qwa
`
`zfixw
`
`mK
`
`mm
`
`9mm
`
`Kmk
`
`mm
`
`mm
`
`222400
`
`H_:om_o
`
`Homgmm
`
`h_:om_o
`
`S.03
`
`gwam
`
`om
`
`0.3mm
`
`I
`
`
`
`$8mmwge‘5%?
`
`$538“$8me
`
`mat
`
`2238SEEa:mm.
`
`.mm48
`
`mmm5%max
`
`5mmSEZS
`
`mzm<m
`
`m»
`
`MNK
`
`mm
`
`Rug:vw
`
`mgksm
`
`Samm.»
`
`m»
`
`«5kaE
`
`mm
`
`E
`
`a3.3%EE:SE
`mVNNumN
`
`um§
`
`zmzmo
`
`mzmzkQ
`
`9Q
`
`gm
`
`NN
`
`(r/tmm
`
`<h<o
`
`H3¢z_
`
`mmugpm
`
`KN
`
`Qua
`
`AlllllllltlmmKmqu
`
`530
`
`mg
`
`Egg
`
`XQOAm
`
`Emiofim
`
`Joszoo
`
`‘II'IIIIIIII'I
`
`mm<>gg
`
`mm:
`
`mm
`
`mam
`
`pnmkzo
`
`mmumzm
`
`mo
`
`Page 3 of 38
`
`Page 3 of 38
`
`
`
`
`
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 3 of 22
`
`5,784,331
`
`
`
`53Emzzomo;85E832%$502§
`55%gig
`55mm25E1055mm26m:‘EEcm>m\cuo<
`
`mzjomo;
`
`t.OE8:8¢.93a.03
`
`m?
`
`505oz<
`
`Egg55mm
`
`a.05
`
`a.2:H585
`
`$53858
`
`max22389I$559.505
`
`agg<cga
`
`muooomo
`
`a.05
`
`3933E
`
`23%;
`
`55%$50)5
`
`my.ME%3m9928Em3‘85é
`
`30:BM:
`
`053
`
`E
`
`Page 4 of 38
`
`Page 4 of 38
`
`
`
`
`
`
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 4 of 22
`
`5,784,331
`
`”.50
`
`930
`
`com
`
`2_
`
`Ba
`
`Page 5 of 38
`
`Page 5 of 38
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 5 of 22
`
`5,784,331
`
`Dmaven
`
`>.
`
`[/606 >.
`
`/l
`
`>.
`
`Vcc
`
`574
`
`604WeD}.
`
`}-IR—Aodd
`
`}.
`
`}.
`
`-
`
`572
`
`D .
`
`p
`
`AONEO
`
`\676’
`
`Fig.5
`
`
`
`FOFFEOD—————o| /6I6
`
`608
`
`Page 6 of 38
`
`Page 6 of 38
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 6 of 22
`
`5,784,331
`
`00>
`
`$68II“I.A
`
`V.
`
`.co>m<m
`
`IE
`I
`
`A
`
`E
`
`Page 7 of 38
`
`Page 7 of 38
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 7 of 22
`
`5,784,331
`
`'
`
`”g 7 W
`
`770
`
`792
`
`112
`
`Eeven
`
`
`204
`
`
`
`R_D—Leven D
`
`D LWLeven
`
`Page 8 of 38
`
`Page 8 of 38
`
`

`

`US. Patent
`
`Jul. 21, 1993
`
`Sheet 8 of 22
`
`.
`
`5,784,331
`
`50
`
`700
`\\
`
`
`706
`
`706
`
`FIg. 9A
`
`ROW ADDRESS -------
`
`CLOCKI -------
`
`
`
`g
`
`“S
`E
`O
`
`a
`<
`0:
`
`g
`0
`
`B
`D
`
`E
`0:
`
`m
`
`L;
`E
`O
`
`571
`<
`c:
`
`g
`O
`
`a
`Q
`
`g
`C}:
`
`m
`
`L;
`E
`Q
`
`E
`<2
`Ix
`
`g
`O
`
`a
`C:
`
`E
`[I
`
`COLUMN AND
`
`BLOCK ADDRESSES
`
`708
`
`INPUT REGISTERS
`
`
`
`
`is
`in
`E
`g
`§
`§
`
`
`COLUMN AND BLOCK SELECT
`
`CLOCKI SENSE AMPS AND STORAGE REGISTERS
`
`
`
`
`DATA INPUT AND OUTPUT
`‘/T
`
`776
`774 772
`
`CLOCK 1 ------------
`
`AND DECODERS
`
`CLOCK 2 ---------------------------------------------------------------
`
`BURST COUNTER
`
`CLOCK 2 ---------------------------------------------------------------
`
`Fzg. QB
`SINGLE BLOCK - T28 COLUMNS — EIGHT I/O GROUPS
`
`700
`
`BLOCK SELECTED
`
`
`
`
`
`CLOCK ‘ """"""
`
`
`
`CLOCK 2----—---
`
`
`
`SELECT ONE
`COLUMN OF FOUR
`
`IN EACH COUNT.
`
`SENSE AMPS AND
`STORAGE REGISTERS
`
`BURST COUNTER
`
`DATA OUT
`
`Page 9 of 38
`
`CLOCK 2-------
`
`DATA INPUT AND OUTPUT
`
`Page 9 of 38
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 9 of 22
`
`5,784,331
`
`f.2:
`
`Exam
`
`ijomzzoo
`
`a:,3§§
`
`
`
`$383me:zoma10.2..
`
`mmmmog$535”993oz<
`
`2238mmmmogEtzm5&2I2238
`
`mmmmoox‘
`
`2238
`
`SN
`
`
`2:382.238amso55%
`
`
`2238
`
`mmmmoo<
`
`E083$5385%E.25mmmmomfi
`
`
`
`:DoEozoom—omm
`
`
`
`
`
`
`QN%~K82v$78A.vEm3m%558%E.2::o:g
`
`90
`
`Page 10 of 38
`
`Page 10 of 38
`
`
`
`
`
`
`
`
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 10 of 22
`
`5,784,331
`
`o55
`
`F.55
`
`m50m50
`
`v.55
`
`
`
`m,.50
`
`555
`
`N.5o
`
`w.50
`
`m.55
`
`Z.559.50
`
`N:
`
`255S55
`
`.1.55
`
`955
`
`N:
`
`9.)
`.325%..
`
`EEO""$885.53NEWmmmmgfi
`Ed22238ms
`
`III}?
`
`mwjoEzoo
`
`5E5
`
`-
`
`ll-EHi_—=$083?"I
`
`
`all“«IlflfifilP.-izi.HI
`.mII.=-..flfl..._=2%....”nIII:_..
`
`
`“filiaLmelfiuu
`'fillI-II—.....gWI.iia........K.we
`
`“ml"Hi._Iaflufl....ll.“al.-Ii
`
`
` I_.%~WHIIHinfl:DQEQ\N.K
`“$15!...“mmmrlwwi
`_l-E.-III.“WEI-flIum
`ThiamflI.I.u.
`
`1:258.HI”3mIN2mI”z:2mnI”2"r.....MmeJ3.2:
`
`mama?
`
`5&2.
`
`Eta
`
`oz<
`
`Epmé
`
`:85
`
`585
`
`Page 11 of 38
`
`Page 11 of 38
`
`
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 11 of 22
`
`5,784,331
`
`125
`
`128
`
`Fig.12
`
`’—
`38 E
`XO—
`
`7/7
`
`KINC
`
`Page 12 of 38
`
`Page 12 of 38
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 12 of 22
`
`5,784,331
`
`fig. 13
`
`7.37
`
`I 05
`
`/
`
`OUTC
`
`FOFFB
`
`AOP
`
`AON
`
`1.37
`
`A1
`
`FON[:>———————————————————4
`747
`
`CAxC
`
`CAxT
`
`Page 13 of 38
`
`Page 13 of 38
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 13 of 22
`
`5,784,331
`
`IIL
`
`
`......................................................................................................LSm:
`
`5
`
`v?
`
`.0;
`
`‘tv.
`
`I33%
`
`.05.2w
`
`Page 14 of 38
`
`Page 14 of 38
`
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 14 of 22
`
`5,784,331
`
` N2
`
`.292m.28%
`
`.:x.omx.Rx
`
`.0;
`
`I35aI05%
`
`Page 15 of 38
`
`Page 15 of 38
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 15 of 22
`
`5,784,331
`
`
`
`00>
`
`I/mS
`
`I35%
`
`05%
`
`ND
`
`.051m‘23%
`
`m2
`
`an“
`
`<>
`
`m»
`
`Page 16 of 38
`
`Page 16 of 38
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 16 of 22
`
`5,784,331
`
`YB
`
`CRYUP I
`
`skLBAyT skUpT
`
`skLCAt
`
`-skLCAc CRYDN'
`sanC II
`sanT in.
`302
`CARRY .mll
`COL.
`YA
`"'—
`HIIIII
`CRYUP
`YB
`IIEEE- SkLBAyC “UPC I:IIIIII
`
`CRYUP:
`
`sanT“Elli
`fll
`Rngml
`um
`COL
`YA
`“In
`RRRRRIIIIIII“
`RR
`IIIII- W C W CIIn
`Illl-:kLBAYR :kUPRII:IIII|
`y
`p
`IE=5kLCAc CRYDN ‘fllll
`RRRRRImI
`COL:
`
`skLCAt
`
`sanC
`
`skLCAt
`
`sanC
`
`.fll'
`
`I 08
`
`Page 17 of 38
`
`Page 17 of 38
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 17 of 22
`
`5,784,331
`
`,///’”
`
`
`
`skUp
`san
`k
`
`4
`
`ijO
`
`- COLT!
`
`i
`:
`g 405
`40’!
`
`K
`
`471 K1
`
`424
`422
`412
`
`SLAVE
`STORAGE
`MASTER
`'5
`i___________________________S222___________________________
`404
`407
`409
`410
`
`40!
`
`'
`
`405
`
`K
`
`4M K1
`
`
`424 6"“ 45?
`422
`3
`“
`k
`5
`4,2
`
`MASTER
`
`STORAGE
`
`SLAVE
`
`403
`
`
`
`401 406
`
`K
`
`47/ K1
`
`
`424 skgrup 4J2
`422
`5k
`472
`
`'
`
`MASTER
`
`STORAGE
`
`404
`
`407
`
`409
`
`400
`
`40,405
`
`K
`
`411m
`
`422
`412
`
`'
`
`MASTER
`
`STORAGE
`
`404
`
`407
`
`409
`
`400
`
`
`
`Page 18 of 38
`
`Page 18 of 38
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 18 of 22
`
`5,784,331
`
`4041\{4
`407
`
`09
`
`475 4/5 408
`424
`
`4I0
`
`SW9 432
`
`MASTER
`
`MASTER
`
`STORAGE
`
`STORAGE
`
`404 407
`
`409
`
`413 41540
`
`424
`
`4 [2
`
`sk
`
`5kUP 432
`
`
`
`MASTER
`
`STORAGE
`
`STORAGE
`
`SLAVE
`
`MASTER
`
`
`
`
`
`
`
`409
`
`4407
`
`4U 4 I540
`
`424
`
`4’7
`
`MASTER
`
`STORAGE
`
`STORAGE
`
`404 407
`
`409 4/3 41540
`
`:5kUP 452
`
`
`k5
`
`SLAVE
`
`MASTER
`
`fig. 20
`
`Page 19 of 38
`
`Page 19 of 38
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 19 0f 22
`
`5,784,331
`
`33%I
`
`05%I
`
`3%I.
`
`ma,
`
`95%I.‘I
`
`33v...“II33%
`23%.‘51%
`:97,II395
`AIET:
`
`I9
`
`Page 20 of 38
`
`Page 20 of 38
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 20 of 22
`
`5,784,331
`
`Vcc
`
`°
`
`268
`
`0
`
`270
`
`80
`
`I BLC
`
`
`
`90
`
`D RBT
`
`92
`
`3 RBC
`
`144
`
`I
`
`82
`BLT D
`BLL D
`
`BLEO -
`
`WBT D
`
`WBC -
`
`75
`
`’4
`
`132
`
`COL - - }
`
`730
`
`736
`
`740
`
`fig. 22
`
`Page 21 of 38
`
`Page 21 of 38
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 21 of 22
`
`5,784,331
`
`566
`
`MEMORY
`
`
`
`
`DATA
`STORAGE
`
`DEVICES
`
`
`
`Fig. 23
`
`
`
`
`COMPUTER
`SYSTEM
`
`50
`
`INPUT
`DEVICES
`
`562
`
`
`
`OUTPUT
`DEVICES
`
`564
`
`ADSP
`
`PENTIUM
`
`0(0-31)
`
`CTRL
`
`ADDR
`
`
`
`CACHE
`CONTROLLER
`
`ADSC
`ADV
`cgs
`
`WEI-8
`
`Page 22 of 38
`
`Page 22 of 38
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 22 of 22
`
`5,784,331
`
`Emwfi
`
`E
`
`@-
`
`IIi—‘E.
`11
`
`Efilo
`
`moo<ES
`
`$30328
`
`$55
`
`Page 23 of 38
`
`Page 23 of 38
`
`

`

`1
`MULTIPLE ACCESS MEMORY DEVICE
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`The following pending US. patent applications by David
`C. McClure entitled: “Architecture Redundancy.” Ser. No.
`08/5 82.424 (Attorney’s Docket No. 95-C-136). and “Redun-
`dancy Control.” Ser. No. 08/580.827 (Attorney’s Docket
`No. 95-C-l43). which were filed on Dec. 29. 1995. and have
`the same ownership as the present application. and to that
`extent are related to the present application. which are
`incorporated herein by reference; and entitled: ‘Test Mode
`Activation And Data Override.” Ser. No. 08/587.709
`(Attorney’s Docket No. 95-C—137). “Pipelined Chip Enable
`Control Circuitry And Methodology.” Ser. No. 08/588.730
`(Attorney’s Docket No. 95—C-138). “Output Driver Cir-
`cuitry Having A Single Slew Rate Resistor.” Ser. No.
`08/588.988 (Attorney’s Docket No. 95-C—139). “Synchro—
`nous Stress Test Control.” Ser. No. 08/589.015 (Attorney’s
`Docket No. 95-C-142). “Write Pass Through Circuit." Ser.
`No. 08/588.662 (Attorney’s Docket No. 95-C- 144). “Data-
`Input Device For Generating Test Signals On Bit And
`Bit-Complement Lines." Ser. No. 08/588.762 (Attorney’s
`Docket No. 95-0145). “Synchronous Output Circuit." Ser.
`No. 08/588.901 (Attorney's Docket No. 95—C-146). “Write
`Driver Having A Test Function.” Ser. No. 08/589.14l
`(Attorney’s Docket No. 95-C-147). “Circuit And Method
`For Tracking The Start Of AWrite To A Memory Cell.” Ser.
`No. 08/589.139 (Attorney’s Docket No. 95-C— 148). “Circuit
`And Method For Terminating A Write To A Memory Cell."
`Ser. No. 08/588.737 (Attorney’s Docket No. 95-C-149).
`“Clocked Sense Amplifier With Word Line Tracking." Ser.
`No. 08/587.782 (Attorney’s Docket No. 95-C-150).
`“Memory-Row Selector Having ATest Function.” Ser. No.
`08/589.l40 (Attorney’s Docket No. 95—C-151). “Synchro-
`nous Test Mode Initialization.” Ser. No. 08/588.729
`(Attorney’s Docket No. 95-C—153). “Device And Method
`For Isolating Bit Lines FromA Data Line.” Ser. No. 08/588.
`740 (Attorney’s Docket No. 95-C-154). “Circuit And
`Method For Setting The Time Duration Of A Write To A
`Memory Cell.” Ser. No. 08/587.7ll (Attorney’s Docket No.
`95-C—156). “Low-Power Read Circuit And Method For
`Controlling A Sense Amplifier." Ser. No. O8I589.024
`(Attorney’s Docket No. 95-C-168). “Device And Method
`For Driving A Conductive Path With A Signal." Ser. No.
`08/587.708 (Attorney’s Docket No. 95-C-169). and the
`following pending US. patent application by Mark A.
`Lysinger entitled: “Burst Counter Circuit And Method of
`Operation Thereof.” Ser. No. 08/589.023 (Attorney’s
`Docket No. 95—C-14lA). all of which have the same eifec-
`tive filing date and ownership as the present application. and
`to that extent are related to the present application. which are
`incorporated herein by reference.
`
`FIELD OF THE INVENTION
`
`This invention is related generally to a burst counter
`circuit and more specifically to a pipelined address scheme
`for storing a second decoded memory address while the
`burst counter circuit is accessing memory locations associ-
`ated with a first decoded memory address.
`
`BACKGROUND OF THE INVENTION
`
`As synchronous burst SRAMs become more popular.
`market pressure to improve performance is increased. Part of
`the increased performance has been obtained by pipelining
`data. While pipelining data increases the speed at which the
`
`65
`
`5.784.331
`
`2
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`data is provided to a user. it does not increase the speed of
`the cycle time nor shorten the overall time required to get
`data into or out of specific addresses within a memory array.
`One known technique for increasing the speed at which
`data is read out of a memory is to use a burst counter which
`increments the input and memory address under the control
`of a clock without requiring new address to be input. Prior
`art burst SRAMs used a burst counter which manipulated the
`address signal before it was input to the address decoder
`circuit. In these SRAMs. the output of the burst counter was
`then passed to an address decoder. This type of burst counter
`could also easily be attached to the front of existing syn-
`chronous designs with no significant changes required to the
`memory core or to the synchronous decoder. Using this
`technique. the memory could use well known and reliable
`decoder circuits to select the rows and columns. One down—
`side of this approach is that all address transitions must still
`propagate through the address decoder. The speed at which
`address signals can propagate through the address decoder
`may become a limiting factor at faster cycle times.
`SUMMARY OF THE INVENTION
`
`invention. a
`According to principles of the present
`memory circuit has a plurality of data storage locations and
`an address associated with each data storage location. Afirst
`decoded address storage circuit stores a first decoded
`memory address and holds it for accessing a particular
`memory address. A second decoded address storage circuit
`stores a second decoded memory address and holds it for
`accessing a second decoded memory address. A control
`circuit is coupled to the first decoded address storage circuit
`and operates to transfer decoded memory address inforrna—
`tion from the second decoded address storage circuit to the
`first decoded address storage circuit.
`In one embodiment. a counter circuit is coupled to the
`output of the first decoded address storage circuit for access-
`ing the data storage location associated with the first
`decoded memory address in response to the first decoded
`memory address being output from the first decoded
`memory circuit. The counter circuit includes a burst counter
`circuit which accesses the data storage location associated
`with the first decoded memory address and also accesses
`three additional data storage locations. the decoded memory
`addresses associated with these three additional data storage
`locations being generated by the burst counter circuit using
`the first decoded memory address.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram of a memory device in accor-
`dance with the present invention.
`FIG. 2 is a block diagram of one embodiment of a
`read/write circuit of the memory device of FIG. 1.
`FIG. 3 is a block diagram of one embodiment of a row
`addressing circuit of the memory device of FIG. 1.
`FIG. 4 is a schematic of the address input buffer of FIG.
`
`3.
`
`FIG. 5 is a schematic of the even/odd row selector of FIG.
`
`3.
`
`FIG. 6 is a detailed schematic of the word line and block
`select circuit of FIG. 3.
`FIG. 7 is a detailed schematic of the word line select
`circuit of FIG. 3.
`FIG. 8 is a detailed schematic of the local word line drive
`circuit of FIG. 3.
`
`FIG. 9A is a block diagram of an SRAM in accordance
`with one embodiment of the present invention.
`
`Page 24 of 38
`
`Page 24 of 38
`
`

`

`5.784.331
`
`3
`FIG. 9B is a detailed block diagram of one of the blocks
`of the SRAM of FIG. 9A.
`
`FIG. 10 is a block diagram. of the pipelined column
`address burst counter circuit in accordance with one embodi-
`ment of the present invention.
`FIG. 11 is a more detailed block diagram of one embodi-
`ment of the pipelined column address burst counter circuit of
`the present invention.
`FIG. 12 is a schematic of the column address input bufier
`and master latch circuit of FIG. 11.
`FIG. 13 is a schematic of the column address driver circuit
`of FIG. 11.
`
`FIG. 14 is a schematic of the column address predecoder
`circuit of FIG. 11.
`FIG. 15 is a schematic of one embodiment of the column
`address decoder circuit and slave latch circuit of FIG. 11.
`FIG. 16 is a schematic of another embodiment of the
`column address decoder circuit and slave latch circuit of
`FIG. 11.
`FIG. 17 is a schematic of still another embodiment of the
`column address decoder circuit and slave latch circuit of
`FIG. 11.
`
`FIG. 18 is a functional block diagram of one embodiment
`of the burst counter circuit of FIG. 10.
`
`FIG. 19 is a functional block diagram of another embodi-
`ment of the burst counter circuit of FIG. 10 comprising a
`plurality of latches.
`FIG. 20 is a functional block diagram of still another
`embodiment of the burst counter circuit of FIG. 10 com-
`
`prising a plurality of latches.
`FIG. 21 is a schematic of the burst controller of FIG. 10.
`FIG. 22 is a schematic of the column select circuit of FIG.
`
`10
`
`FIG. 23 is a block diagram of a computer system includ—
`ing a memory device according to the present invention.
`FIGS. 24 and 25 are block diagrams of alternative
`embodiments of computer systems using a memory device
`of the present invention.
`
`DETAJLED DESCRIPTION OF THE
`INVENTION
`
`FIG. 1 shows a memory device 50 having a memory array
`52 thereon.
`
`The memory array 52 is subdivided into a plurality of
`memory array blocks 54. The memory array 52 is subdi-
`vided into as many memory array blocks 54 as desired.
`according to the design. For example. eight blocks. nine
`blocks. or 16 blocks are rather common numbers of array
`blocks 54. In one embodiment. 32 memory array blocks 54
`are formed as shown in FIG. 1. The 32 blocks are grouped
`into four quadrants. each quadrant having eight blocks.
`There are four quadrants on the memory device 50.
`Associated with each memory may block 54 is a respec-
`tive block input/output (I/O) circuit 56 and word line drive
`circuit 58. In one embodiment. the word line drive circuit 58
`for two adjacent memory array blocks 54 is positioned in a
`single region between the two adjacent memory array
`blocks. Alternatively. the word line drive circuit 58 can be
`located in the central or peripheral regions of the memory
`device 50. Other circuitry for accessing a memory cell in the
`memory array 52. such as row and address decoders. input!
`output bufiers and sense amplifiers are located in the block
`110 circuitry 56. central regions 60 and 62 and other posi-
`tions on the memory device 50 as needed. A plurality of
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`65
`
`4
`
`bonding pads 64 are provided in the peripheral region of the
`memory device 50 for connecting to data input/output pins.
`voltage supply lines. address lines and other electrical con-
`nections as needed.
`FIGS. 2 and 3 illustrate an embodiment of a read/write
`circuit 69 and a row address circuit 105. respectively. of the
`memory device 50. Each memory array block 54 is provided
`with circuitry for providing data to and from for that
`individual block. In one embodiment. the circuitry of FIGS.
`2 and 3 will be provided for each memory array block 54 so
`that there are 32 such circuits on a single memory device 50.
`Alternatively. for that circuitry which can be shared between
`two memory array blocks 54. only 16 such circuits will be
`needed. as will be apparent to those of skill in the art. In one
`embodiment. the memory device 50 is capable of receiving
`32 bits of data simultaneously and outputting 32 bits of data
`simultaneously. Therefore. all circuitry required to input and
`output 32 bits of data simultaneously is provided. such as 32
`input/output buifers. and the like. The 32 bits can be
`provided by simultaneously accessing one memory cell in
`each of the 32 memory array blocks 54 or. alternatively. by
`accessing 8 memory cells in one memory array block within
`one quadrant and accessing four blocks one within each
`quadrant simultaneously. The circuits shown in FIGS. 2 and
`3 are thus provided for each individual block of the memory
`array 52 and can have a 1 bit bus. an 8 bit bus. a 4 bit bus
`or the like.
`
`As shown in FIG. 2. a data signal line 27 receives data and
`provides the data to a conventional data input bulfer 68. The
`data input buffer 68 outputs the data complement DC. on a
`signal line 70 and the data true DT. on a signal line 72. A
`write driver 75 receives the data from the data input buffer
`68 and outputs the data on a pair of signal lines write bit
`complement. WBC 74 and write bit true. WET 76. The data
`input buffer 68 also outputs the data to an output bufier 98
`on line 97. The signal lines WBC 74 and WBT 76 are input
`to a column select circuit 78. The column select circuit 78
`
`outputs the data on bit line complement BBC 80 and bit line
`true BLT 82 for writing to the memory array blocks 54. A
`burst counter 40 outputs column select signals 130 directly
`to the column select circuit 78 for addressing specific bit
`lines within the memory array block 54. The BLC line 80
`and BLT line 82 are connected to the memory array block 54
`as shown in FIG. 3. The WBC and WBT signal lines 74 and
`76 are also connected to a reset control circuit 84 which
`
`outputs signal lines RESET 86 and reset bar (RESET B) 88.
`The column select circuit 78 also receives additional input
`signals to control reading and writing data to and from the
`memory array block 54 as explained in more detail with
`respect to FIG. 19. A read bit complement RBC 90 and a
`read bit true RBT 92 signal are output by the column select
`circuit 78 and carry the read bit data when the circuitry of the
`memory device 50 is in the read mode. The signals RBC 90
`and RBT 92 are input to a sense amp circuit 94 which
`operates to sense read data in a manner well known in the
`art.
`
`Referring to FIG. 3. the row address circuit 105 includes
`an address decoder 107 which receives address information
`
`and outputs decoded address information to a word line and
`block select circuit 104. Additional address decode circuitry
`including an input buifer 106. an even/odd row selector 108
`and a word line select circuit 110 are part of the address
`decode circuitry. The word line select circuit 110 provides
`signals to a local word line driver circuit 112 which outputs
`signals LWLl and LWLO to drive individual word lines of
`the memory array block 54. As will be appreciated. the
`appropriate address decoder circuitry for the column address
`
`Page 25 of 38
`
`Page 25 of 38
`
`

`

`5
`
`6
`
`5,784,331
`
`is also provided so that individual memory cells are acces—
`sible. Test mode logic 114 is also provided to permit testing
`of the memory device 50.
`FIG. 4 is a schematic diagram of one embodiment of the
`address input buffer 106 of FIG. 3. The address input bufier
`106 receives the odd/even address bit on an input terminal
`600 and provides the buffered odd/even address bit on an
`output terminal 602.
`FIG. 5 is a schematic diagram of one embodiment of the
`even/odd row selector 108 of FIG. 3. A first stage 606
`includes an even number (here 4) inverters that are serially
`coupled between the address input terminal 604 and a row
`address even terminal mm. A mode selection stage 608
`has a number of mode select input terminals coupled to the
`mode terminals FONB. AOPED. AON'EO. and FOFFEO. an
`input terminal coupled to the input terminal 604. and an
`output terminal 610. The mode selection stage 608 includes
`switches 612. 614. and 616. which are coupled as shown. A
`second stage 618 includes an odd number (here 3) of
`inverters that are serially coupled between the output ter—
`rninal 610 and the row address odd terminal flow.
`In operation during a read or write cycle. the switch 612
`is conducting. thus coupling the address bit at the terminal
`604 to the stage 618. The switches 614 and 616 are non-
`conducting. If the address bit at the input terminal 604
`indicates that an even row is to be accessed. i.e.. the address
`bit is a logic 0. then the stage 606 generates an active logic
`0 for my“. and the stage 618 generates an inactive logic
`1 for R—Aodd. Thus. the addressed even row is selected. and
`all the remaining even rows and all the odd rows of memory
`cells in the memory blocks 54 are unselected. Conversely. if
`the address bit at the input terminal 604 is a logic 1 to
`indicate that an odd row is to be accessed. then the stage 606
`drives mm to an inactive logic 1. and the stage 618 drives
`flow to an active logic 0. Thus. the addressed odd row is
`selected and the remaining odd rows and all the even rows
`of memory cells in the blocks 54 are unselected.
`FIG. 6 is a schematic diagram of the word line and block
`select circuit 104 of FIG. 3. Only the portion that generates
`the mew. signal is shown. it being understood that the
`portion generating the E6044 signal is similar in construction
`and in operation. In operation.
`the circuit 104 receives
`Em" and generates mm". The circuit 104 also receives
`three block address signals BAO. BAl. and BA2 and gen-
`erates therefrom a block select signal 38. In one embodi-
`ment of the invention. there is one circuit 104 for every two
`memory blocks 54. The signals F609,, and EM, are
`common to all the memory blocks 54. and are generated by
`multiple circuits 104 in order to prevent problems such as
`excessive fan-out. Furthermore. in the embodiment of the
`memory device 50 where four (out of 32) memory blocks 54
`are accessed at a time. only eight E8 signals need be
`generated. Thus. each of these eight ITS signals are coupled
`to a corresponding memory block 54 in each of the quad—
`rants of the memory device 50.
`FIG. 7 is a schematic diagram of one embodiment of the
`word line select circuit 110 of FIG. 3. In operation. the word
`line select circuit 110 generates RDLmn from 1375",".
`mm from E6044. and BS from ES. The signals BS from
`two circuits 110 are coupled to the block read/write control
`circuit 125 (FIG. 2) as block select left ESL and block select
`right BSR. respectively.
`FIG. 8 is a schematic diagram of one embodiment of the
`local word line driver circuit 112 of FIG. 3. The circuit 112
`
`generates an active logic 1 for f—even when mm” is a
`logic 0 and MWL and ENABLE are logic 1 and 0. respec-
`
`tively. Likewise. the_circ_uit 112 generates an active logic 1
`for WE.“ when RDLodd is a logic 0 and MWL and
`ENABLE are logic 1 and 0. respectively. In one embodiment
`of the invention. each memory block 54 has 260 rows of
`memory cells and in such an embodiment there are 130 of
`the local word line driver circuits 112 per memory block 54.
`The detailed circuits for each of the blocks shown in
`FIGS. 4 to 8 can be implemented using conventional cir-
`cuitry now available for performing such functions. As will
`be appreciated. specific embodiments for such circuitry are
`shown and described in the related applications mentioned
`on page 1 of the present application. However. such detailed
`circuits do not form a part of this present invention and. for
`purposes of this invention. any currently available circuitry
`for carrying out the functions described in the blocks is
`acceptable.
`FIG. 10 is a block diagram of one embodiment of a
`pipelined column address burst counter circuit according to
`principles of the present invention. A column address input
`bulfer and master latch circuit 104 receives a column address
`101 directly from input pins of the memory device 50. The
`circuit 104 outputs the column address data on line 12
`labeled OUTC which is input to a column address driver
`106. The column address driver 106 generates true and
`complement address signals corresponding to each address
`provided on the line 12. These include the true column
`address x on line 18. labeled CAxT. and the complement
`column address It on line 16. labeled CAxC. In the present
`embodiment. x is a number from 0 to 13 because there are
`4 addresses that are decoded to selected 16 columns in a
`group. The column address signals. CAxT and CAxC. are
`input to a column predecoder 110. The true column address
`CAxT is also input on a line 28 to a burst controller 30. In
`a preferred embodiment. x=0 on the particular signal line 18
`which is provided to the burst controller 30 so that the burst
`controller receives the least significant address bit from the
`current column address from the column address driver 106.
`The burst controller 30 outputs numerous control signals on
`multiple lines. labeled 38 as a group. to control a column
`address burst counter circuit 40. The details of this imple-
`mentation of the burst controller 30 will be described in
`more detail later with respect to FIG. 21.
`The column predecoder 110 receives the signals on lines
`18 and 16 and outputs partially decoded address
`information. labeled Yx on line 22. The parn'ally decoded
`column address information Yx is input to a column address
`decoder circuit 100. The decoded column address data is
`output by the column address decoder circuit 100 on line 26
`and input to the burst counter 40. The burst counter 40
`outputs a column select signal COL. SEL. on line 130 which
`is input to the column select circuit 78. The column select
`circuit 78 shown in FIG. 10 is the same as that shown in FIG.
`2. FIG. 10 depicts the path which the column address
`follows for either writing data to or reading data from the
`memory array 52 via lines 80 and 82 also shown in FIG. 2.
`When data is read from the memory array 52. it is output on
`a read bit true (RBT) line 92 and a read bit complement
`(RBC) line 90 for sensing by a sense amp 94. As shown in
`FIG. 10. the burst controller 30 is coupled to directly receive
`the column address information CAxT from the column
`address driver 106 simultaneously with the column address
`predecoder 110 receiving such information. The burst con-
`troller 30 remains coupled to the burst counter 40 to generate
`control signals on line 38 to control the burst counter 40.
`Rather than receiving the decoded column address informa-
`tion on line 26. the burst controller 30 receives the column
`address information directly on line 28. According to a
`
`IO
`
`15
`
`2O
`
`25
`
`30
`
`35
`
`4s
`
`50
`
`55
`
`65
`
`Page 26 of 38
`
`Page 26 of 38
`
`

`

`5.784.331
`
`7
`further alternative embodiment. the burst controller 30 is
`coupled to receive the output on line 26 from the column
`decoder 100 and reencode this output to determine the
`interleaved direction in the event it is operating in the
`interleaved mode.
`
`FIG. 11 is a more detailed block diagram of another
`embodiment of the present invention. This embodiment is
`similar to that previously described with reference to FIG.
`10. In this embodiment. however. the burst controller 30 is
`coupled to the column address predecoder 110 and receives
`the first stage predecoded address information on line 22.
`The burst controller 30 in this embodiment contains an
`encoder circuit for reestablishing the original column
`address signal from the predecoded column address infor-
`mation Yx received on line 22. The burst controller 30
`
`outputs signals on line 38 to control the burst counter 40 as
`explained in more detail herein.
`The column address signal 101 is input to the column
`address input butfer and master latch circuit 104 on indi-
`vidual column address lines 98. This circuit 104 is made of
`a number of individual buffer and master latch circuits 103
`and is equivalent to the column address input butfer 104 of
`FIG. 10. The outputs of each of the circuits 103 is input to
`the column address driver circuit 106. which is made of
`individual driver circuits 105 and corresponds to the column
`address driver 106 of FIG. 10. The outputs of each of the
`column address driver circuits 105 is input to the column
`address predecoder circuit 110. which is made of individual
`predecoders 107 and is shown in block form as the column
`address predecoder 110 in FIG. 10. The outputs of each of
`the individual column address predecoders 107 is input to a
`column address decoder circuit 100. The circuit 100 includes
`
`a plurality of individual column address decoder circuits
`109. The outputs from the individual decoders 109 are
`coupled to a slave latch circuit 111 which includes a plurality
`of individual slave latches 102. The slave latch circuit 111 is
`within the burst counter 40 in FIG. 10. Each of the individual
`slave latch circuits 102 outputs one of the column select
`signals 130 from the slave latch circuit 111. Thes