Paper 1
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________
`
`
`
`QUALCOMM INCORPORATED
`
`PETITIONER
`
`
`v.
`
`
`MONTEREY RESEARCH, LLC
`
`PATENT OWNER
`
`______________
`
`INTER PARTES REVIEW NO. IPR2020-01491
`PATENT 6,534,805
`______________
`
`
`PETITION FOR INTER PARTES REVIEW UNDER 35 U.S.C. § 312
`
`
`
`

`

`IPR2020-01491
`Patent 6,534,805
`
`TABLE OF CONTENTS
`INTRODUCTION .......................................................................................... 1
`I.
`II. MANDATORY NOTICES ............................................................................ 2
`A.
`Real Party in Interest (37 C.F.R. § 42.8(b)(1)) ..................................... 2
`B.
`Related Matters (37 C.F.R. § 42.8(b)(2)) .............................................. 2
`C.
`Lead and Back-Up Counsel (37 C.F.R. § 42.8(b)(3)) ........................... 3
`D.
`Service Information (37 C.F.R. § 42.8(b)(4)) ....................................... 4
`III. GROUNDS FOR STANDING ...................................................................... 4
`IV. STATEMENT OF PRECISE RELIEF REQUESTED FOR EACH CLAIM
`CHALLENGED ............................................................................................. 5
`A.
`Claims for Which Review Is Requested (37 C.F.R. § 42.104(b)(1)).... 5
`B.
`Statutory Grounds of Challenge (37 C.F.R. § 42.104(b)(2)) ................ 5
`THE GROUNDS IN THIS PETITION ARE NOT CUMULATIVE ............ 6
`V.
`VI. OVERVIEW OF THE ’805 PATENT ........................................................... 8
`A. Overview of the ’805 Patent .................................................................. 8
`B.
`Prosecution History .............................................................................10
`C.
`Ex Parte Reexamination ......................................................................11
`D.
`Level of Ordinary Skill in the Art .......................................................12
`VII. CLAIM CONSTRUCTION .........................................................................12
`A.
`“Substantially Oblong” .......................................................................13
`VIII. SPECIFIC EXPLANATION OF GROUNDS .............................................15
`A. Ground 1A: Oh Renders Claims 8-14, 16-20, 22-25, 27-28, and 30-32
`Obvious................................................................................................15
`Oh ..............................................................................................15
`1.
`Element-by-element analysis ....................................................19
`2.
`Ground 1B: Oh in view of CMOS Circuit Design Renders Claims 8-
`14, 16-20, 22-25, 27-28, and 30-32 Obvious ......................................70
`CMOS Circuit Design Overview ...............................................70
`1.
`2. Motivation to combine ..............................................................72
`3. Modification of Oh in view of CMOS Circuit Design...............74
`
`B.
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`C.
`
`E.
`
`F.
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`IPR2020-01491
`Patent 6,534,805
`Element-by-element analysis ....................................................75
`4.
`Ground 2A: Oh in Combination with Lee Renders Claims 7, 15, 21,
`26, 29, and 58 Obvious ........................................................................77
`Dual Damascene processes ......................................................77
`1.
`2. Motivation to modify Oh in view of Lee to implement dual
`damascene .................................................................................81
`3. Modification of Oh in view of Lee ............................................83
`Element-by-element analysis ....................................................86
`4.
`D. Ground 2B: Oh in Combination with Lee and CMOS Circuit Design
`Renders Claims 7, 15, 21, 26, 29, and 58 Obvious .............................92
`Ground 3A: Oh in Combination with Nii Renders Claims 53-57, 59-
`61 Obvious ..........................................................................................92
`SRAM Cell Signal and Power Lines .........................................92
`1.
`2. Motivation to modify Oh in view of Nii ...................................101
`3. Modification of Oh in view of Nii ...........................................103
`Element-by-element analysis ..................................................109
`4.
`Ground 3B: Oh in Combination with Nii and CMOS Circuit Design
`Renders Claims 53-57, 59-61 Obvious .............................................114
`G. Ground 4A: Oh in Combination with Nii and Lee Renders Claim 58
`Obvious..............................................................................................114
`Oh modified by Nii and Lee ....................................................114
`1.
`Element-by-element analysis ..................................................115
`2.
`H. Ground 4B: Oh in Combination with Nii, Lee, and CMOS Circuit
`Design Renders Claim 58 Obvious ...................................................115
`Grounds 5A-5B, 6A-6B: Oh in Combination with Hara, CMOS
`Circuit Design, and Lee Renders Claims 53-61 Obvious .................116
`IX. CONCLUSION ..........................................................................................117
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`I.
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`Petitioner’s Exhibit List
`
`IPR2020-01491
`Patent 6,534,805
`
`1001
`
`1002
`1003
`1004
`
`1005
`
`1006
`1007
`
`Exhibit No. Description
`U.S. Patent No. 6,534,805 (with Ex Parte Reexamination
`Certificate Appended)
`Omitted
`Omitted
`U.S. Patent No. 6,417,549 (“Oh”)
`R. Jacob Baker et al., CMOS Circuit Design, Layout And
`Simulation, IEEE Press (1998) (“CMOS Circuit Design”)
`Prosecution History for U.S. Patent Application No. 09/829,510
`Ex Parte Reexamination History for U.S. Patent No. 6,534,805
`Ishida, et al., “A Novel 6T-SRAM Cell Technology Designed with
`Rectangular Patterns Scalable beyond 0.18 μm Generation and
`Desirable for Ultra High Speed Operation,” IEDM 98, IEEE 1998,
`pp. 201-204 (“Ishida IEDM”)
`U.S. Patent No. 6,677,649 (“Osada”)
`Certain Static Random Access Memories and Products Containing
`the Same, USITC Inv. No. 337-TA-792, Order 29 (Feb. 9, 2012)
`Omitted
`Omitted
`Omitted
`Omitted
`Omitted
`Omitted
`Omitted
`Omitted
`Declaration of Dr. Jack Lee
`U.S. Patent No. 5,702,982 (“Lee”)
`U.S. Patent No. 6,347,062 (“Nii”)
`Dr. Jack Lee CV
`
`1008
`
`1009
`
`1010
`
`1011
`1012
`1013
`1014
`1015
`1016
`1017
`1018
`1019
`1020
`1021
`1022
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`IPR2020-01491
`Patent 6,534,805
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`1024
`
`1025
`
`1026
`
`1027
`
`Exhibit No. Description
`1023
`U.S. Patent No. 5,930,163 (“Hara”)
`Ben G. Streetman et al., Solid State Electronic Devices, Prentice
`Hall (5th ed. 2000) (“Streetman”)
`U.S. Patent No. 6,399,511 (“Tang”)
`Basic Integrated Circuit Technology Reference Manual (1993)
`(“Bowman”)
`U.S. Patent No. 4,584,027 (“Metz”)
`Declaration of Dr. Sylvia Hall-Ellis re CMOS Circuit Design
`(EX1005)
`U.S. Pat. No. 4,795,716 (“Yilmaz”)
`U.S. Pat. No. 4,574,467 (“Halfacre”)
`Petition for Inter Partes Review, IPR2020-00990, Paper 1
`(“AMD IPR Petition”)
`
`1028
`
`1029
`1030
`
`1031
`
`
`
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`
`
`Claim Limitation
`No.
`[1Pre]
`
`1
`
`2
`
`4
`
`5
`
`7
`
`8
`
`[1A]
`
`[1A-1]
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`1A-2]
`
`[2]
`
`[4A]
`
`[4A-1]
`
`[5A]
`
`[5A-1]
`
`[7]
`
`[8Pre]
`
`[8A]
`
`[8B]
`
`IPR2020-01491
`Patent 6,534,805
`
`Claim Listing
`
`Limitation
`A memory cell comprising
`a series of four substantially oblong active regions formed
`within a semiconductor substrate and arranged side-by-side
`with long axes substantially parallel
`wherein each of the inner active regions of the series
`comprises a pair of source/drain regions for a respective p-
`channel transistor
`wherein … each of the outer active regions of the series
`comprises a pair of source/drain regions for a respective n-
`channel transistor
`The memory cell as recited in claim 1, further comprising a
`plurality of substantially oblong polysilicon structures
`arranged above and substantially perpendicular to the active
`regions
`The memory cell as recited in claim 2, further comprising
`source/drain contacts to the source/drain regions of transistors
`wherein at least one of the source/drain contacts comprises a
`shared contact to one of the inner active regions and one of the
`polysilicon structures
`The memory cell as recited in claim 4, further comprising a
`series of substantially oblong local interconnects arranged
`substantially perpendicular to the active regions
`wherein the shared contact is connected to another of the
`source/drain contacts by one of the local interconnects.
`The memory cell as recited in claim 5, wherein the local
`interconnects have an upper surface that is substantially
`coplanar with an upper surface of the source/drain contacts.
`A memory cell comprising
`a plurality of substantially oblong active regions formed in a
`semiconductor substrate and arranged substantially in parallel
`with one another
`a plurality of substantially oblong local interconnects above
`said substrate that extend only partially across the memory cell
`and are arranged substantially in parallel with one another and
`substantially perpendicular to said active regions
`
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`
`
`Claim Limitation
`No.
`[8C]
`
`IPR2020-01491
`Patent 6,534,805
`
`Limitation
`a single local interconnect layer comprising local
`interconnects corresponding to bitlines and a global wordline
`The memory cell as recited in 8, further comprising
`substantially square local interconnects above said substrate,
`wherein all local interconnects within the cell are either
`substantially oblong or substantially square.
`The memory cell as recited in claim 8, further comprising a
`shared contact to one of the active regions and a polysilicon
`structure,
`wherein the polysilicon structure is arranged substantially
`perpendicular to said active region and a portion of the
`polysilicon structure abuts a portion of said active region
`the memory cell of claim 8, wherein each local interconnect of
`the single local interconnect layer is substantially oblong.
`the memory cell of claim 8, the single local interconnect layer
`comprising local interconnects corresponding to common
`power and common ground
`The memory cell of claim 12, wherein each local interconnect
`of the single local interconnect layer is substantially oblong
`The memory cell of claim 8, comprising: a first contact to one
`of the substantially oblong active regions;
`a shared contact to another one of the substantially oblong
`active regions and a polysilicon structure,
`a first substantially oblong local interconnect that connects the
`[14C]
`first contact and the shared contact,
`[14C-1] wherein the single local interconnect layer comprises the first
`substantially oblong local interconnect.
`[15Pre]
`The memory cell of claim 8, comprising:
`[15A]
`a first contact to one of the substantially oblong active regions
`a shared contact to another one of the substantially oblong
`[15B]
`active regions and a polysilicon structure
`a first substantially oblong local interconnect that connects the
`first contact and the shared contact
`wherein the first substantially oblong local interconnect is
`formed from a trench opening as a contact to one of the
`substantially oblong active regions
`[16Pre] A memory cell comprising
`
`[9]
`
`[10A]
`
`[10A-1]
`
`[11]
`
`[12]
`
`[13]
`
`[14A]
`
`[14B]
`
`[15C]
`
`[15C-1]
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`9
`
`10
`
`11
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`12
`
`13
`
`14
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`15
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`16
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`
`
`Claim Limitation
`No.
`
`[16A]
`
`IPR2020-01491
`Patent 6,534,805
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`Limitation
`a series of four substantially oblong active regions formed
`within a semiconductor substrate and arranged side-by-side
`with long axes substantially parallel
`[16A-1] wherein each inner active region of the series comprises a pair
`of source/drain regions for a respective p-channel transistor
`[16A-2] wherein each outer active region of the series comprises a pair
`of source/drain regions for a respective n-channel transistor
`a single local interconnect layer comprising local
`interconnects corresponding to bitlines and a global wordline
`The memory cell of claim 16, wherein each local interconnect
`of the single local interconnect layer is substantially oblong.
`The memory cell of claim 16, the single local interconnect
`layer comprising local interconnects corresponding to
`common power and common ground
`The memory cell of claim 18, wherein each local interconnect
`of the single local interconnect layer is substantially oblong
`The memory cell of claim 16, comprising a first contact to one
`of the outer active regions
`a shared contact to one of the inner active regions and a
`polysilicon structure
`a first substantially oblong local interconnect that connects the
`[20C]
`first contact and the shared contact
`[20C-1] wherein the single local interconnect layer comprises the first
`substantially oblong local interconnect
`The memory cell of claim 16, comprising: a first contact to
`one of the outer active regions
`a shared contact to one of the inner active regions and a
`polysilicon structure
`a first substantially oblong local interconnect that connects the
`first contact and the shared contact
`wherein the first substantially oblong local interconnect is
`formed from a trench opening as a contact to one of the active
`regions
`The memory cell of claim 16, comprising a plurality of
`substantially oblong polysilicon structures arranged above and
`substantially perpendicular to the active regions
`
`[16B]
`
`[17]
`
`[18]
`
`[19]
`
`[20A]
`
`[20B]
`
`[21A]
`
`[21B]
`
`[21C]
`
`[21C-1]
`
`[22A]
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`
`
`Claim Limitation
`No.
`[23A]
`
`IPR2020-01491
`Patent 6,534,805
`
`[23A-1]
`
`[24A]
`
`[24A-1]
`
`[25]
`
`[26]
`
`[27A]
`
`Limitation
`The memory cell of claim 16, comprising source/drain
`contacts to the source/drain regions of transistors
`wherein at least one of the source/drain contacts comprises a
`shared contact to one of the inner active regions and one of the
`polysilicon structures
`The memory cell of claim 23, comprising a series of
`substantially oblong local interconnects arranged substantially
`perpendicular to the active regions
`wherein the shared contact is connected to another of the
`source/drain contacts by one of the substantially oblong local
`interconnects
`The memory cell of claim 24, wherein the substantially oblong
`local interconnects are dielectrically spaced above the
`semiconductor substrate
`The memory cell of claim 24, wherein the substantially oblong
`local interconnects have an upper surface that is substantially
`coplanar with an upper surface of the source/drain contacts
`[27Pre] A memory cell, comprising:
`a series of four substantially oblong active regions formed
`within a semiconductor substrate and arranged side-by-side
`with long axes substantially parallel
`[27A-1] wherein each inner active region of the series comprises a pair
`of source/drain regions for a respective p-channel transistor
`[27A-2] wherein each outer active region of the series comprises a pair
`of source/drain regions for a respective n-channel transistor
`[27B]
`a first contact to one of the outer active regions
`a shared contact to both a polysilicon structure and to one of
`[27C]
`the inner active regions
`a substantially oblong local interconnect that connects the first
`contact and the shared contact
`wherein the substantially oblong local interconnect overlaps
`both the poly silicon structure and said one of the inner active
`regions
`The memory cell of claim 27, wherein the substantially oblong
`local interconnect is dielectrically spaced above the
`semiconductor substrate
`
`
`23
`
`24
`
`25
`
`26
`
`27
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`28
`
`[27D]
`
`[27D-1]
`
`[28]
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`IPR2020-01491
`Patent 6,534,805
`
`
`
`[29A-1]
`
`29
`
`[29C-1]
`
`Claim Limitation
`Limitation
`No.
`[29Pre] A memory cell, comprising:
`wherein each inner active region of the series comprises a pair
`of source/drain regions for a respective p-channel transistor,
`and
`[29A-2] wherein each outer active region of the series comprises a pair
`of source/drain regions for a respective n-channel transistor
`[29B]
`a first contact to one of the outer active regions
`[29C]
`source/drain contacts to the source/drain regions of transistors
`wherein at least one of the source/drain contacts comprises a
`shared contact to both a polysilicon structure and to one of the
`inner active regions
`a substantially oblong local interconnect that connects the first
`contact and the shared contact
`wherein the substantially oblong local interconnect overlaps
`both the poly silicon structure and said one of the inner active
`regions, and
`wherein the substantially oblong local interconnect has an
`upper surface that is substantially coplanar with an upper
`surface of the source/drain contacts
`[30Pre] A memory cell, comprising:
`a plurality of substantially oblong active regions formed in a
`semiconductor substrate and arranged substantially in parallel
`with one another
`a plurality of substantially oblong local interconnects above
`said substrate that extend partially across the memory cell and
`are arranged substantially in parallel with one another and
`substantially perpendicular to the active regions
`a first contact to one of the active regions
`a shared contact to both a polysilicon structure and to another
`one of the active regions; and
`a substantially oblong local interconnect that connects the first
`contact and the shared contact
`wherein the substantially oblong local interconnect overlaps
`both the polysilicon structure and said another one of the
`active regions
`
`[29D]
`
`[29D-1]
`
`[29D-2]
`
`[30A]
`
`[30B]
`
`[30C]
`[30D]
`
`[30E]
`
`[30E-1]
`
`30
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`
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`Claim Limitation
`No.
`
`IPR2020-01491
`Patent 6,534,805
`
`Limitation
`The memory cell of claim 30, comprising: substantially square
`local interconnects above the substrate, wherein local
`interconnects within the cell are one of substantially oblong
`and substantially square
`the memory cell of claim 30, wherein the polysilicon structure
`is arranged substantially perpendicular to said another one of
`the active regions, and wherein a portion of the polysilicon
`structure abuts a portion of the said another one of the active
`regions
`[53Pre] A memory cell, comprising
`a series of four substantially oblong active regions formed
`[53A]
`within a semiconductor substrate and arranged side-by-side
`with long axes substantially parallel
`[53A-1] wherein each inner active region of the series comprises a pair
`of source/drain regions for a respective p-channel transistor
`[53A-2] wherein each outer active region of the series comprises a pair
`of source/drain regions for a respective n-channel transistor
`a first metal layer above the semiconductor substrate, wherein
`the first metal layer contacts bitlines, common power, and
`common ground globally across a plurality of memory cells;
`and
`a second metal layer above the first metal layer, wherein the
`second metal layer is configured as a global wordline
`The memory cell of claim 53, comprising: a plurality of
`substantially oblong polysilicon structures arranged above and
`substantially perpendicular to the active regions
`The memory cell of claim 54, comprising: source/drain
`contacts to the source/drain regions of transistors, wherein at
`least one of the source/drain contacts comprises a shared
`contact to one of the inner active regions and one of the
`polysilicon structures
`wherein at least one of the source/drain contacts comprises a
`shared contact to one of the inner active regions and one of the
`polysilicon structures
`
`
`[31]
`
`[32]
`
`[53B]
`
`[53C]
`
`[54]
`
`[55A]
`
`31
`
`32
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`53
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`54
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`55
`
`[55A-1]
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`
`
`Claim Limitation
`No.
`
`IPR2020-01491
`Patent 6,534,805
`
`Limitation
`The memory cell of claim 55, comprising: “a series of
`substantially oblong local interconnects arranged substantially
`perpendicular to the active regions
`[56A-1] wherein the shared contact is connected to another of the
`source/drain contacts by one of the local interconnects
`The memory cell of claim 56, wherein the local interconnects
`are dielectrically spaced above the semiconductor substrate
`The Memory Cell Of Claim 56, wherein The Substantially
`Oblong Local Interconnects Have An Upper Surface That Is
`Substantially Coplanar With An Upper Surface Of The
`Source/Drain Contacts
`[59Pre] A memory cell, comprising
`a plurality of substantially oblong active regions formed in a
`semiconductor substrate and arranged substantially in parallel
`with one another
`a plurality of substantially oblong local interconnects above
`the substrate and extending partially across the memory cell
`and are arranged substantially in parallel with one another and
`substantially perpendicular to the active regions
`a first metal layer above the semiconductor substrate, wherein
`the first metal layer contacts bitlines, common power, and
`common ground globally across a plurality of memory cells;
`and
`a second metal layer above the first metal layer, wherein the
`second metal layer is configured as a global wordline
`the memory cell of claim 59, comprising: substantially square
`local interconnects above the substrate, wherein local
`interconnects within the cell are one of substantially oblong
`and substantially square
`The memory cell of claim 59, comprising: a shared contact to
`one of the active regions and a polysilicon structure, wherein
`the polysilicon structure is arranged substantially
`perpendicular to the active region, and wherein a portion of
`the polysilicon structure abuts a portion of the active region
`
`[56A]
`
`[57]
`
`[58]
`
`[59A]
`
`[59B]
`
`[59C]
`
`[59D]
`
`[60]
`
`[61]
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`56
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`57
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`58
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`59
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`60
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`61
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`IPR2020-01491
`Patent 6,534,805
`
`I.
`
`INTRODUCTION
`The ’805 Patent previously underwent ex parte reexamination in which no
`
`challenged original claims survived without amendment. EX1007. While the
`
`Examiner allowed amended and new claims to issue, the reasoning for those
`
`allowances are not applicable to and do not overcome the art cited in this Petition.
`
`First, Patentee amended several claims to include “a single local interconnect
`
`layer comprising local interconnects corresponding to bitlines and a global
`
`wordline,” and obtained allowance on that basis. Id., 1057-58/1439, 1090-91/1439.
`
`Unlike the art at issue in the reexamination, Oh discloses this. See §§VIII.A-VIII.B.
`
`Next, the Examiner concluded that the art of record did not disclose local
`
`interconnects “having an upper surface that is substantially coplanar with an upper
`
`surface of the source/drain contact.” EX1007, 1014/1439. But this language is met
`
`through use of the well-known and advantageous damascene process. Thus, the
`
`Ground 2 claims are obvious over Oh in view of Lee. See §§VIII.C-VIII.D.
`
`Finally, Patentee argued that the ’805 Patent’s “wordline on top of bitlines”
`
`arrangement was patentable over art showing “the reverse order of bitlines on top of
`
`wordlines,” and obtained allowance on that basis. EX1007, 502/1439, 1014/1439.
`
`However, Nii discloses this known and advantageous configuration. Thus, the
`
`Ground 3 and 4 claims are obvious over Oh in view of Nii. See §§VIII.E-VIII.H.
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`100790905.9
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`

`IPR2020-01491
`Patent 6,534,805
`
`II. MANDATORY NOTICES
`A. Real Party in Interest (§42.8(b)(1))
`The real parties-in-interest are Qualcomm Incorporated, Qualcomm
`
`Technologies, Inc., and Qualcomm CDMA Technologies Asia-Pacific Pte Ltd.
`
`B. Related Matters (§42.8(b)(2))
`(1) Monterey Research, LLC v. Qualcomm Inc. et al., Civil Action No.
`
`1:19-cv-02083 (D. Del. 2019), which involves the ’805 Patent.
`
`(2) Monterey Research, LLC v. Advanced Micro Devices, Inc., No. 1:19-
`
`cv-02149 (D. Del.), which involves the ’805 Patent.
`
`(3) Monterey Research, LLC v. Nanya Technology Corp. et al., Civil
`
`Action No. 1:19-cv-02090 (D. Del. 2019), which involves the ’805 Patent.
`
`(4) Monterey Research, LLC v. STMicroelectronics N.V., No. 1:20-cv-
`
`00089 (D. Del. 2019), which involves the ’805 Patent.
`
`(5) Monterey Research, LLC v Marvell Tech. Grp. Ltd., No. 1:20-cv-00158
`
`(D. Del.), which involves the ’805 Patent.
`
`(6) Marvell Semiconductor, Inc. v. Monterey Research, LLC, No. 3:20-cv-
`
`03296 (N.D. Cal. 2020), which involves the ’805 Patent.
`
`(7) The ’805 Patent was previously asserted before the International Trade
`
`Commission by Patent Owner’s predecessor-in-interest in In the Matter of Certain
`
`Static Random Access Memories and Products Containing the Same, Inv. No. 337-
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`IPR2020-01491
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`TA-792 (U.S.I.T.C.) and in district court in Cypress Semiconductor Corp. v. GSI
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`Technology, Inc., No. 3:13-cv-03757-JST (N.D. Cal.).
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`(8) The ’805 Patent was also previously before the Board in Appeal No.
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`2014-002896. See, e.g., EX1007, 1322-31/1439.
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`(9) The ’805 Patent is also the subject of IPR2020-00990.
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`C. Lead and Back-Up Counsel (§42.8(b)(3))
`
`Back-Up Counsel
`Lead Counsel
`Eagle H. Robinson (Reg. No. 61,361) Daniel S. Leventhal (Reg. No. 59,576)
`Richard S. Zembek (Reg. No. 43,306)
`Hao Wu (Reg. No. 75,926)
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`IPR2020-01491
`Patent 6,534,805
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`D.
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`Service Information (§42.8(b)(4))
`Lead Counsel
`Eagle H. Robinson
`Norton Rose Fulbright US LLP
`98 San Jacinto Boulevard, Suite 1100
`Austin, Texas 78701
`512.536.3083 (telephone)
`512.536.4598 (facsimile)
`eagle.robinson@nortonrosefulbright.com
`
`
`Back-Up Counsel
`Daniel S. Leventhal
`Richard S. Zembek
`Norton Rose Fulbright US LLP
`Fulbright Tower
`1301 McKinney, Suite 5100
`Houston, TX 77010-3095
`713.651.5151 (telephone)
`713.651.5246 (facsimile)
`daniel.leventhal@nortonrosefulbright.com
`richard.zembek@nortonrosefulbright.com
`
`Hao Wu
`Norton Rose Fulbright US LLP
`2200 Ross Avenue, Suite 3600
`Dallas, Texas 75201-7932
`214.855.8000 (telephone)
`214.855.8200 (facsimile)
`hao.wu@nortonrosefulbright.com
`
`Petitioner consents to electronic service.
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`III. GROUNDS FOR STANDING
`Pursuant to §42.104(a), Petitioner certifies that the ’805 Patent is available for
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`IPR, and that Petitioner is not barred or estopped from requesting an IPR on the
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`grounds identified in this Petition. The ’805 Patent has not been subject to a previous
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`final written decision in an estoppel-based AIA proceeding.
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`IPR2020-01491
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`IV. STATEMENT OF PRECISE RELIEF REQUESTED FOR EACH
`CLAIM CHALLENGED
`A. Claims for Which Review Is Requested (§42.104(b)(1))
`Petitioner requests review and cancellation of Claims 7-32 and 53-61.
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`Statutory Grounds of Challenge (§42.104(b)(2))
`B.
`Grounds 1A & 1B: Claims 8-14, 16-20, 22-25, 27-28, and 30-32 are obvious
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`over Oh (EX1004) (Ground 1A), and Oh in view of CMOS Circuit Design (EX1005)
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`(Ground 1B). Filed on September 13, 2000, Oh is prior art under §102(e). CMOS
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`Circuit Design was published in 1997 and was publicly available by at least 1998,
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`qualifying as prior art under at least §§102(a), (b). EX1005; EX1028, ¶¶1-51.
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`Ground 2A & 2B: Claims 7, 15, 21, 26, 29, 58 are obvious over Oh in view
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`of Lee (EX1020) (Ground 2A), and further in view of CMOS Circuit Design
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`(Ground 2B). Issued on December 30, 1997, Lee is prior art under at least §102(b).
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`Grounds 3A & 3B: Claims 53-57, 59-61 are obvious over Oh in view of Nii
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`(EX1021) (Ground 3A), and further in view of CMOS Circuit Design (Ground 3B).
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`Filed April 3, 2001, Nii is prior art under §102(e).
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`Grounds 4A & 4B: Claim 58 is obvious over Oh in view of Nii and Lee
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`(Ground 4A), and further in view of CMOS Circuit Design (Ground 4B).
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`Grounds 5A and 5B: To the extent Monterey seeks to antedate Nii, Claims
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`53-57, 59-61 are obvious over Oh in view of Hara (EX1023) (Ground 5A), and
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`further in view of CMOS Circuit Design (Ground 5B). Issued on July 27, 1999,
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`Hara is prior art under §102(b).
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`Grounds 6A and 6B: To the extent Monterey seeks to antedate Nii, Claim 58
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`is obvious over Oh in view of Hara and Lee (Ground 6A) and further in view of with
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`CMOS Circuit Design (Ground 6B).
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`V. THE GROUNDS IN THIS PETITION ARE NOT CUMULATIVE
`The Grounds in this Petition are not cumulative over the grounds in IPR2020-
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`00990 because this Petition challenges 30 additional claims beyond the seven
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`addressed in IPR2020-00990.1 Additionally, for the seven overlapping challenged
`
`claims, this Petition provides additional bases for mapping the art to the challenged
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`claims based on: (1) reliance on additional proposed claim constructions, and (2)
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`reliance on Oh’s “second embodiment.” IPR2020-00990 does not propose
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`construction for the term “substantially oblong,” noting that construction was not
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`necessary under the mappings presented. EX1031, 18. This Petition explicitly
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`construes “substantially oblong” and, applying that construction, presents additional
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`mappings to Oh not raised in IPR2020-00990.
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`1 For the Board’s convenience, common exhibits are given the same exhibit numbers
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`and paginations.
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`The Grounds in this Petition are also not cumulative over the prior
`
`reexamination. Oh, CMOS Circuit Design, Lee, and Nii were not before the
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`Examiner or the Board during prosecution or ex parte reexamination of the ’805
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`Patent. EX1006; EX1007. And, Oh is not cumulative of the art previously
`
`considered. For example, in the reexamination, Patentee amended claims to recite a
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`single local interconnect layer comprising local interconnects corresponding to
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`bitlines and a global wordline to distinguish Osada. EX1007, 1052-53/1439. Oh
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`Figure 5 is different than Osada and discloses this element—in fact, closely
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`resembling ’805 Patent Figure 3. See §VIII.A.
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`For the “first” and “second” metal layers recited in independent Claims 53
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`and 59, this Petition relies on the combination of Oh and Nii, which were not before
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`the Examiner. To the extent Monterey seeks to antedate Nii, this Petition relies on
`
`the combination of Oh and Hara. Hara was before the Examiner in the
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`reexamination, but no rejections for these claims were issued, and the Examiner
`
`provided no specific analysis of Hara. EX1007, 502/1439 (Patentee distinguishing
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`a different reference, Osada), 1014/1439. To the extent the Examiner considered
`
`Hara in accepting Patentee’s argument that the ’805 Patent’s “wordline on top of
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`bitlines” design was patentable, the Examiner erred; Hara discloses a “word line
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`WL” in “metal wiring layer 3” on top of “bit lines BL and /BL” in “metal wiring
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`layers 2” design in multiple embodiments. EX1023, 6:51-56, Figs. 2, 5, 8.
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`VI. THE ’805 PATENT
`A. Overview
`The ’805 Patent discloses an SRAM cell design. EX1001, 1:7-10. Figure 2
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`illustrates [yellow] active regions serving as the source, drain, and channel of six
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`transistors and [purple] polysilicon structures serving as the gates of the six
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`transistors as well as local interconnects. Id., Abstract, 3:35-37, 6:17-30, 6:53-64.
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`
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`“NMOS transistors 1-4 are formed within active regions 21 and 24, and
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`PMOS transistors 5 and 6 are formed within active regions 22 and 23.” Id., 6:26-
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`29. The patent describes the shape of the active regions as “substantially oblong” in
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`contrast to “the markedly ‘L-shaped’ regions formed in layouts for which two
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`transistors are arranged at right angles to each other.” Id., 7:31-34. Likewise, the
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`patent describes the shape of the polysilicon structures as “substantially oblong.”
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`Id., 10:64-11:10.
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`The SRAM cell also includes, shown in both Figures 2 and 3, [blue] contacts
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`“formed through a dielectric material arranged above the topography of the features
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`shown in FIG. 2,” including “contact regions 31-34” that connect upward to an
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`interconnect layer and are “used for the local interconnections of gates and drains,”
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`and contacts 13c6, 13c5, 14c3, 14c2, 16c, 15c, 17c1, 17c4 that connect upward to
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`an interconnect layer to ultimately couple to bitlines, global wordline, VSS (ground),
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`and VCC (power). Id., 10:44-46, 13:10-33.
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`
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`“FIG. 3 illustrates a local interconnect layer” having [green] local
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`
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`interconnects 35-44. Id., 11:50-51. The patent states that “local interconnect layer”
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`refers to “a distinct process layer that exclusively performs such short connections,”
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`while other layers