Basic Integrated Circuit
`Technology Reference
`Manual
`
`e m i c o nductorIn
`
`dustr y
`
`®
`
`S
`
`i n c e 1964
`
`bal S
`
`rvingtheGlo
`
`e
`
`S
`
`Editor:
`Richard D. Skinner
`
`ICE Staff Contributors:
`Ron Bowman
`Jim Griffin
`Bill McClean
`
`Introduction
`
`Section 1. Products
`
`Section 2. Basic Integrated
`Circuit Manufacturing
`
`Section 3. Packaging
`
`Seciton 4. Terms by Major
`Area of Interest
`
`Glossary
`
`Qualcomm Incorporated
`EX1026
`Page 1 of 19
`
`

`

`Basic Integrated Circuit
`Technology Reference
`Manual
`
`e m i c o nductorIn
`
`dustr y
`
`®
`
`S
`
`i n c e 1964
`
`bal S
`
`rvingtheGlo
`
`e
`
`S
`
`Editor:
`Richard D. Skinner
`
`ICE Staff Contributors:
`Ron Bowman
`Jim Griffin
`Bill McClean
`
`Introduction
`
`Section 1. Products
`
`Section 2. Basic Integrated
`Circuit Manufacturing
`
`Section 3. Packaging
`
`Seciton 4. Terms by Major
`Area of Interest
`
`Glossary
`
`Page 1 of 19
`
`

`

`ISBN 1-877750-24-7
`
`Copyright © 1993 by Integrated Circuit Engineering Corporation
`
`All rights reserved. No material contained in this report may be
`reproduced in whole or in part without the written permission of the
`publisher.
`
`Page 2 of 19
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`

`

`Basic Integrated Circuit Manufacturing
`
`b. Photomasks
`
`The photomask is created by a series of additional process steps beyond the making of a 10X ret-
`icle for each layer. Refer to Figure 2-20. At the contact print to submaster stage the mask polarity
`must be determined (depends on whether negative or positive photoresist is used). The submas-
`ter to working print stage can print either emulsion or chrome on glass substrates. The choice is
`determined by the wafer alignment equipment. A photomask is shown in Figure 2-17.
`
`c. E-beam
`
`Also shown in Figure 2-20 are two other alternative technologies to form the designer's require-
`ments into a photoresist layer on the silicon wafer. One alternative is to use an e-beam system to
`write the pattern directly on the photoresist-coated wafer. This approach eliminates the reticles or
`mask-making stage but has a very slow throughput.
`
`d. X-ray
`
`The other technique uses x-ray energy to expose the photoresist-coated wafer. The mask for this
`technique is very expensive and difficult to manufacture. However, x-ray steppers have excellent
`resolution capability and will probably be needed by the end of the 1990's.
`
`4. Photolithography Sequence
`
`Figure 2-21 illustrates the manufacturing sequence for photolithography. These photolitho-
`graphic steps encompass all of the patterning operations, including wafer priming, coating, align,
`expose, develop, etch, and photoresist removal. The characteristics of the light-sensitive photore-
`sists determine the basic process technique. As was shown in Figure 2-16, the photolithographic
`process is repeated several times. Because of this it is often referred to as the hub of the IC fabri-
`cation process.
`
`a. Photoresist, Negative and Positive
`
`There are two kinds of photoresist commonly used: negative and positive. The chemical behav-
`ior of each resist is illustrated in Figure 2-22. The negative resist responds to the radiation (UV
`light) in a manner that prevents the developer solution from removing the exposed resist. The
`image formed in the resist is the same as the clear area on the mask. The unexposed resist is
`removed by the developing process. Positive photoresist has the opposite response to the radia-
`tion. The areas of the photoresist that are exposed are removed by the developer solution. Thus,
`the unexposed resist remains and forms the image on the surface of the wafer.
`
`The chemistries of positive and negative photoresist are very different. Positive photoresist is
`developed with a mild alkaline (basic) solution and the negative resist requires a solvent (xylene)
`for developing.
`
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`Basic Integrated Circuit Manufacturing
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`Photoresist
`
`Wafers
`
`Vapor Prime
`and Bake
`
`Coating
`
`Class 1 - 100, "Gold Lighted" Area
`(Yellow Room)
`
`Inspected
`Masks or
`Reticle
`
`Develop
`Inspect
`(A.D.I.)
`
`Develop
`
`Wafer
`Alignment
`And Exposure
`
`Dry and
`Cure Bake
`(Soft Bake)
`
`Hard Bake
`
`Etch
`
`Etch Inspect
`(A.E.I.)
`
`Photoresist
`Strip And
`Clean
`
`1146E
`
`Figure 2-21. Photolithography Process Flow Chart
`
`i. Exposure Wavelengths
`
`A portion of the electromagnetic spectrum is illustrated in Figure 2-23. The blue-violet region is
`referred to as the ultraviolet wavelengths. Also shown is the relationship between wavelength (l)
`and the frequency (f) for this form of energy.
`
`The light-sensitive responses of both resists are similar in that both are exposed by light in the
`blue-violet wavelength (190 - 450nm). These wavelengths are commonly found in mercury arc
`lamps and similar bulbs. For this reason, the process area for photoresist must have these wave-
`lengths filtered out during manufacturing to prevent unwanted exposure. Yellow filters or lights
`are used to illuminate the work area for these processing steps.
`
`2-22
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`Basic Integrated Circuit Manufacturing
`
`Exposing Radiation
`
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`
`Mask
`
`Irradiation
`Region
`
`Resist
`Thin Film
`
`Substrate
`
`Actinic: The property of radiant energy, especially in
`the visible and ultra-violet spectral regions,
`by which chemical changes are produced.
`
`Developing
`
`Positive Resist
`
`Resist
`
`Negative Resist
`
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`
`Etching and Stripping
`
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
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`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
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`(cid:0)(cid:0)(cid:0)(cid:0)
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`(cid:0)(cid:0)(cid:0)(cid:0)
`
`Source: ICE
`
`7417A
`
`Figure 2-22. Characteristic of Negative and Positive Resists
`
`1013
`
`1014
`
`Frequencies
`1015
`1016
`
`1017
`
`1018
`
`Ultraviolet
`
`X-Rays
`
`Visible Light
`
`Region
`
`Infrared
`
`10–2
`100µ
`
`10–3
`10µ
`
`10–4
`1µ
`
`10–5
`0.1µ
`Wavelength (in cm)
`
`10–6
`0.01µ
`
`10–7
`0.001µ
`
`10–8
`0.0001µ
`
`18069B
`
`Figure 2-23. Part of the Electromagnetic Spectrum
`
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`Basic Integrated Circuit Manufacturing
`
`vi. Inspection After Develop
`
`Visual inspection of the photoresist-patterned surface is a difficult task. And, as the circuitry
`becomes denser, the inspection after develop (ADI) will become even more difficult. Therefore,
`the photoresist process will rely more on Statistical Process Control and less on the visual inspec-
`tion.
`
`The current trend in technology for monitoring the develop process after developing is to use pro-
`grammed pattern recognition visual inspection equipment. This type of automation eliminates
`the eye fatigue problem and provides more consistent results. The automated visual inspection
`station sample inspects using a statistical plan. This provides immediate feedback for manufac-
`turing control and aids in keeping the rework rate low.
`
`The decision to rework a wafer (or wafers) after the develop inspection has a significant impact
`on the cycletime of the overall process. Good manufacturing practices dictate keeping reworks
`low at this inspection. The long-term goal is to be able to eliminate this inspection through con-
`tinued improvement by using Statistical Process Control.
`
`vii. Post-Develop (Hard) Bake
`
`After the inspection is completed, the wafers are given a "hard bake" at a temperature of 130°C to
`160°C to dehydrate the photoresist prior to etch or ion implant processes. This bake stabilizes the
`resist characteristics and makes the resist less sensitive to these hostile process environments.
`
`f. Etch
`
`The etching process removes the material not protected by the hardened photoresist. The result
`of the etching process was illustrated in Figure 2-15 for positive resist and is shown in Figure 2-39
`for negative resist.
`
`These figures are idealistic representations of the patterning process. In actual manufacturing,
`there are varying degrees of acceptable results. Figure 2-40 illustrates several examples.
`
`The etching process is divided into two basic methods: isotropic and anisotropic. These terms
`describe the geometrical shape the film will have after the etching process.
`
`i. Isotropic/Anisotropic
`
`An isotropic etch process will etch laterally while etching the material vertically. The worst case
`is when the lateral rate is equal to the vertical etch rate. The anisotropic etch will etch only in the
`vertical direction. These concepts are illustrated in Figure 2-41.
`
`2-40
`
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`1
`
`2
`
`3
`
`Basic Integrated Circuit Manufacturing
`
`Photoresist
`
`SiO2
`
`Photoresist
`
`SiO2
`
`SiO2
`
`18408
`
`Figure 2-39. Photolithography Using Negative Photoresist
`
`The etching process is essentially a subtractive process to remove the material not protected by
`the photoresist. There are several methods used to remove any given material. The more
`common methods are: wet chemistry, plasma dry chemistry, reactive ion etching dry chemistry,
`and ion milling.
`
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`Basic Integrated Circuit Manufacturing
`
`Heating the photoresist as a cleaning process is not used because of the residue remaining. A tech-
`nique that is gaining acceptance is to use ultraviolet energy in the presence of ozone (O3).
`
`After the photoresist has been stripped (removed), the wafer is given some type of visual inspec-
`tion. Like other visual inspections, pattern recognition inspection equipment and sampling tech-
`niques are used.
`
`E. JUNCTION FORMATION
`
`Recalling from the materials section, dopant atoms are added to the silicon lattice when the sili-
`con ingot is grown to provide the electrical characteristics of the wafer (N-type or P-type). During
`the process of producing ICs on the wafer, atoms of the same polarity as the wafer or of the oppo-
`site polarity must be introduced into the wafer in selected regions. This alteration of the dopant
`levels is done by solid-state diffusion or ion implantation.
`
`1. Diffusion
`
`Diffusion is the term used to describe the movement of atoms, molecules, or particles from a loca-
`tion of high concentration to a new location of lower concentration. An example of the process of
`diffusion can be visualized by watching a small drop of red coloring being dropped into a glass
`of clear water.
`
`Initially, as the drop strikes the clear water, the red color is highly concentrated. After a short
`period of time the deep red color begins to lessen and the color starts to spread out over a larger
`volume. As more time elapses, the color continues to spread out and the red color starts to change
`to pale red and on into a pink. In a given time the pink will almost disappear in the now nearly
`clear water.
`
`The process just described represents diffusion as a function of time and temperature. The rate an
`atom, molecule or compound diffuses from a high concentration to a lesser concentration is
`related to temperature and time. The parameter that ties the diffused rate to temperature for a
`given time is known as the diffusion coefficient or diffusivity.
`
`The dopant atom must displace a silicon atom in the crystal structure of the silicon to become elec-
`trically active. The process of diffusion is used in semiconductor processing to introduce a con-
`trolled amount of a chosen dopant into selected regions of a semiconductor crystal. The diffusion
`process used to accomplish this substitution is divided into two distinct steps.
`
`1. Predeposition
`2. Redistribution or drive-in
`
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`Basic Integrated Circuit Manufacturing
`
`A. Stained single-junction structure
`revealed by interference fringes.
`
`B. Stained double-junction structure
`revealed by interference fringes.
`
`Photos by ICE
`
`1851
`
`Figure 2-54. Monochromatic Light Examinations
`
`Figure 2-55. Silicon Gate MOS Cross-Section
`
`10250B
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`Basic Integrated Circuit Manufacturing
`
`• Low electrical resistivity
`• Ohmic and low contact resistance
`• Stable contact formation to silicon or other metal(s)
`• High temperature stability
`• Excellent adhesion and low stress
`• Good electromigration resistance
`• Good corrosion resistance
`• Controlled oxidation properties and stability in an
` oxidizing environment
`• Ease of formation
`• Ease of fine line pattern transfer
`• Smooth surface features
`
`18419
`
`2. Materials
`
`The basic materials requirements to
`interconnect the components within
`an IC are listed in Figure 2-70.
`Unfortunately, no individual metal
`can meet all of the requirements.
`Aluminum is the most often used
`metal but its use is being challenged
`by newer circuit requirements.
`
`Figure 2-70. Conductor Material Properties
`Requirements for VLSI
`
`When pure aluminum is used to
`interconnect shallow p-n junction
`devices, a reliability problem can
`occur. The silicon atoms in the sub-
`strate diffuse into the aluminum metallization. Over extended time and temperature, sufficient sil-
`icon is depleted to cause a metal short through the p-n junction. This concept is illustrated in Figure
`2-71. The problem can be minimized by adding a small percentage of silicon into the aluminum.
`
`0.3µ
`
`N+
`
`SHORT
`
`Al
`SiO2
`
`P
`
`N
`
`Source: ICE
`
`3090A
`
`Figure 2-71. Aluminum/Silicon Dissolution
`
`3. Methods
`
`a. E-beam, Filament Evaporation
`
`The methods for depositing metal films are tabulated in Figure 2-72. The semiconductor industry
`has evolved through each of the methods except Ion Beam deposition, which has not been imple-
`mented to any great extent yet. Sputtering is the most commonly used method while
`LPCVD/PECVD is being used for selected films of tungsten. Diagrams for filament evaporation
`and electron-beam (e-beam) are shown in Figure 2-73 and Figure 2-74, respectively.
`
`2-66
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`Basic Integrated Circuit Manufacturing
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`Evaporation
`• Hot Filaments
`• Resistive Filaments, Heated Crucible
`• R.F. Heated Crucible
`• Electron-Beam
`
`Sputtering
`• Planar Diode
`• Planar Triode
`• Planar Magnetron (Diode or Triode)
`• R.F. Diode
`
`Chemical Vapor Deposition
`• LPCVD
`• PECVD
`
`Ion Beam Deposition
`
`Figure 2-72. Methods of Metal Deposition
`
`18420
`
`Evaporant
`Charge
`
`Bell Jar
`
`To
`High Current
`Source
`
`1959B
`
`To Vacuum Pump
`(10–5 Torr)
`
`Source: ICE
`
`Figure 2-73. Vacuum Evaporation System
`
`INTEGRATED CIRCUIT ENGINEERING CORPORATION
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`Heater
`Filament
`
`Vapor
`
`Wafers
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`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
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`Basic Integrated Circuit Manufacturing
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`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`Planetary
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`Wafer
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`Holder
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`Vapor
`Evaporant
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`Charge
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`Electron
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`Beam Gun
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)
`To Vacuum
`(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)
`Pump
`(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)
`
`(cid:0)(cid:0)(cid:0)
`
`Source: ICE
`
`Figure 2-74. Electron Beam Evaporation
`
`To EB
`Power
`Supply
`1430
`
`The electron-beam system requires a separate e-gun for each material to co-deposit the film. This
`increases the cost of the deposition system.
`
`b. Sputtering
`
`Low-pressure sputtering evolved as an improved alternative to the e-beam deposition system. A
`sputtering system is diagrammed in Figure 2-75. The main advantage of sputtering is the physi-
`cal nature of the process. Argon is the ionized atom most commonly used to bombard the target
`material. This physical bombardment causes the target material to be deposited from many dif-
`ferent angles, which provides a more uniform deposition, regardless of target composition. The
`resulting step coverage is improved as shown in Figure 2-76.
`
`Many refinements have been made on the hardware of sputtering deposition systems. These
`improvements have made it the method of choice for the majority of wafer fabs. Various ways of
`configuring the sputtering system were noted in Figure 2-72. One of the more popular concepts
`is shown in Figure 2-77.
`
`2-68
`
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`
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`
`

`

`Basic Integrated Circuit Manufacturing
`
`I. PROCESSES
`
`1. CMOS
`
`Figures 2-83, 2-84, and 2-85 provide a graphical representation of the IC manufacturing cycle.
`Figures 2-86, 2-87, and 2-88 provide graphical cross-sections of the CMOS structure as the circuit
`travels through the manufacturing cycle. Each group of process steps are narrated relative to
`Figures 2-83, 2-84, and 2-85.
`
`EPI-Silicon
`Single Crystal
`
`Wafers
`
`Oxidation
`Furnace
`
`LPCVD
`Furnace
`
`Mask 1
`
`Plasma Etch
`
`Ion Implanter
`
`Initial
`Oxidation
`
`Deposit
`Silicon
`Nitride
`
`N-Well
`Photolithography
`
`Nitride Etch
`
`Phosphorus Ion Implant
`N-Well
`
`Diffusion
`Furnace
`
`Plasma Etch
`
`Ion Implanter
`
`Diffusion
`Furnace
`
`Strip
`Resist
`
`Diffusion
`Furnace
`
`Strip
`Oxide
`
`Strip Nitride
`
`N-Well Drive &
`Selective Oxidation
`
`Boron Ion Implant
`P-Well
`
`P-Well
`Drive &
`Oxidation
`
`Grow
`Buffer
`Oxide
`
`LPCVD
`Furnace
`
`Mask 2
`
`Diffusion
`Furnace
`Plasma System
`
`Diffusion
`Furnace
`
`Deposit Silicon
`Nitride
`
`Active Area
`Photolithography
`
`Etch Nitride
` Strip Resist
`
`Selective Oxidation
`Field
`
`Planarize -
`Strip Nitride
`Etch-Back
`Oxide
`
`Grow Implant
`Buffer Oxide
`
`Ion Implanter
`
`Mask 3
`
`Ion Implanter
`
`Diffusion
`Furnace
`
`LPCVD
`Furnace
`
`Strip
`Resist
`
`Adjust Implant
`
`VTR
`Source: ICE
`
`VTP
` Adjust Implant
`Photolithography
`
`VTP Adjust Implant
`
`Gate Oxidation
`
`Polysilicon
`Deposition
`
`14811
`
`Figure 2-83. Twin-Well Silicon-Gate CMOS Manufacturing Sequence (1 of 3)
`
`2-74
`
`INTEGRATED CIRCUIT ENGINEERING CORPORATION
`
`Page 13 of 19
`
`

`

`Basic Integrated Circuit Manufacturing
`
`LPCVD
`
`Rapid Thermal
`Processor
`
`Mask 4
`
`RIE Plasma Etch
`
`Poly Doping
`Implant
`
`Tungsten Silicide
`Deposition
`
`Create Polycide
`
`Gate
`Photolithography
`
`Etch Silicide/Poly
`
`Ion Implanter
`
`Mask 5
`
`Ion Implanter
`
`Lpcvd
`Furnace
`
`RIE Plasma Etch
`
`Phosphorus Implant,
`N-Channel Lightly
`Doped Drain (LDD)
`
`P-Channel LDD
`Photolithography
`
`Boron Implant
`P-Channel Lightly
`Doped Drain (LDD)
`
`Deposit Oxide
`For Sidewall
`Spacers
`
`Form Sidewall
`Spacers
`
`Diffusion
`Furnace
`
`Mask 6
`
`Ion Implanter
`
`Mask 7
`
`Ion Implanter
`
`Grow Implant
`Buffer Oxide
`
`P-Channel Source-Drain
`Photolithography
`
`Boron Ion Implant
`P-Channel Source-Drain
`Ion Implant
`
`N-Channel Source-Drain
`Photolithography
`
`Arsenic Ion Implant
`N-Channel
`Source-Drain
`
`Furnace
`
`LPCVD
`Furnace
`
`Diffusion
`Furnace
`
`LPCVD
`Furnace
`
`Diffusion
`Furnace
`
`Mask 8
`
`Apply
`Spin-On
`Glass
`(SOG)
`
`Implant Anneal,
`Source Drain
`Diffusion
`
`Deposit
`Low-Temperature
`Phosphosilicate
`Glass
`
`Source: ICE
`
`Deposit
`Reflow Oxide
`Densify SOG
`Borophosphosilicate
`Glass (BPSG)
`
`Contact
`Photolithography
`
`14812
`
`Figure 2-84. Twin-Well Silicon-Gate CMOS Manufacturing Sequence (2 of 3)
`
`INTEGRATED CIRCUIT ENGINEERING CORPORATION
`
`2-75
`
`Page 14 of 19
`
`

`

`Basic Integrated Circuit Manufacturing
`
`Plasma Etch
`
`Etch Contacts
`
`Mask 9
`
`Ion Implanter
`
`Rapid Thermal
`Processor
`
`Metal Deposition
`System
`
`N-Contact
`Enhancement
`Photolithography
`
`Phosphorus Implant
`N+ Contacts
`
`Implant
`Active/Anneal
`
`Deposit First
`Level Metal
`
`Mask 10
`
`Plasma Etch
`
`Diffusion
`Furnace
`
`LPCVD
`Furnace
`
`Mask 11
`
`Plasma Etch
`
`Metal-1
`Photolithography
`
`RIE Etch
`Metal 1
`
`Sinter
`Metal 1
`
`Deposit
`Interlevel
`Oxide
`
`Via
`Photolithography
`
`RIE Etch Vias
`
`Metal Deposition
`System
`
`Mask 12
`
`LPCVD
`Furnace
`
`Plasma Etch
`
`Metal 2
`Photolithography
`
`RIE Metal 2
`
`Deposit
`Passivation
`Film
`
`Deposit Metal 2
`
`Mask 13
`
`Wafer Probe
`
`Bonding Pad
`Photolithography
`& Etch
`Source: ICE
`
`14813
`
`Figure 2-85. Twin-Well Silicon-Gate CMOS Manufacturing Sequence (3 of 3)
`
`2-76
`
`INTEGRATED CIRCUIT ENGINEERING CORPORATION
`
`Page 15 of 19
`
`

`

`Basic Integrated Circuit Manufacturing
`
`INFANT
`MORTALITY
`
`OPERATING
`LIFE
`
`WEAROUT
`
`TIME
`
`INSTALLATION
`CUSTOMER USE
`
`15038
`
`FAILURE RATE l
`
`BURN-IN
`
`Source: IEEE
`
`Figure 2-120. Bathtub Curve Prediction of Reliability
`
`L. SUMMARY OF SEMICONDUCTOR MANUFACTURING
`
`The impact of integrated circuits on the electronics industry has been phenomenal. Not only are
`they changing the physical appearance and modes of operation of electronic equipment, but are
`also causing major changes in the entire structure of the electronic industry. Methods of transact-
`ing business are changing. The supplier-user interface is changing. The decision to custom design
`ICs or use standard or semicustom devices becomes a major consideration for many electronic
`companies.
`
`The IC manufacturing process roadmap is illustrated in Figure 2-121. The logic designer can
`either work for a systems company or be part of the IC design team within the semiconductor
`manufacturer. The circuit designer generally works for the semiconductor manufacturer. The cir-
`cuit designer translates the logic designer's requirements into a semiconductor circuit design.
`
`The circuit designer will convert the electrical schematic of the circuit into the physical size of each
`component, i.e., transistor, diode, resistor, capacitor, etc., that makes up the circuit. The designer
`uses a workstation (CAD) to accomplish the design and do the many different simulations
`required for design verification.
`
`INTEGRATED CIRCUIT ENGINEERING CORPORATION
`
`2-107
`
`Page 16 of 19
`
`

`

`Basic Integrated Circuit Manufacturing
`
`Logic Designer
`
`Circuit Designer
`
`Computer
`Pushed Polygons
`
`Electron
`Beam System
`
`Tape-Out
`
`Grow
`Crystal
`
`Slice/Polish
`Wafers
`
`Reticle or Masks
`
`Ion Implantation
`+ Reoxidation
`
`Photoetch
`
`Basic Building
`Block
`
`Die-Attach Lead
`Bonding and Sealing
`
`Test Scribe
`and Dice
`
`Aluminum Interconnection
`and Passivation
`
`M
`
`E T E K
`1 2 3 4 5 6 7 8 A B C
`
`A C
`
`Marking
`
`End Product
`
`Shipping
`
`Source: ICE
`
`Test
`
`16859
`
`Figure 2-121. Integrated Circuit Manufacturing Process
`
`2-108
`
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`
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`
`

`

`Basic Integrated Circuit Manufacturing
`
`The geometrical layout is the final output of the workstation in the form of a database tape. The
`database tape is the input information for the electron-beam system. The electron-beam system
`uses the input data to create the reticles or masks required in IC manufacturing. The number of
`reticles or masks is determined by the actual manufacturing process cycle. This is often referred
`to as the "Fab Process." The newer Fab Processes use between fourteen and twenty-four reticles
`or masks.
`
`The central region of Figure 2-121 depicts the wafer fab process. After the wafer fab process is
`completed, the wafers are tested electrically to the required specifications and then forwarded to
`the assembly process.
`
`The assembly process will package each electrically good die. After packaging is completed, the
`device will be given a final electrical test, burn-in as required, and shipped to the end user. The
`end user creates the electronic system by bringing together all the necessary electrical compo-
`nents, mechanical hardware and the final package of the product.
`
`There is no doubt the world is in the silicon age. Silicon devices in the form of discrete products
`or ICs touch our lives in many ways everyday. And — since silicon is the second most abundant
`element in the earth, there doesn't appear there will ever be a shortage of the raw material.
`
`INTEGRATED CIRCUIT ENGINEERING CORPORATION
`
`2-109
`
`Page 18 of 19
`
`

`

`Basic Integrated Circuit Manufacturing
`
`2-110
`
`INTEGRATED CIRCUIT ENGINEERING CORPORATION
`
`Page 19 of 19
`
`