`
`Solid State Electronic Devices
`Solid State Electronic Devices
`
`'
`
`•
`
`Qualcomm Incorporated
`EX1024
`
`Page 1 of 31
`
`Qualcomm Incorporated
`EX1024
`Page 1 of 31
`
`

`

`..
`
`.·
`
`.·
`
`..
`
`. ~
`
`Multi-level copper metallization of o complementary metal oxide semiconductor (CMOS) chip. This
`scanning electron micrograph (scale: 1 cm -= 3.5 microns) of a CMOS integrated circuit shows six levels
`of copper metallization that ore used to ca rry electrical signals on the chip. The inter-metal dielectric
`insulators have been chemically etched away here lo reveal the copper interconnects. [Photograph
`courtesy of IBM )
`
`Page 2 of 31
`
`

`

`FIFTH EDITION
`
`Solid State
`Electronic Devices
`
`BEN G. STREETMAN AND SANJAY BANERJEE
`
`Microelectronics Research Center
`Department of Electrical and Computer Engineering
`The University of Texas at Austin
`
`•
`
`PRENTICE HALL
`Upper Saddle River, New Jersey 07458
`
`Page 3 of 31
`
`

`

`Library of Congress Cataloging-in-Publication Da1a
`Streetman, Ben G.
`Solid state electronic devices I Ben G. Streetman and Sanjay
`Banerjee -- 5th ed.
`p. cm. - {Prentice Hall series in solid state physical
`electronics)
`Includes bibliographical references and index.
`ISBN 0-13-025538-6 ( casebound)
`I. Banerjee, Sanjay.
`1. Semiconductors.
`ill. Series
`TK7871.85.S77 2000
`621.3815'2--<lc21
`
`II. Title.
`
`99-16963
`CIP
`
`Publisher: Tom Robbins
`Assistant Vice President of Production and Manufacturing: David W. Riccardi
`Editor-in-Chief: Marcia Horton
`Associate Editor: Alice Dworkin
`Cover Design: Joseph Sengotta
`Cover: Fourth Generation PowerPC Microprocessor chip courtesy of Motm:ola, Inc.
`Photograph by Kobi Benzvi and Pradipto Mukherjee
`Manufacturing Manager: Trudy Pisciotti
`
`• ©2000, 1995, 1990, 1980, 1972 by Prentice Hall, Inc .
`
`A Simon & Schuster Company
`Upper Saddle River, New Jersey 07458
`
`All rights reserved. No part of this book may be
`reproduced, in any form or by any means,
`without permission in writing from the publisher.
`
`Printed in the United States of America
`
`10 9 8 7 6 5 4 3 2 1
`
`ISBN 0-13-025538-6
`
`Prentice Hall International (UK) Limited, London
`Prentice Hall of Australia Pty. Limited, Sydney
`Prentice Hall Canada Inc., Toronto
`Prentice Hall Hispanoamericana, S.A., Mexico
`Prentice Hall of India Private Limited, New Delhi
`Prentice Hall of Japan, Inc., Tokyo
`Simon & Schuster Asia Pte. Ltd., Singapore
`Editora Prentice Hall do Brasil, Ltda., Rio de Janeiro
`
`.-
`
`Page 4 of 31
`
`

`

`286
`
`Chapter 6
`
`6.5
`THE MOS FIELD(cid:173)
`EFFECT
`TRANSISTOR
`
`The MOS transistor is also called a surface field-effect transistor, since it de(cid:173)
`pends on control of current through a thin channel at the surface of the semi(cid:173)
`conductor (Fig. 6-10). When an inversion region is formed under the gate,
`current can flow from drain to source (for an n-channel device). In this sec(cid:173)
`tion we analyze the conductance of this channel and find the ID - VD char(cid:173)
`acteristics as a function of gate voltage VG· As in the JFET case, we will find
`these characteristics below saturation and then assume ! 0 remains essen(cid:173)
`tially constant above saturation.
`
`6.5. l Output Characteristics
`
`The applied gate voltage VG is accounted for by Eq. (6-28) plus the voltage
`required to achieve flat band:
`
`(6-44)
`
`The induced charge Q 5 in the semiconductor is composed of mobile charge
`Qn and fixed charge in the depletion region Qd· Substituting Q,, + Qd for Q"
`we can solve for the mobile charge:
`
`(6-45)
`
`At threshold the term in brackets can be written Va - VT from Eq. (6-38).
`With a voltage V 0 applied, there is a voltage rise V< from the source to
`each point x in the channel. Thus the potential <j>s(x) is that required to achieve
`strong inversion (2<l>F) plus the voltage V":
`
`If we neglect the variation of Qd(x) with bias Vx, Eq. ( 6-46) can be sim(cid:173)
`plified to
`
`Q 11(x) = -C;( VG - VT - Vx)
`
`(6-47)
`
`This equation describes the mobile cha ge in the channel at pomtx (Fig. 6--6).
`The conductance of the differential element dx is j:J::11Q 11(x )Z/ dx. where Z is Lhe
`width of the channel and µ;n is a swf'Clce e lectron mobility indicating the mobil(cid:173)
`ity in a thin region near the surface i not the same as in the bulk material). At
`point x we have
`
`(6-48)
`
`Page 5 of 31
`
`

`

`Field-Effect Transistors
`
`G
`
`+ + + +
`
`z
`
`287
`
`Figure 6-26
`Schematic view of
`the n-channel re(cid:173)
`gion of a MOS
`transistor under
`bias below pinch(cid:173)
`off, and the varia(cid:173)
`tion of voltage Vx
`along the conduct(cid:173)
`ing channel.
`
`x
`I
`I
`I
`I
`I
`I
`
`I
`x +dx
`I
`I
`I
`I
`I
`I
`
`0
`
`0
`
`L
`
`Integrating from source to drain,
`
`I Ddx = µ;nZC;
`
`f L
`
`0
`
`f V
`
`0
`
`(Va - V r - V x)dV x
`
`0
`
`(6--49)
`
`where
`
`determines the conductance and transconductance of then-channel MOSFET
`(see Eqs. (6-51) and (6-54)).
`In this analysis the depletion charge Qd in the threshold voltage V r is
`simply the value with no drain current. This is an approximation, since Qix)
`varies considerably when VD is applied, to reflect the variation in Vx (see Fig.
`6-26b ). However, Eq. ( 6--49) is a fairly accurate description of drain current
`for low values of VD• and is often used in approximate design calculations be(cid:173)
`cause of its simplicity. A more accurate and general expression is obtained by
`including the variation of Qix). Performing the integration of Eq. (6--48)
`using Eq (6--46) for Qn(x), one obtains
`
`Page 6 of 31
`
`

`

`288
`
`Chapter 6
`
`µ,,zc,
`ln= - -
`L
`
`2 "v'2E N
`}
`C~ n ((Vo+2<j>F)312 -(2<!>dl2J
`X (VG-VFB-2<1>f-tVo)Vo-3
`{
`
`(6-50)
`
`The drain characteristics that result from these questions are shown in Fig.
`6-lOc. If the gate voltage is above threshold (Va > VT), the drain current is de(cid:173)
`scribed by Eq. (6-50) or approximately by Eq. (6-49) for low VD· Initially the
`channel appears as an essentially linear resistor, dependent on V 0 • The conduc(cid:173)
`tance of the channel in this linear region can be obtained from Eq. (6-49) with
`Vn ~(Va - Vr):
`
`(6-51)
`
`where V c > VT for a channel to exist.
`As the drain voltage is increased, the voltage across the oxide decreases
`near the drain, and Q,, becomes smaller there. As a result the channel be(cid:173)
`comes pinched off at the drain end, and the current saturates. The saturation
`condition is approximately given by
`
`The drain current at saturation remains essentially constant for larger values
`of drain voltage. Substituting Eq. (6-52) into Eq. (6-49), we obtain
`
`I 0 (sat.) = !l:LnC;~( V c - VT)2 = 2~f:LnCYb(sat.)
`
`(6-53)
`
`(6-52)
`
`for the approximate value of drain current at saturation.
`The transconductance in the saturation range can be obtained ap(cid:173)
`proximately by differentiating Eq. (6-53) with respect to the gate voltage:
`CJ! v( at. ) z_
`cW G = L µ,nC;(V G - V r)
`
`gm( sat.) =
`
`(6-54)
`
`The derivations presented here are based on the n-channel device. For
`the p-channel enhancement transistor the voltages VD• VG• and VT are neg(cid:173)
`ative, and current flows from source to drain (Fig. 6-27).
`
`6.5.2 Transfer Characteristics
`
`The output characteristics plot the drain current as a function of the drain
`bias, with gate bias as a parameter (Fig. 6-27). On the other hand, the trans(cid:173)
`fer characteristics plot the output drain current as a function of the input
`gate bias, for fixed drain bias (Fig. 6-28a). Clearly, in the linear region, 10
`versus V c should be a straight line from Eq. (6-49). The intercept of this line
`on the V c axis is the linear region threshold voltage, VT (lin.) and the slope
`
`,
`
`.
`
`Page 7 of 31
`
`

`

`289
`
`Figure 6-27
`Drain current(cid:173)
`voltage character(cid:173)
`istics for enhance(cid:173)
`ment transistors:
`(a) for n-channel
`V0 , VG, Vr, and 10
`are positive; (b)
`for p-channel all
`these quantities
`are negative.
`
`5
`
`4
`
`3
`
`Field-Effect Transistors
`
`+
`
`+
`
`(a)
`
`(b)
`
`-3
`
`- s -
`
`-
`
`-
`
`VG= - 6V ___ ..-
`
`(divided by the applied V v) gives us the linear value of kN, kN(lin. ), of the
`n-channel MOSFET. If we look at actual data, however, we see that while the
`characteristics are approximately linear at low gate bias, at high gate biases
`the drain current increases sub-linearly. The transconductance, gm (lin.), in the
`linear region can be obtained by differentiating the right hand side of Eq. ( 6-49)
`with respect to gate bias. The gm (lin.) is plotted as a function of VG in Fig. 6-28b.
`It may be noted that the transconductance is zero below VT because there is lit(cid:173)
`tle drain current. It goes through a maximum at the point of inflection of the
`Iv-VG curve, and then decreases. This decrease is due to two factors that will be
`discussed in Sections 6.5.3 and 6.5.8: degradation of the effective channel mo(cid:173)
`bility as a function of increasing transverse electric field across the gate oxide,
`and source/drain series resistance.
`For the transfer characteristics in the saturation region, since Eq. (6-53)
`shows a quadratic dependence of Iv on VG' we get a linear behavior by plot(cid:173)
`ting not the drain current, but rather the square root of Iv, as a function of
`VG (Fig. 6-29). In this case the intercept gives us the threshold voltage in the
`saturation region, V r(sat.). We shall see in Section 6.5.10 that due to effects
`such as drain induced barrier lowing (DIBL), for short channel length MOS(cid:173)
`FETs the Vr(sat.) can be lower than Vr(lin.), while the long channel values
`are similar. Similarly, the slope of the transfer characteristics can be used to
`determine the value of kN in the saturation region, kN(sat.) for then-channel
`MOSFET, which can be different from kN(lin.) for short channel devices.
`
`'
`
`Page 8 of 31
`
`

`

`290
`
`Chapter 6
`
`Figure 6-28
`Linear region
`transfer character-
`istics: (a) plot of
`drain current ver(cid:173)
`sus gate voltage
`for MOSFETs in
`the linear region;
`(b) transconduc(cid:173)
`tance as a func(cid:173)
`tion of gate bias .
`
`Deviation from linearity
`due to field - dependent
`mobility and
`source - drain series
`resistance
`
`. .. ..
`
`.
`.....
`:.
`
`0
`
`6.5.3 Mobility Models
`
`The mobility of carriers in the channel of a MOSFET is lower than in bulk
`semiconductors because there are additional scattering mechanisms. Since
`carriers in the channel are very close to the semiconductor-oxide interface,
`they are scattered by surface roughness and by coulombic interaction with
`fixed charges in the gate oxide. When the carriers travel in the inversion Jayer
`from the source to the drain, they encounter microscopic roughness .on an
`
`Page 9 of 31
`
`

`

`Field-Effect Transistors
`
`)I (sat) =JkN(sat) (V - V )
`z
`D
`G
`T
`
`/
`i
`l
`
`291
`
`Figure 6-29
`Saturation region
`transfer character(cid:173)
`istics: plot of
`square root of the
`drain current ver(cid:173)
`sus gate voltage
`for MOSFETs .
`
`...__ Slope gives
`kN(sat)
`
`f
`/
`
`atomistic scale at the oxide-silicon interface and undergo scattering because, as
`discussed in Section 3.4.1, any deviation from a perfectly periodic crystal po(cid:173)
`tential results in scattering. This mobility degradation increases with the gate
`bias because a higher gate bias draws the carriers closer to the oxide-silicon in(cid:173)
`terface, where they are more influenced by the interfacial roughness.
`It is very interesting to note that if we plot the effective carrier mobil(cid:173)
`ity in the MOSFET as a function of the average transverse electric field in
`the middle of the inversion layer, we get what is known as a "universal" mo(cid:173)
`bility degradation curve for any MOSFET, which is independent of the tech(cid:173)
`nology or device structural parameters such as oxide thickness and channel
`doping (Fig. 6-30). We can apply Gauss's law to the region marked by the col(cid:173)
`ored box in Fig. 6-31, which encloses all the depletion charge and half of the
`inversion charge in the channel. We see that the average transverse field in
`the middle of the inversion region is given by
`
`cgeff = ~' ( Qd + ~ Qn)
`
`(6-55a)
`
`While this model works quite well for electrons, for reasons that are not clear(cid:173)
`ly understood at present, it has to be modified slightly for holes in the sense
`that the average transverse field must now be defined as
`cgeff = ~s ( Qd + ~ Qn)
`
`(6- 55b)
`
`Page 10 of 31
`
`

`

`292
`
`Chapter 6
`
`Figure 6-30
`Inversion layer
`electron mobility
`versus effective
`transverse field, at
`various tempera(cid:173)
`tures. The trian(cid:173)
`gles, circles and
`squares refer to
`different MOSFETs
`with different gate
`oxide thicknesses
`and channel dop(cid:173)
`ings. (After Sabnis
`and Clemens,
`IEEE IEDM,
`1979) .
`
`800
`
`700
`
`\
`
`Si
`o-chao::iel
`~-« 103 V.1cm
`
`~ 600
`I
`~"'
`
`I > 500
`N a
`-!:!.-
`" ::l. 400
`
`300
`
`200
`
`0
`
`3
`5
`6
`2
`4
`Effective transverse field ~y(1Cl5 V/cm)
`
`7
`
`~eff
`
`. ..
`
`I
`o. !
`I
`I
`I
`Oct
`__ ___ __ I
`
`Gaussian
`"box "
`
`y
`
`y
`
`y
`
`Figure 6-31
`Determination of effective transverse field . Idealized charge distribJtion and transverse electric field in
`the inversion layer and depletion layer, as a function of depth in the channel of a MOSFET. The region
`to whicr we apply Gauss's law is shown in color.
`
`This degradation of mobility with gate bias is often compactly described
`by ~Titing the drain current expression as
`.
`_
`µ,"zc,
`[
`1 ,2 ]
`Io - L{ J + a v c - V·rl} (Va - v TW o - 2ii o
`
`(6-56)
`
`where 8 is called the mobility degradation parameter. Because of the additional
`(Va - VT) term in the denominator, the drain current increases sub-linearly with
`gate bias for high gate voltages.
`In addition to this dependence of the channel mobility on gate bias or
`transverse electric field, there is also a strong dependence on drain bias or the
`
`Page 11 of 31
`
`

`

`Field-Effect Transistors
`
`293
`
`longitudinal electric field.As shown in Fig. 3-24, the carrier drift velocity in(cid:173)
`creases linearly with electric field (ohmic behavior) until the field reaches ~sat;
`in other words, the mobility is constant up to ~sat· After this, the velocity sat(cid:173)
`urates at v,, and it can no longer be described in terms of mobility. These ef(cid:173)
`fects can be described as:
`
`V = µ ~ for ~ < ~sat
`and V = V5 for ~ > ~sac
`The maximum longitudinal electric field near the drain end of the channel is ap(cid:173)
`proximately given by the voltage drop along the pinch-off region, (VD-VD( sat.)),
`divided by the length of the pinch-off region, l:l.L.
`
`(6-57)
`
`(6-58)
`
`= (V0 - V0 (sat.))
`
`~max
`
`l:l. L
`
`(6-59)
`
`From a two-dimensional solution of the Poisson equation near the drain end,
`one can show that the pinch-off region l:l.L shown in Fig. 6-llc is approxi(cid:173)
`mately equal to v'(3dxj), where dis the gate oxide thickness and xi is the
`source/drain junction depth. The factor of 3 is due to the ratio of the dielec(cid:173)
`tric constant for Si to that of Si02.
`
`6.5.4 Short Channel MOSFET 1-V Characteristics
`
`In short channel devices, the analysis has to be somewhat modified. As men(cid:173)
`tioned in the previous section, the effective channel mobility decreases with
`increasing transverse electric field perpendicular to the gate oxide (i.e., the
`gate bias). Furthermore, for very high longitudinal electric fields in the pinch(cid:173)
`off region, the carrier velocity saturates (Fig. 3-24 ). For short channel lengths,
`the carriers travel at the saturation velocity over most of the channel. In that
`case, the drain current is given by the width times the channel charge per
`unit area times the saturation velocity.
`
`As a result, the saturation drain current does not increase quadratically with
`(Va - Vr) as shown in Eq. (6-53), but rather shows a linear dependence
`(note the equal spacing of curves in Fig. 6-32). Due to the advances in Si de(cid:173)
`vice processing, particularly photolithography, MOSFETs used in modern
`integrated circuits tend to have short channels, and are commonly described
`by Eq. (6--60) rather than Eq. (6--53).
`
`(6-60)
`
`6.5.5 Control of Threshold Voltage
`
`Since the threshold voltage determines the requirements for turning the MOS
`transistor on or off, it is very important to be able to adjust VT in designing the
`device. For example, if the transistor is to be used in a circuit driven by a 3-V
`
`Page 12 of 31
`
`

`

`294
`
`Chapter 6
`
`Figure 6-32
`Experimental out-
`put characteristics
`of n-channel and
`p-channel
`MOSFETs with
`0.1 µm channel
`lengths. The
`curves exhibit al-
`most equal spac-
`ing, indicating a
`linear depen-
`dence of 10 on VG,
`rather than a qua-
`dratic depen-
`dence. We also
`see that 10 is not
`constant but in-
`creases somewhat
`with Ve in the sat-
`uration region .
`The p-channel de-
`vices have lower
`currents because
`hole mobilities are
`lower than elec-
`Iron mobilities.
`
`I '
`
`. '
`
`pMOS
`
`nMOS
`
`V0 =1.5V
`
`d =3nm
`
`- l.5V
`
`900
`
`800
`
`700
`
`600
`
`500 -
`
`e
`2-
`< :i
`..9 400
`
`300 -
`
`200 -
`
`100
`
`0
`-1.5
`
`'.
`-.75
`
`I . '
`0.75
`
`1.5
`
`0
`
`Vo(V)
`
`battery, it is clear that a 4-V threshold voltage is unacceptable. Some applica(cid:173)
`tions require not only a low value of VT> but also a precisely controlled value
`to match other devices in the circuit.
`All of the terms in Eq. (6- 38) can be controlled to some extent. The
`work function potential difference <l>111s is determined by choice of the gate
`conductor material; <l>F depends on the substrate doping; G; can be reduced
`by proper oxidation methods and by using Si grown in the (100) orientation;
`Qd can be adjusted by doping of the substrate; and C; depends on the thick(cid:173)
`ness and dielectric constant of the insulator. We shall discuss here several
`methods of controlling these quantities in device fabrication .
`
`Choice of Gate Electrode. Since VT depends on <1>111,., the choice of the gate
`electrode material (i.e., the gate electrode work function) has an impact on the
`threshold voltage. When MOSFETs were first made in the 1960's, they used
`Al gates. However, since Al has a low melting point, it precluded the use of a
`self-aligned source/drain technology because that required a high temperature
`source/drain implant anneal after the gate formation. Hence, Al was sup(cid:173)
`planted by n+ doped LPCVD polysilicon refractory (high melting point) gates,
`where the Fermi level lines up with the conduction band edge in Si. While
`this works quite well for n-cbannel MOSFETs, we shall see in Section 9.3.l that
`
`Page 13 of 31
`
`

`

`Field-Effect Tran sistors
`
`295
`
`it can create problems for p-channel MOSFETs. Therefore, sometimes, a p+
`doped polysilicon gate is used for p-channel devices. Refractory metal gates
`with suitable work functions are also being researched as possible replace(cid:173)
`ments for doped polysilicon. One attractive candidate is tungsten,whose work
`function is such that the Fermi level happens to lie near the mid-gap of Si.
`
`Control of C;. Since a low value of VT and a high drive current is usually
`desired, a thin oxide layer is used in the gate region to increase C; = E/d in
`Eq. (6-38). From Fig. 6-20 we see that increasing C; makes VT less negative
`for p-channel devices and less positive for n-channel with -Qd > Qi· For
`practical considerations, the gate oxide thickness is generally 20 - 100 A
`(2 - 10 nm) in modem devices having submicron gate length. An example
`of such a device is shown in Figure 6-33. The gate oxide, easily observable in
`
`Figure 6-33
`Cross section of a MOSFET. This high resolution transmission electron micrograph of a silicon
`Metal-Oxide ,Semiconductor Field Effect Transistor shows the silicon channel and metal gate separated
`by a thin (40A, 4nm) silicon-dioxide insulator. The inset shows a magnified view of the three regions, in
`which individual rows of atoms in the crystalline silicon can be distinguished. (Photograph courtesy of
`AT&T Bell Laboratories.)
`
`•
`
`Page 14 of 31
`
`

`

`296
`
`Chapter 6
`
`this micrograph, is 40A thick. The interfacial layer between the crystalline sil(cid:173)
`icon and the amorphous Si02 is also observable.
`Although a low threshold voltage is desirable in the gate region of a
`transistor, a large value of VT is needed between devices. For example, if a
`number of transistors are interconnected on a single Si chip, we do not want
`inversion layers to be formed inadvertently between devices (generally called
`the field). One way to avoid such parasitic channels is to increase VT in the
`field by using a very thick oxide. Figure 6-34 illustrates a transistor with a gate
`oxide 10 nm thick and a field oxide of 0.5 µm.
`
`EXAMPLE 6-4
`
`Consider an n+ polysilicon-Si02-Si p-channel device with Nd= 1016 cm- 3 and
`G; = 5 X 1010q C/cm2
`. Calculate VT for a gate oxide thickness of 0.01 µm and
`repeat for a field oxide thickness of 0.5 µm.
`
`SOLUTION
`
`Values of <l>F, O;, and Qd can be obtained from Examples 6-2 and 6-3 if
`we use appropriate signs as in Fig. 6-20a. The value of C; for the thin oxide
`case is the same as in Example 6-2. From Fig. 6-17, <l>ms = -0.25 V.
`v = -0.25 - 0.694 - 8 x 10 9 + 4.82 x 10- = -1.1 v
`34.5 X 10- s
`
`T
`
`iOi
`
`I
`1-~
`---_-__ -1/
`
`I
`
`p-Si
`
`n-channel MOSFET
`
`Polysilicon or
`metal interconnect
`
`Field
`Si02
`-0.5 µ.m
`
`'
`
`y ----- "
`
`I
`
`p-channel stop
`
`Parasitic field
`transistor
`(isolation)
`
`Adj'!cent
`MOSFET
`
`Figure 6-34
`Thin oxide in the gate rei:;bn and thick oxide in the field between t-ansistors for Vr control I rot to scale} .
`
`..
`
`Page 15 of 31
`
`

`

`field-Effect Transistors
`
`297
`
`This value corresponds to that expected from Fig. 6-20b. In the field re(cid:173)
`gion where d = 0.5 µm,
`V = -0.944 - 5·62 x rn-s = -9.1 V
`6.9 X 10-9
`
`T
`
`The value of C; can also be controlled by varying E;. A Si02 layer which
`has some N incorporated in it, leading to the formation of a silicon oxynitride,
`is often used. Such silicon oxynitrides have slightly higher E; and C; than Si02,
`with excellent interface properties. Other high dielectric constant materials
`such as Ta20 5, Zr02 and ferroelectrics (e.g. , barium-strontium-titanate) are
`also being investigated as replacements for Si02 as the gate dielectric in
`MOSFETs in order to increase C; = e/d and, therefore, the drive current of
`the MOSFET. Generally speaking, we cannot use these high dielectric con(cid:173)
`stant materials directly on the Si substrate; a very thin (-0.5 nm) interfacial
`Si02 layer is needed to achieve a low fast interface state density. It is clear
`from the expression for C; that for these high dielectric constant materials, a
`physically thicker layer, d, can be used than for Si02 and still achieve acer(cid:173)
`tain C;. This is very useful for reducing the tunneling leakage current through
`the gate dielectric, discussed in Section 6.4.7. A physically thicker layer im(cid:173)
`plies a wider tunneling barrier with a reduced tunneling probability.
`
`Threshold Adjustment by Ion Implantation. The most valuable tool for
`controlling threshold voltage is ion implantation (Section 5.1.4). Since very
`precise quantities of impurity can be introduced by this method, it is possi(cid:173)
`ble to maintain close control of VT· For example, Fig. 6- 35 illustrates a boron
`implantation through the gate oxide of a p-channel device such that the im(cid:173)
`planted peak occurs just below the Si surface. The negatively charged boron
`acceptors serve to reduce the effects of the positive depletion charge Qd. As
`a result, V r becomes less negative. Similarly, a shallow boron implant into
`the p-type substrate of an n-channel transistor can make V r positive, as re(cid:173)
`quired for an enhancement device.
`If the implantation is performed at higher energy, or into the bare Si
`instead of through an oxide layer, the impurity distribution lies deeper below
`the surface. In such cases the essentially gaussian impurity concentration
`profile cannot be approximated by a spike at the Si surface. Therefore, ef(cid:173)
`fects of distributed charge on the Qd term of Eq. (6-38) must be considered.
`Calculations of the effects on VT in this case are more complicated, and the
`shift of threshold voltage with implantation dose is often obtained empiri(cid:173)
`cally instead.
`The implantation energy required for shallow VT adjustment implants
`is low (50-100 keV), and relatively low doses are needed. A typical Vr ad(cid:173)
`justment requires only about 10 s of implantation for each wafer, and there(cid:173)
`fore this procedure is compatible with large-scale production requirements.
`
`Page 16 of 31
`
`

`

`. :.
`
`.•
`
`298
`
`Chapter 6
`
`Boron implant through gate oxide
`{before polysilicon gate formation)
`
`l G
`
`l
`
`n--poly
`
`B
`
`B R B
`
`Field
`~ i o~
`osµm
`
`/
`Gau.: .SiOz
`(O.dt to!o)
`
`n- i
`
`(a)
`
`{log)
`
`0
`
`0.01
`
`0.02
`
`y(µm)
`
`(b)
`
`Figure 6-35
`Adjustment of Vr in a p-<:hannel transistor by boron implantation: (a) boron ions ar~ implanted through
`the thin gate oxide but are abc.bed within the thick oxide regions; (b) variation of i-r1planted boron
`concentration in the gate regi-:::n-here the peak of the boron distripution lies just bebw the Si surface .
`
`. ...
`·· ..
`
`...
`· ..
`
`--·---- - - · I
`
`· .. i
`
`Page 17 of 31
`
`

`

`Fiel d-Effect Tran sistors
`
`299
`
`For the p-channel transistor of Example 6-4, calculate the boron ion dose F 8
`(B+ ions/cm2) required to reduce VT from - 1.1 V to - 0.5 V. Assume that the
`implanted acceptors form a sheet of negative charge just below the Si surface.
`
`EXAMPLE 6-5
`
`- 0.5 = -1.1 + c.
`'
`
`qFB
`
`F = 3.45 x 10-1(0.6) = 1.3 x 1012 cm-2
`1.6 X 10- 19
`B
`
`SOLUTION
`
`For a beam current of 10 µA scanned over a 650-cm2 target area,
`10- 5(C/s)
`- - -2...;....t( ) = 1.3 x 1012 (ions/cm2) x 1.6 x 10-19(C/ion)
`650cm
`
`The implant time is t = 13.5 s.
`
`If the implantation is continued to higher doses, VT can be moved past
`zero to the depletion-mode condition (Fig. 6-36). This capability provides con(cid:173)
`siderable flexibility to the integrated-circuit designer, by allowing enhancement(cid:173)
`and depletion-mode devices to be incorporated on the same chip. For example,
`a depletion-mode transistor can be used instead of a resistor as a load element
`for the enhancement device. Thus an array of MOS transistors can be fabricat(cid:173)
`ed in an IC layout, with some adjusted by implantation to have the desired en(cid:173)
`hancement mode VT and others implanted to become depletion loads.
`As mentioned above, VT control is important not only in the MOSFETs
`but also in the isolation or field regions. In addition to using a thick field
`oxide, we can do a channel stop implant (so called because it stops turning on
`
`+1
`
`+0.5
`
`Depletion
`
`0
`~ -0.5
`
`~
`f..
`:::,..
`
`-1
`
`-1.5
`
`-2
`
`Enhancement
`
`2
`
`10
`12
`8
`6
`4
`B+ dose (10 12 ions/cm2)
`
`Figure 6-36
`Typical variation
`of Vr for a
`p-channel device
`with increased im(cid:173)
`planted boron
`dose. The origi(cid:173)
`nally enhance(cid:173)
`ment p-channel
`transistor
`becomes a
`depletion-mode
`device (Vr > 0) by
`sufficient B
`implantation .
`
`Page 18 of 31
`
`

`

`..
`
`' ~
`
`300
`
`Chapter 6
`
`a parasitic channel in the isolation regions) selectively in the isolation regions
`under the field oxide (Fig. 6--34 ). Generally, a B channel stop implant is used for
`n-channel devices. (It must be noted that such an acceptor implant will raise the
`field thresholds for n-channel MOSFETs made in a p-substrate, but will decrease
`the field thresholds for p-MOSFETs made in an n-substrate ).
`
`6.5.6 Substrate Bias Effects
`
`In the derivation of Eq. (6-49) for current along the channel, we assumed that
`the source S was connected to the substrate B (Fig. 6-27). In fact, it is possi(cid:173)
`ble to apply a voltage between S and B (Fig. 6-37). With a reverse bias be(cid:173)
`tween the substrate and the source (VB negative for an n-channel device), the
`depletion region is widened and the threshold gate voltage required to
`achieve inversion must be increased to accommodate the larger Qd. A sim(cid:173)
`plified view of the result is that Wis widened uniformly along the channel,
`so that Eq. (6-32) should be changed to
`Q~ = -[2e5qN 0(2<1>F - V B)] 112
`The change in threshold voltage due to the substrate bias is
`
`(6-61)
`
`6..Vr = ~ [(2<h - VB)1/2 -
`If the substrate bias VB is much larger than 2<1>F (typically -0.6 V), the
`threshold voltage is dominated by VB and
`
`(2<1>F)1f2]
`
`(6-62)
`
`I
`
`6.Vr=
`
`v'2'°-/f.Na
`(-VB) 1f2
`C
`
`I
`
`(nchannel)
`
`(6-63)
`
`where V8 will be negative for then-channel case.As the substrate bias is in(cid:173)
`creased, the threshold voltage becomes more positive. The effect of this bias
`becomes more dramatic as the substrate doping is increased, since 6. VT is
`also proportional to VN;. For a p-channel device the bulk-to-source voltage
`VB is positive to achieve a reverse bias, and the approximate change 6. VT for
`VB~ 2<1>Fis
`
`Li V r =
`
`Y2e.5qN11
`C
`r
`
`112
`V 8
`
`(p channel)
`
`(6-64)
`
`Thus the p-channel threshold voltage becomes more negative with sub(cid:173)
`strate bias.
`The substrate bias effect (also called the body effect) increases VT for
`either type of device. This effect can be used to raise the threshold voltage
`of a marginally enhancement device (VT= 0) to a somewhat larger and more
`manageable value. This can be an asset for n-channel devices particularly
`(see Fig. 6--20). The effect can present problems, however, in MOS integrat(cid:173)
`ed circuits for which it is impractical to connect each source region to the
`
`Page 19 of 31
`
`

`

`Field-Effect Transistors
`
`301
`
`1.0
`
`Slope =
`
`E;/ d
`
`d=80 A
`N 0 =1.5 x 1017 cm- 3
`
`p-Si
`
`o~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`
`0.5
`
`1.0
`
`1.5
`
`Figure 6-37
`Threshold voltage dependence on substrate bias resulting from application of a voltage Vs From the sub(cid:173)
`strate (i.e., bulk) to the source. For n channel, Vs must be zero or negative to avoid forward bias of the
`source junction. For p channel, Vs must be zero or positive.
`
`substrate. In these cases, possible VT shifts due to the body effect must be
`taken into account in the circuit design.
`
`6.5.7 Subthreshold Characteristics
`
`If we look at the drain current expression (Eq. 6-53), it appears that the cur(cid:173)
`rent abruptly goes to zero as soon as Va is reduced to VT· In reality, there is still
`some drain conduction below threshold, and this is known as subthreshold
`
`Page 20 of 31
`
`

`

`302
`
`Cha pter 6
`
`conduction. This current is due to weak inversion in the channel between flat(cid:173)
`band and threshold (for bandbending between zero and 2<h), which leads to
`a diffusion current from source to drain. The drain current in the subthreshold
`region is equal to
`
`(6-65)
`
`where
`
`_ [
`1 +
`c,. -
`
`Ci1 + C1,]
`c.
`
`I
`
`It can be seen that In depends exponentially on gate bias, V c· However,
`VD has little influence once VD exceeds a few kT/q. Obviously, if we plot
`ln I 0 as a function of gate bias VG• we should get a linear behavior in the
`subthreshold regime, as shown in Fig. 6-38a. The slope of this line (or more
`precisely the reciprocal of the slope) is known as the subthreshold slope, S,
`which has typical values of -70 mV/decade at room temperature for state(cid:173)
`of-the-art MOSFETs. This means that a change in the input V c of 70 m V
`will change the output I 0 by an order of magnitude. Clearly, the smaller
`the value of S, the better the transistor is as a switch. A small value of S
`means a small change in the input bias can modulate the output current
`considerably.
`It can be shown that the expression for S is given by
`
`Ctt + C;,]
`
`C;
`
`(6- 66)
`
`kT[
`dVc
`d
`2·3 q 1 +
`S = d(log TD) = Jn 10 d(ln 10
`Here, the factor In I 0 ( = 2.3) is introduced to change from log 10 to
`natural logarithm, In. This equation can be understood by looking at the
`electrical equivalent circuit of the MOSFET in terms of the capacitors (Fig.
`6-38b ). Between the gate and the substrate, we find the gate capacitance,
`C;, in series with the parallel combination of the depletion capacitance in
`the channel, C", and the fast interface state capacitance, C;1 = qD;r. The ex(cid:173)
`pression in brackets in Eq. (6-66) is simply the capacitor divider ratio which
`tells us what fraction of the applied gate bias, V 0 , appears at the Si-Si02 in(cid:173)
`terface as the surface potential. Ultimately, it is the surface potential that
`is responsible for modulating the barrier between source and drain, and
`therefore the drain current. Hence, S is a measure of the efficacy of the
`gate potential in modulating In. From Eq. (6-66) , we observe that Sis im(cid:173)
`proved by reducing the gate oxide thickness, which is reasonable because
`if the gate electrode is closer to the channel, the gate control is obviously
`better. The value of S is higher for heavy channel doping (which increases
`the depletion capacitance) or