(12) United States Patent
`Osada et al.
`
`USOO6677649B2
`US 6,677,649 B2
`*Jan. 13, 2004
`
`(10) Patent No.:
`(45) Date of Patent:
`
`(54) SRAM CELLS WITH TWO P-WELL
`STRUCTURE
`
`(75) Inventors: Kenichi Osada, Kawasaki (JP);
`Masataka Minami, Hino (JP); Shuji
`Ikeda, Koganei (JP); Koichiro
`Ishibashi, Warabi (JP)
`(73) Assignee: Hitachi, Ltd., Tokyo (JP)
`
`5,744,844 A 4/1998 Higuchi
`5,930,163 A * 7/1999 Hara et al................... 365/154
`6,147,385 A 11/2000 Kim et al.
`6,160,298 A 12/2000 Ohkubo ...................... 257/393
`6,476,424 B1 11/2002 Ishida
`
`FOREIGN PATENT DOCUMENTS
`10178110
`6/1998
`10-223 777
`* 8/1998 ....... HO1 L/21/8244
`
`JP
`JP
`
`(*) Notice:
`
`This patent issued on a continued pros
`ecution application filed under 37 CFR
`1.53(d), and is subject to the twenty year
`patent term provisions of 35 U.S.C.
`154(a)(2).
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/565,535
`(22) Filed:
`May 5, 2000
`
`(65)
`
`Prior Publication Data
`US 2002/0117722 A1 Aug. 29, 2002
`2
`Foreign Application Priority Data
`(30)
`May 12, 1999
`(JP) ........................................... 11-130945
`(51) Int. Cl." .......................... H01L 29/76; H01L 27/11
`(52) U.S. Cl. ........................ 257/379; 257/393; 257/904
`(58) Field of Search ................................. 257/393,379,
`257/903, 904, 401
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`5,072.286 A 12/1991 Minami et al.
`
`* cited by examiner
`
`Primary Examiner-Ori Nadav
`(74) Attorney, Agent, or Firm-Antonelli, Terry, Stout &
`Kraus, LLP
`ABSTRACT
`(57)
`Prior known static random access memory (SRAM) cells are
`required that a diffusion layer be bent into a key-like shape
`in order to make electrical contact with a Substrate with a
`P-type well region formed therein, which would result in a
`decrease in asymmetry leading to occurrence of a problem
`as to the difficulty in micro-patterning. To avoid this
`problem, the P-type well region in which an inverter making
`up an SRAM cell is formed is subdivided into two portions,
`which are disposed on the opposite Sides of an N-type well
`region NW1 and are formed so that a diffusion layer forming
`a transistor has no curvature while causing the layout
`direction to run in a direction parallel to well boundary lines
`and bit lines. At intermediate locations of an array, regions
`for use in Supplying power to the Substrate are formed in
`parallel to word lines in Such a manner that one regions is
`provided per group of thirty two memory cell rows or sixty
`four cell rows.
`
`7 Claims, 15 Drawing Sheets
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`Qualcomm Incorporated
`EX1009
`Page 1 of 23
`
`

`

`U.S. Patent
`
`Jan. 13, 2004
`
`Sheet 1 of 15
`
`US 6,677,649 B2
`
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`Page 2 of 23
`
`

`

`US. Patent
`
`Jan. 13, 2004
`
`Sheet 2 0f 15
`
`US 6,677,649 132
`
`FIG.3
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`Page 3 of 23
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`Page 3 of 23
`
`
`
`
`
`
`

`

`U.S. Patent
`
`Jan. 13, 2004
`
`Sheet 3 of 15
`
`US 6,677,649 B2
`
`f3 TN3
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`Page 4 of 23
`
`

`

`US. Patent
`
`Jan. 13, 2004
`
`Sheet 4 0f 15
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`US 6,677,649 B2
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`Page 5 of 23
`
`Page 5 of 23
`
`

`

`U.S. Patent
`
`Jan. 13, 2004
`
`Sheet 5 of 15
`
`US 6,677,649 B2
`
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`Page 6 of 23
`
`

`

`U.S. Patent
`
`Jan. 13, 2004
`
`Sheet 6 of 15
`
`US 6,677,649 B2
`
`FIG.O
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`Page 7 of 23
`
`

`

`U.S. Patent
`
`Jan. 13, 2004
`
`Sheet 7 of 15
`
`US 6,677,649 B2
`
`
`
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`
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`
`Page 8 of 23
`
`

`

`U.S. Patent
`US. Patent
`
`Jan. 13, 2004
`Jan. 13, 2004
`
`Sheet 8 of 15
`Sheet 8 0f 15
`
`US 6,677,649 B2
`US 6,677,649 B2
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`Page 9 of 23
`
`Page 9 of 23
`
`

`

`US. Patent
`
`Jan. 13, 2004
`
`Sheet 9 0f 15
`
`US 6,677,649 B2
`
`FIG.13
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`Page 10 of 23
`
`Page 10 of 23
`
`

`

`U.S. Patent
`
`Jan. 13, 2004
`
`Sheet 10 Of 15
`
`US 6,677,649 B2
`
`FIG.15
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`Page 11 of 23
`
`

`

`U.S. Patent
`
`Jan. 13, 2004
`
`Sheet 11 of 15
`
`US 6,677,649 B2
`
`
`
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`Page 12 of 23
`
`

`

`U.S. Patent
`
`Jan. 13, 2004
`
`Sheet 12 of 15
`
`US 6,677,649 B2
`
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`Page 13 of 23
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`

`

`U.S. Patent
`
`Jan. 13, 2004
`
`Sheet 13 of 15
`
`US 6,677,649 B2
`
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`Page 14 of 23
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`

`

`U.S. Patent
`
`Jan. 13, 2004
`
`Sheet 14 of 15
`
`US 6,677,649 B2
`
`1 P--
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`Page 15 of 23
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`

`

`U.S. Patent
`
`Jan. 13, 2004
`
`Sheet 15 of 15
`
`US 6,677,649 B2
`
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`Page 16 of 23
`
`

`

`1
`SRAM CELLS WITH TWO P-WELL
`STRUCTURE
`
`US 6,677,649 B2
`
`2
`also a gate connected to a word line, and a fourth N-channel
`MOS transistor having a Source connected to the output
`terminal of Said Second inverter, a drain connected to a
`Second bit line, and a gate connected to a word line, wherein
`the first and third N-channel MOS transistors are formed in
`a first P-type well region, wherein the diffusion layer has no
`curved or bent portions, while letting the direction of the
`layout be parallel to the boundary with respect to the first
`N-well region with the first and second P-channel MOS
`transistors formed therein, and wherein Said Second and
`fourth N-channel MOS transistors are formed in the second
`P-type well region, whose diffusion layer has no bent
`portions, while letting the layout direction be parallel to the
`boundary with respect to the first N-well region with the first
`and second P-channel MOS transistors formed therein.
`The diffusion layer is arranged to have its outer shape,
`which mainly consists of Straight line Segments including
`the longest Straight line portion, which lies parallel to the
`boundary with respect to the first N-well region with the first
`and second P-channel MOS transistors formed therein, and
`Simultaneously in the case of defining a Straight line acting
`as the center line extending parallel to Such a boundary, the
`longest line portion is in linear Symmetry with Said center
`line; the second and fourth N-channel MOS transistors are
`formed in the second P-well region, whose diffusion layer is
`mainly arranged by Straight line Segments including its
`longest Straight line portion that is parallel to the boundary
`with respect to the first N-well region with the first and
`Second P-channel MOS transistors formed therein while
`allowing, when defining a Straight line for use as the center
`line extending parallel to Such a boundary, the line portion
`to be linearly Symmetrical to the center line. At this time, in
`the case of employing the linear Symmetrization Scheme,
`complete linear Symmetry will not always be required.
`Alternatively, slight nonsymmetry may also be permissible
`on a case-by-case basis. This nonsymmetry results from
`modifying the diffusion layer to have a shape in which its
`portions on the right and left Sides of the center line are
`Substantially the same in area as each other, by way of
`example.
`In accordance with another aspect of this invention, a first
`polycrystalline Silicon lead layer for use as the gate of Said
`third N-channel MOS transistor and a second polycrystalline
`Silicon lead layer for use as the gate of Said first P-channel
`MOS transistor, and also as the gate of said first N-channel
`MOS transistor, are disposed in parallel to each other,
`wherein a third polycrystalline Silicon lead layer for use as
`the gate of said fourth N-channel MOS transistor, and a
`fourth polycrystal-line Silicon lead layer for use as the gate
`of said second N-channel MOS transistor, and also as the
`gate of said second P-channel MOS transistor are disposed
`in parallel to each other, and wherein the first and third
`polycrystalline Silicon lead layers are connected via a con
`tact to a Second layer which Serves as a metal lead layer
`constituting the word lines.
`In accordance with another aspect of the invention, the
`input terminal of Said first inverter and the output terminal
`of Said Second inverter may be electrically connected
`together at a contact, whereas the input terminal of Said
`Second inverter and the output terminal of Said first inverter
`are electrically connected together at a contact.
`In accordance with yet another aspect of the invention, a
`power Supply line connected to the first and Second bit lines,
`the Sources of said first and second P-channel MOS
`transistors, and a ground line connected to the Sources of
`said first and second N-channel MOS transistors may be
`formed of a third layer Serving as a metal lead layer lying
`parallel to a diffusion layer.
`
`15
`
`BACKGROUND OF THE INVENTION
`The present invention relates generally to Semiconductor
`integrated circuit devices and, more particularly, to layout
`schemes of static random access memory (SRAM) cells. The
`invention also relates to Semiconductor memory devices
`using Such cells.
`One-port SRAM cells with complementary metal oxide
`semiconductor (CMOS) configurations are typically
`designed So that each cell consists essentially of Six Separate
`transistors. An exemplary layout of Such cells has been
`disclosed, for example, in JP-A-10-178110 (laid open on
`Jun. 30, 1998).
`In the previously known SRAM cell layout, a semicon
`ductive well region of P type conductivity with inverters
`formed therein is subdivided into two subregions, which are
`disposed on the opposite sides of an. N-type well region
`while permitting a well boundary line to extend in a direc
`tion parallel to the bit lines.
`The quest for higher integration and ultra-fine patterning
`techniques in modern memory devices requires an optical
`exposure apparatus or equipment to decrease the wave
`length of the beams used therein. To this end, the equipment
`is designed to employ exposure beams of Shorter
`wavelengths, which have advanced from G line to I line, and
`then further to excimer lasers. Unfortunately, the require
`ments for micro-patterning architectures have grown more
`rapidly than technological advance in the trend of shortening
`wavelengths in Such equipment. In recent years, it has been
`Strictly required that micropatterning be done with the
`minimum device-feature length that shrinks to less than or
`equal to the wavelength of the exposure beam used. This
`minimum feature length shrinkage would result in a layout
`of IC components-particularly, memory cells-becoming
`more complicated in planar shape, which necessitates the
`use of irregular polygonal layout patterns including key
`shaped components, in order to achieve the intended con
`figuration of an on-chip circuitry with enhanced accuracy.
`This makes it impossible, or at least very difficult, to
`microfabricate ultrafine layout patterns while disadvanta
`geously Serving as the cause of the destruction of the
`Symmetry of memory cells.
`Regrettably, the prior art approach is associated with a
`need to curve or bend a diffusion layer into a complicated
`key-like shape for the purpose of making electrical contact
`with a substrate of the P-type well region. Thus, the prior art
`suffers from the problem of the degradation of the symme
`trization of the cell layout pattern, making the Successful
`achievement of microfabrication architectures for higher
`integration densities difficult.
`SUMMARY OF THE INVENTION
`In accordance with one aspect of the present invention, a
`Semiconductor device is provided which comprises a first
`inverter including a first N-channel metal oxide Semicon
`ductor MOS transistor, and a first channel MOS transistor, a
`second inverter including a second N-channel MOS transis
`tor and a second P-channel MOS transistor with an input
`terminal being connected to an output terminal of the first
`inverter and with an output terminal being connected to an
`input terminal of said first inverter, a third N-channel MOS
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`transistor having a Source connected to the output terminal
`of Said first inverter, a drain connected to a first bit line, and
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`In accordance with a still another aspect of the invention,
`the first bit line formed of said third layer serving as a metal
`lead layer may be arranged So that it is between a power
`Supply line formed of Said third layer Serving as a lead layer
`and a ground line as connected to the Source of Said first
`N-channel MOS transistor formed of said third layer serving
`as a metal lead layer whereas the Second bit line formed of
`Said third layer Serving as a metal lead layer is between a
`power Supply line formed of Said third layer Serving as a
`metal lead layer and a ground line as connected to the Source
`of said second N-channel MOS transistor formed of said
`third layer Serving as a metal lead layer.
`In accordance with another aspect of the invention, the
`first and Second bit lines and a power Supply line connected
`to the Sources of said first and second P-channel MOS
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`transistors may be formed of a Second layer Serving as a
`metal lead layer, wherein word lines are formed of a third
`layer of metal lead layer, and wherein a ground line con
`nected to the Sources of Said first and Second N-channel
`MOS transistors is formed of the third layer and second layer
`Serving as a metal lead layer.
`In accordance with a still another aspect of the invention,
`memory cells are laid out into the form of an array, wherein
`contacts to a Substrate of a P-type well region and a contact
`to a Substrate of an N-type well region are linearly disposed
`within the array and at upper and lower portions of the array
`in a direction parallel to the word lines. Although the above
`is an example which causes two separate P-well regions to
`be disposed on the opposite sides of an N-Well region, two
`N-Well regions may be disposed on the opposite Sides of a
`P-well region when the need arises.
`In accordance with yet another aspect of the invention, a
`Semiconductor device is provided which comprises a plu
`rality of memory arrays, each including an array of memory
`cells having at least an N-type well region and a P-type well
`region, and at least one intermediate region between the
`memory arrays, wherein the N-type well region and P-type
`well region define therebetween a boundary with at least one
`Straight line portion, and wherein a diffusion layer is formed
`in both the N-type well region and the P-type well region to
`have a planar shape of either (1) a rectangle having long
`sides extending parallel to said Straight line portion, or (2) a
`shape resulting from letting a plurality of rectangles having
`long Sides extending parallel to the Straight line portion be
`combined together via respective short Sides thereof; or
`alternatively, (1) a rectangle having long Sides parallel to
`said straight line portion, or (2) a shape resulting from letting
`a plurality of rectangles having long Sides parallel to Said
`Straight line portion be combined together, causing them to
`extend in the direction of the Straight line.
`At least in the memory array regions, bit lines are laid out
`in a direction parallel to the Straight line portion, whereas
`word lines are disposed in a direction perpendicular to the
`Straight portion. Preferably, in the intermediate region, at
`least one type of electrical lead is railed in a direction at right
`angles to the Straight portion, and a lead (e.g. contact) is also
`formed with the purpose of making electrical contact
`between a power Supply Voltage lead and the diffusion layer
`as formed in the N-well region or P-well region. This lead
`may include a power Supply lead, ground lead, or other
`potential leads.
`The invention is particularly useful for those Semicon
`ductor memory devices having Static RAM memory cells
`each consisting essentially of six separate transistors.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a diagram showing an SRAM cell in accordance
`with Embodiment 1 of the present invention, for explaining
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`a layout pattern of those contacts for connection between
`MOS transistors and those for connecting between MOS
`transistors and metal lead layers.
`FIG. 2 is a diagram showing a layout of via holes of
`SRAM cells for connection between multilayered metal
`leads in accordance with Embodiment 1 of this invention.
`FIG. 3 is a diagram showing a layout of memory cells and
`their associated peripheral circuitry in accordance with
`Embodiment 2 of the invention.
`FIG. 4 is a diagram showing an SRAM cell in accordance
`with Embodiment 3 of the invention, for explaining a layout
`of those contacts for connection between MOS transistors
`and those for connection between MOS transistors and metal
`lead layers.
`FIG. 5 is a diagram showing a layout of via holes of
`SRAM cells for connection between multilayered metal
`leads in accordance with Embodiment 3 of the invention.
`FIG. 6 is a diagram showing an SRAM cell in accordance
`with Embodiment 4 of the invention, for explaining a layout
`of those contacts for connection between MOS transistors
`and those for connection between MOS transistors and metal
`lead layers.
`FIG. 7 is a diagram showing a layout of via holes of
`SRAM cells for connection between muitilayered metal
`leads in accordance with Embodiment 3 of the invention.
`FIG. 8 is a diagram showing an SRAM cell in accordance
`with Embodiment 5 of the invention, for explaining a layout
`of those contacts for connection between MOS transistors
`and those for connection between MOS transistors and metal
`lead layers.
`FIG. 9 is a diagram showing a layout of via holes of
`SRAM cells for connection between multilayered metal
`leads in accordance with Embodiment 5 of the invention.
`FIG. 10 is a diagram showing an SRAM cell in accor
`dance with Embodiment 6 of the invention, for explaining a
`layout of those contacts for connection between MOS tran
`sistors and those for connection between MOS transistors
`and metal lead layers.
`FIG. 11 is a diagram showing a layout of via holes of
`SRAM cells for connection between multilayered metal
`leads in accordance with Embodiment 6 of the invention.
`FIGS. 12a to 12fare diagrams illustrating in cross-section
`Some of major process Steps in the manufacture of the
`Semiconductor device in accordance with Embodiment 6 of
`the invention.
`FIG. 13 is a diagram showing an SRAM cell in accor
`dance with Embodiment 7 of the invention, for explaining a
`layout of those contacts for connection between MOS tran
`sistors and those for connection between MOS transistors
`and metal lead layers.
`FIG. 14 is a diagram showing a layout of via holes of
`SRAM cells for use in connecting between multilayered
`metal leads in accordance with Embodiment 7 of the inven
`tion.
`FIG. 15 is a diagram showing an SRAM cell in accor
`dance with Embodiment 8 of the invention, for explaining a
`layout of those contacts for connection between MOS tran
`sistors and those for connection between MOS transistors
`and metal lead layers.
`FIG. 16 is a diagram showing a layout of via holes of
`SRAM cells for connection between multilayered metal
`leads in accordance with Embodiment 8 of the invention.
`FIG. 17 is a sectional view of a semiconductor device in
`accordance with Embodiment 8 of the invention.
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`FIGS.18a to 18fare diagrams illustrating in cross-section
`Some of major proceSS Steps in the manufacture of a Semi
`conductor device in accordance with Embodiment 9 of the
`invention.
`FIGS. 19a to 19g are diagrams illustrating in cross
`Section Some of major process Steps in the manufacture of a
`semiconductor device in accordance with Embodiment 10 of
`the invention.
`
`DETAILED DESCRIPTION OF EMBODIMENTS
`Several preferred embodiments of the semiconductor
`memory device in accordance with the present invention
`will be explained with reference to the accompanying draw
`ings below.
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`connect lead layer FG1 to be used as the gate electrode of the
`N-channel MOS transistor TN1 and the P-channel MOS
`transistor TP1 and a polycrystalline Silicon interconnect lead
`layer FG2 to be used as the gate electrode of the N-channel
`MOS transistor TN2 and the P-channel MOS transistor TP2,
`plus the polycrystalline silicon lead layers (FG3, FG4), are
`disposed in parallel to the word lines.
`The N-channel MOS transistor TN1 has its source elec
`trode connected to a ground potential line VSS1 that is
`formed of the third layer Serving as a metal lead layer,
`whereas a Source electrode of the N-channel MOS transistor
`TN2 is connected to a ground line VSS2 that is formed of the
`third layer Serving as a metal lead layer. In addition, Source
`electrodes of the P-channel MOS transistors (TP1, TP2) are
`connected to a power Supply Voltage line Vcc1 which is
`formed of the third layer Serving as a metal lead layer.
`The bit line BL1 is located midway between the power
`Supply Voltage line Vcc1 and ground line VSS1, whereas bit
`line BL2 is between the Supply Voltage line Vcc1 and ground
`line VSS2. This structure makes it possible to reduce croSS
`couple noises occurring between bit lines, which advanta
`geously lowerS Voltages while increasing operation Speeds.
`In addition, it is considered that, in case a contact is
`formed on an in layer through the partial cutaway of Side
`Spacers during the etching of contact holes, a leakage current
`from the contact via the n layer to the Substrate may be
`produced. When a contact is formed for connection between
`a polycrystalline Silicon lead layer and a diffusion layer, the
`distance between the diffusion layer LP2 and polycrystalline
`silicon lead layer FG1 should be greater than the length of
`a side Spacer to thereby eliminate the formation of an in layer
`on the polycrystalline silicon lead layer FG1 side of the
`diffusion layer LP2, which in turn makes it possible to
`prevent a flow of leakage current.
`Embodiment 2
`Turning to FIG. 3, an exemplary case is shown where the
`memory cells MC of Embodiment 1 are laid out into the
`form of an array. Symbols used herein are the same as those
`indicated at the lower part of FIG. 2.
`The memory cells MC are organized into an array of 256
`rows and 128 columns, by way of example. In view of the
`fact that these memory cells in Embodiment 1 are shorter in
`length in the longitudinal direction of the bit lines, the total
`length of the 256 rows of memory cells along the bit lines
`is shorter than that of prior art devices, thus increasing
`resultant operation Speeds. Neighboring memory cells MC
`are disposed in linear Symmetry with respect to a “y” axis
`whereas upper and lower adjacent memory cells MC are in
`linear Symmetry with an “X” axis. In addition, Specified
`regions ST for use in Supplying more than one power Supply
`Voltage to the Substrate are formed at the intermediate part
`of the array in Such a manner that the regions ST extend
`parallel to word lines WD. One example is that the regions
`ST are laid out in units of 32-row groups. Another example
`is that regions ST are disposed in units of 64-row groups.
`An electrical lead Vbn for Supplying a Voltage potential to
`the P-well regions (PW1, PW2) and a lead Vbp for supply
`ing a voltage to the N-well region NW1 are formed to lie
`parallel to word lines. The lead Vbn may be coupled to the
`ground potential VSS or, alternatively, any Voltage may be
`applied thereto which is potentially different from the
`ground VSS. The lead Vbp may be coupled to the power
`Supply Voltage Vcc or, alternatively, any Voltages potentially
`different from the Vcc may be applied thereto.
`Note that in each region ST, a power Supply Voltage line
`Vcc for potentially “reinforcing a power Supply Voltage
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`Embodiment 1
`Referring to FIGS. 1 and 2, SRAM cell layout MC
`embodying the invention. FIG. 1 illustrates well regions and
`diffusion layerS plus a polycrystalline Silicon interconnect
`lead layer, as well as contacts, all of which are formed in or
`over a Semiconductor Substrate FIG. 2 depicts a first layer
`Serving as a metal lead layer, via holes 1, a Second layer
`Serving as a metal lead layer, via holes 2, and a third layer
`serving as a metal lead layer. Symbols used in FIGS. 1 and
`2 are indicated at the lower part of FIG. 2.
`An N-channel type MOS transistor TN1 formed in a
`P-type semiconductive well region PW1 and a P-channel
`type MOS transistor TP1 formed in an N-type well region
`NW1 constitute an inverter INV1. In addition, an N-channel
`MOS transistor TN2 formed in P-type well region PW2 and
`a P-channel MOS transistor TP2 formed in N-type well
`region NW1 constitute an inverter INV2.
`An output node of the inverter INVL is electrically
`connected by a contact SC1 to an input node of the inverter
`INV2. An output of the inverter INV2 is electrically con
`nected via a contact SC2 to an input of the inverter INV1.
`An N-channel MOS transistor TN3 has a drain electrode
`connected to a bit line BL1, a Source electrode connected to
`a drain of the N-channel MOS transistor TN1, and a gate
`electrode connected to a word line WD. Similarly, an
`N-channel MOS transistor TN4 has a drain electrode con
`nected to a bit line BL2, a Source electrode connected to a
`drain of the N-channel MOS transistor TN2, and a gate
`electrode connected to a word line WD.
`The N-channel MOS transistor TN1 and the N-channel
`MOS transistor TN3 are formed over a diffusion layer LN1,
`whereas the N-channel MOS transistor TN2 and the
`N-channel MOS transistor TN4 are formed over a diffusion
`layer LN2. The P-channel MOS transistor TP1 is formed
`over a diffusion layer LP1, whereas the P-channel MOS
`transistor TP2 is formed over a diffusion layer LP2.
`As the diffusion layers (LN1, LN2, LP1, LP2) are straight
`lines with no curved portions, any pattern correction at the
`folded portions is no longer necessary, resulting in the
`balance between nodes being improved. In case the memory
`cells are laid out into the form of an array, the diffusion
`layers become four Separate Straight lines extending parallel
`to the bit lines (BL1, BL2).
`In addition, a polycrystalline Silicon interconnect lead
`layer FG3 to be used the gate electrode of the N-channel
`MOS transistor TN3 and a polycrystalline silicon lead layer
`FG4 to be used as the gate electrode of the N-channel MOS
`transistor TN4 are connected to word lines WL, which are
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`formed of the Second metal lead layer in a vertical direction
`to the bit lines (BL1, BL2) A polycrystalline silicon inter
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`line Vcc1 is formed in parallel to word lines while, allowing
`a ground potential line VSS for potentially reinforcing
`ground potentials (VSS1, Vss2) to be formed in parallel to the
`word lines.
`Also note that the ground lines (VSS1, VSS2) are disposed
`in a direction perpendicular to the word lines WD, whereby
`upon Selecting a single word line a Voltage potential is
`Supplied from the pair of ground lines to a respective one of
`those memory cells operatively associated with this Selected
`word line So that any possible noises occurring at Such
`Voltage lines are reduced, thereby advantageously Speeding
`an acceSS operation while potentially reducing any Voltages
`concerned.
`Furthermore, the memory cells MC used are great in
`width in the word line direction so that the layout design of
`Sense amplifiers AMP is made easier, thereby avoiding the
`need to lay out one Sense amplifier for two adjacent columns
`of memory cells, which in turn makes it possible to permit
`one Sense amplifier to be laid out at each column.
`Additionally, a word line driver circuit wadrv becomes fiat
`in layout as compared to previously prior known ones.
`Embodiment 3
`FIGS. 4 and 5 show a SRAM cell layout MC2 in
`accordance with Embodiment 3. Symbols as used in FIGS.
`4-5 are the same as those in FIG. 2. Memory cell MC2 of
`Embodiment 3 is similar to the memory cell MC of Embodi
`ment 1, with the exception that, as compared to Embodiment
`1, in which the diffusion layer (LN1, LN2) is formed into a
`"T"-like planar shape, which resembles a Japanese battle
`dore plate called “hagoita,” the diffusion layer (LN3, LN4)
`of Embodiment 4 is of a rectangular shape, and the contacts
`(SC1, SC2) are replaced with contacts (SC3, SC4) in the first
`layer Serving as metal lead layers (M11, M12).
`To attain Stability, memory cells are typically designed So
`that the gate width of the N-channel MOS transistors (TN1,
`TN2) is one and a half times greater than that of the
`N-channel MOS transistors (TN3, TN4) However, in this
`case, the shape of the diffusion layerS resembles a T-like
`planar shape, as shown in Embodiment 1, which in turn
`requires extra techniques, including pattern correction pro
`cedures such as optical proximity effect correction (OPC)
`processes. Additionally, this would result in the degradation
`of the balance between transistors. In contrast, Embodiment
`3 is such that t