A Novel 6T-SRAM Cell Technology Designed with Rectangular Patterns
`Scalable beyond 0.18 pm Generation and Desirable for Ultra High Speed Operation
`M. Ishida, T. Kawakami, A. Tsuji, N. Kawamoto, M. Motoyoshi and N. Ouchi
`System LSI Division, Sony Corporation, 4- 14- 1, Asahi-cho, Atsugi-shi, Kanagawa, 243-0014, Japan
`
`Abstract
`
`A novel 6T-SRAM cell layout designed with rectangular
`patterns has been developed. Employing this layout, 4.13 pm2
`and 5.33 pm2 cells with word transistor width of 0.25 pm and
`0.75 pm are obtained, respectively, based on the 0.20 pm rule.
`Among the various layouts of 6T-SRAM cells, this layout
`provides minimum cell size and the smallest bit line
`capacitance with word transistor width over 0.75 ym for the
`ultra high speed operation. It
`is also demonstrated
`quantitatively that the optimized SRAM cell layout for high
`speed use is different from that for low power use. The cell
`layout proposed also provides the excellent scalability beyond
`0.18 pm generation due to its highly simplified pattern design.
`
`Introduction
`
`In recent years, it is reported that the speed of CPU and DSP
`has been improved up to giga hertz operation [l]. In such
`situation, the most important role of SRAM for such high
`performance devices is the high speed operation.
`Fig.1 shows contents of SRAM access time determined from
`our products. It mainly consists of (i) decoding delay and
`sensing delay, and (ii) bit line (BL) delay. Decoding delay and
`sensing delay are resulted from the operation in peripheral
`circuits of SRAM. These delays depend on gate delay of
`peripheral circuits. On the other hand, BL delay is resulted
`from the operation in the memory cell. This delay depends on
`memory cell current to pull down BL. Therefore, to achieve
`the high speed SRAM operation, (1) the reduction of gate
`delay in peripheral circuits and (2) the increase of memory cell
`current that means the increase of the word transistor (WT)
`size and the reduction of BL capacitance are required.
`The above (l), the reduction of gate delay, has been widely
`studied. On the contrary, as for the memory cell technology,
`the cell size reduction has been reported [2-51, but the increase
`of WT size and the reduction of BL capacitance for the high
`speed operation have not been reported quantitatively. In this
`paper, an optimized SRAM cell layout which will satisfy these
`requirements consistently is proposed and is verified from
`experiments.
`
`Analysis on cell design
`
`SRAM cell designs are essentially categorized into four
`variations for possible combinations of two inverters as shown
`in Table-1. All SRAM cells reported with the sub-0.20 pm rule
`are categorized into type-la, 2 and 3 as are described in Table-
`2 [2-51. As a variation of WT layout of type-la, type-lb is also
`proposed [6]. The smallest and secondly smallest cells
`previous reported were type-2 and 3. Cell size of type-la is
`almost equal to that of type-2.
`The disadvantages related with these conventional cells are
`
`as follows. (i) Complicated cell design results in the corner
`rounding and deformation of patterns. And transistor size is not
`constant due to the overlay shift in lithography. (ii) The
`spacing between each wiring pattern is designed with minimum
`spacing rule. Since it requires continuous improvements of
`resolution and NA in lithography for the further scaling, some
`new idea of more simplified pattern definition is desired.
`A new type-lb cell is proposed as shown in Figs.2 and 3 to
`resolve these problems. Significant geometrical features of this
`cell are (i) highly simplified rectangular pattern design and (ii)
`wide spacing between each wiring pattern. As the result of this
`design, no corner rounding of patterns nor irregularity. of
`transistor size caused by the overlay shift are achieved. These
`features will be important even in design rules in future.
`Furthermore, the cell is 4.13 pm2, which is comparable to
`the best data available for 0.2 ym generation, employing the
`minimum spacing not of 0.2 pm but of 0.42 pm in the active
`area and the poly Si layers, and of 0.69 pm in each local wiring
`layer. This wide spacing design is also desirable for the scaling
`in future.
`
`Sample preparation and design rule verification
`Proposed type-lb cell is designed with the 0.20 pm rule for
`electrical evaluation as shown in Figs.2, 3 and 4. Conventional
`type-2and 3 cells are also designed with the same rule of
`0.20 pm for the reference.
`The N+/P+ spacing of 0.42 ym was achieved with the
`shallow trench isolation of 0.4 pm depth. Dual gate transistor
`of 0.18 pm gate length with insulator on the gate electrode was
`fabricated. CVD SiN and Si02 were deposited and planarized
`by CMP. In the type-lb cell, VssNdd contacts were extended
`to the edge of cell using inlaid tungsten wirings. This structure
`enables the layout that TIN local wiring runs above Vss-N+
`and Vdd-P+ contacts with the use of stacked plug interconnects
`which connect inlaid wirings to VssNdd line?. Two pieces of
`local wirings were defined independently,’one with a Si02
`mask and the other with a resist mask.
`DC characteristics of these three cells with WT width of
`0.25 pm are measured as shown in Fig.5. The cell operation is
`demonstrated for the cell size from 3.40 to 4.14 pm2. Thus the
`design rule and process technology we have employed are
`verified as equivalent to the best performances in the 0.20 pm
`generation as shown in Table-2.
`
`Results and discussion
`(I) Conditions of SRAM cell design
`The dependence of cell stability on the size of transistor
`needs to be studied since the larger size WT for high speed
`operation will result in the worse cell stability. Fig.6 shows
`simulated static noise margins (SNM) with the ratio of
`driver / word transistor (BDT/BWT) as parameters. Consider-
`
`0-7803-4774-9/98/$10.00 0 1998 IEEE
`
`IEDM 98-201
`
`8.2.1
`
`Qualcomm Incorporated
`EX1008
`Page 1 of 4
`
`

`

`ing the distribution of cell stability due to the process
`conditions, the criterion of SNM is defined as SNM > 0.15 V
`at IVthl = 0.3 V. So, the ratio BDT / BWT 2 1 is required. The
`correlation between the ratio of driver / load transistor
`(BDT / BLT) and simulated SNM with the ratio BDT / BWT = 1
`in Fig.7 shows 6T-SRAM is stable in the range of
`2 5 BDT / BLT I 10. SRAM cells described below are designed
`with the ratio BDT / BWT = 1 and BDT / BLT = 6.
`
`(U} Optimization of cell size and bit line capacitance
`
`The memory cell size and BL capacitance are estimated as
`a function of WT width and shown in Figs.8 and 9.
`In Fig.8, the cell size of type-lb is the smallest for the WT
`width of larger than 0.75 pm. With increasing WT width, the
`type-2 and 3 cells expand both in the bit line and the word line
`directions keeping BDT / BWT = 1, while the type-lb cell
`expands only in the word line direction but is constant in the
`bit line direction, due to the layout of WT and DT arrayed in
`the same direction as shown in Table-3 (a). With WT width of
`0.75 pm, type-lb provides the smallest cell size of 5.33 pm2,
`which is 2 % and 35 % smaller than those of type-2 and 3.
`Furthermore, it is pointed out that type-3 provides the
`smallest cell size among these three cells for WT width of
`0.25 pm, but it provides 54 % larger cell than that of type-lb
`for WT width of 0.75 pm. This means the optimized cell
`layout with large size WT is different from that with minimum
`size WT. Although SRAM cell layout has been evaluated in
`terms of the cell size with small size WT in the past, we would
`like to emphasize to examine the cell layout in terms of large
`WT width for the high speed operation.
`
`As shown in Fig.9, BL capacitance of type-lb is the smallest
`and it is monotonously reduced with increasing WT width,
`which exhibits a sharp contrast to those of type-2 and 3. This is
`because the expansion af WT width for type-lb only results in
`the expansion of BL space while maintaining BL length
`constant as shown in Table-3 (b). With WT width of 0.75 pm,
`minimized BL capacitance is 0.37 fF/bit for type-lb.
`The cell size and BL capacitance with WT width of 0.75
`pm are summarized in Table-4. It is obvious that the type-lb
`cell provides the minimum values in the cell size and BL
`capacitance for WT width larger than 0.75 pm. Therefore, the
`type-lb layout is concluded to be desirable for the ultra high
`speed operation among these three cells.
`
`Fig. 10 shows the comparison of estimated access time with
`WT width of (a) 0.25 pm and (b) 0.75 pm. With increasing
`WT width, cell current is increased three times and BL
`capacitance is reduced 12 %, then BL delay results in the
`70 % reduction. Word line capacitance is increased 2.3 times
`with increasing WT width, but it results in only 1 % increase in
`total access time. As the result, total access time is reduced 25
`% with the increase of WT width. To achieve the same access
`time, not with the increase of WT width but with the reduction
`of gate delay in peripheral circuits, gate delay should be
`reduced 50 %. This shows the importance of SRAM cell layout
`with large size WT for the high speed operation.
`
`Figs. 11 and 12 show the SEM image and DC characteristics
`of type- 1 b with WT width of 0.75 pm, respectively.
`
`Since P and N wells in type-lb are extended along BL, and
`they are longer than those of reference cells, the dependence
`of SNM on the cell array size is measured. As shown in Fig.
`13, the SNM is insensitive to the well length for the array size
`less than 512 bit.
`(III) Scalability infuture
`
`Our proposed cell layout consistently provides three
`advantages for future scaling. (1) The corner rounding of
`patterns and irregularity of transistor size caused by the
`overlay shift are eliminated due to the rectangular design. (2)
`Low NA steppers can be used due to the wide spacing of each
`wiring layer. (3) Narrow gate length in peripheral circuits is
`allowed due to the wide focus depth with the above low NA
`steppers.
`
`The results of structure studies for the type- 1 b cell designed
`with the 0.18 pm rule are shown in Fig.14 where the cell size
`is reduced to 3.04 (1.52 x 2.00) pm2. As shown in Fig.14, no
`corner rounding of patterns nor irregularity of transistor size
`caused by the overlay shift are observed.
`The characteristics in lithography are shown in Figs. 15 and
`16. In Fig.15, the type-2 cell provides the focus range of only
`0.4 pm with NA of 0.45, and it requires at least NA of 0.55 to
`obtain enough range as shown in Fig. 16. For future scaling, a
`new stepper with higher NA is required. On the contrary,
`conventional low NA steppers can be used for type-lb as
`shown in Fig.15 due to the wide spacing of patterns.
`Furthermore it is pointed out that pattern printing with
`lower NA in type-lb provides wider focus range of the
`isolated gate pattern even for narrower gate length as shown in
`Fig.16. Narrower gate length allowed in type- lb contributes
`the reduction of gate delay in peripheral circuits due to the
`higher drivability and lower gate capacitance.
`The above three advantages demonstrate the geometrical
`advantage and the excellent scalability of type- 1 b beyond
`0.18 pm generation.
`
`Conclusion
`
`A novel 6T-SRAM cell layout designed with rectangular
`patterns has been developed. Among the various layouts of
`6T-SRAM cells, this layout provides minimum cell size and
`the smallest bit line capacitance with word transistor width
`over 0.75 pm for the ultra high speed operation. The cell
`layout proposed also provides the excellent scalability beyond
`0.18 pm generation due to highly simplified pattern design.
`
`Acknowledgement
`
`The authors would like to express their heartfelt thanks to
`Dr. T. Mamine for his support and discussions. They would
`also like to thank Mr. H. Kawahira for his support.
`
`References
`
`[l] J. Silberman et al., ISSCC Dig., p.230 (1998).
`[2] Y. Sambonsugi et al., Symp. on VLSI Tech., p.62 (1998)
`[3] K. Noda et al., EDM Tech. Dig., p.847 (1997).
`[4] M. Woo et al., Symp. on VLSI Tech., p.12 (1998).
`[SI Y. Taka0 et al., Symp. on VLSI Tech., p.1 I (1997).
`[6] M. Helm et al., Symp. on VLSI Tech., p.65 (1993).
`
`202-IEDM 98
`
`8.2.2
`
`Page 2 of 4
`
`

`

`Table-1 : Variations of the inverter lavouts and SF
`Category 1
`Category 2
`
`M cell layouts.
`Category 3
`
`Category 4
`
`Word Line Delay 0.1
`Fig.1: Contents of SRAM access time (a.u.)
`
`1
`
`!EO
`
`1 pp
`
`Table-2: Recent reported SRAM cells with 0.20 bm rule
`and the bevond.
`Samboni :;la
`-sugi & c.
`38VLSI (21 971EDM [3] 98VLSI [4] 97VLSI [5]
`
`Author
`
`E-
`
`Type-2
`-
`0.13
`-
`2.49
`
`~
`
`~
`
`~~
`
`Type-3 Type-1 a Type-1 a
`
`0.18
`
`0.20
`
`0.20
`
`2.91
`
`3.97
`
`4.08
`
`Type-1 a cell
`
`Design
`
`Cell Size
`
`This
`work
`
`This
`work
`
`This
`work
`
`Type-1 b cell
`
`Type-2
`
`Type-3 Type-1 b
`
`Type-2 cell
`
`U
`
`Type-3 cell i Type-4 cell
`vss -
`Vdd -
`I
`
`Gate Electrode
`I
`Description of Svmbols
`
`Layout
`
`Design
`Rule (pm)
`
`Cell Size
`( P 2 )
`Word
`
`Line
`
`0.20
`
`0.20
`
`0.20
`
`4.14
`
`3.40
`
`4.13
`
`Fig.4: SEM images of SRAM cells after 1 st contact fabrication;
`(a) type-lb cell (1.72 x 2.40 = 4.13 pm2), (b) type-2 cell
`(1.84 x 2.25 = 4.14 p2), (c) type-3 cell (1.08 x 3.15 = 3.40 pm2).
`
`Driver/Load
`Transistor Gate
`
`! Vdd Contact
`
`-Activ
`Area
`0 Poly-Si
`
`Local Wiring
`Etched by Resist Mask
`Local Wiring
`Etched by Si02 Mask
`Fig.2: Layouts of proposed type-1 b SRAM cell.
`
`'0
`
`0.5
`1
`Vin.Voui (V)
`(a)
`
`1.5
`
`'0
`
`1.5
`
`0.5
`1
`Vin,Vout (V)
`(b)
`Fig.5: DC characteristics of SRAM cells at Vcc = 1.5 V;
`(a) type-lb cell, (b) type-2 cell, (c) type-3 cell.
`
`'0 U 0.5
`
`1.5
`
`I
`Vin,Vout (V)
`( 4
`
`o.6 l v c c = 1.5v
`
`Fig.3: SEM images of proposed type-1 b SRAM cell;
`(a) after poly Si fabrication,
`(b) after local wiring fabrication.
`
`'6.4 0.6 0.8 1 1.2 1.4 1.6
`R DT / P WT Ratio
`Fig.6: DT and WT size dependence
`of the cell stabilty with BDT/BLT = 6.
`
`":
`
`. A Ib
`
`6
`I
`R DT / R LT Ratio
`Fig.7: DT.WT and LT size dependence
`of the cell stability with RDTIRWT = 1.
`
`8.2.3
`
`IEDM 98-203
`
`Page 3 of 4
`
`

`

`ODTIOWT = 1
`ODT/OLT = 6
`
`1
`
`
`
`
`
`q 1 ,
`
`Word Tr. Width (pm)
`
`OO
`
`1
`0.5
`Word Tr. Width (pm)
`
`Fig.8: Cell size of each SRAM cell
`layout as a function of WT size.
`
`Fig.9: BL capacitance of each SRAM cell
`layout as a function of WT size.
`
`Cell
`Layout
`
`WT width
`= 0.25 pm
`
`Cell Size
`(pmVBit)
`
`WT width
`= 0.75 pm
`
`Cell Size
`(p mYB it)
`
`BL Capacitance
`(fF/Bit)
`
`Type-1 b
`
`Type-2
`
`4.13 [I .72x2.401
`
`I 4.14 [1.84x2.251
`
`I
`
`5.33 [2.22x2.40]
`
`5.45 [1.98x2.751
`
`I
`
`0.37
`
`0.44
`
`Type-3
`
`3.4 [1.08x3.15]
`
`8.22 [1.98~4.15]
`
`0.67
`
`I auie-3: w I size aepenaence ot cell transistor layouts
`and bit line layouts.
`Type-3 Cell
`
`Type-1 b Cell
`
`1
`
`U
`
`Exuansion
`of the WT width uu
`5
`.P '5 C V
`;!i
`1
`-
`
`Z E - I
`
`im
`
`1
`
`
`
`L Word Line Delay
`Fig.10: Comparison of the access time;
`(a) reference and (b) BL delay reduction.
`
`0.3
`I
`Vcc=1.5V
`" +
`C .- g 0.2
`I
`.- I
`2
`g 0.1
`m m
`
`Y
`
`-1.Opm
`
`Fig.11: SEM image of type-lb cell
`with WT width of 0.75 pm
`after poly Si fabrication.
`
`Vin,Vout (V)
`Fig.12: DC characteristics of type-lb
`cell with WT width of 0.75 pm.
`
`Cell Array Size (Bit)
`Fig.13: Cell array size dependence
`of the cell stability.
`
`Focus (Mm)
`Fig.15: Focus depth dependence of the
`gate length of the memory cell
`transistor. Round plot is of type-I b
`cell, and triangle plot is of type-2
`cell. Both plots are with NA of 0.45.
`
`0 5 -0.08-
`
`c
`L
`Y?
`6 -0.12
`0.3 0.6
`-0.6 -0.3
`0
`Focus (pm)
`Fig.16: Focus depth dependence of the
`gate length of the memory cell
`transistor and the isolated transistor.
`Vacant plot is with NA of 0.55, and
`occupied plot is with NA of 0.45.
`
`Fig.14: SEM images of type-lb cell designed with 0.18 pm rule;
`(a) after poly Si fabrication, (b) after 1st contact fabrication.
`(c) after local wiring fabrication. Cell size = 3.04 (1.52x2.00) pm2.
`
`204-IEDM 98
`
`8.2.4
`
`Page 4 of 4
`
`