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`..
`
`IEEE Press
`445 Hoes Lane, P.O. Box 1331
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`Editorial Board
`John B. Anderson, Editor in Chief
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`

`

`CMOS
`Circuit Design, Layout, and Simulation
`
`R. Jacob Baker, Harry W. Li and David E. Boyce
`Department ofElectrical Engineering
`Microelectronics Research Center
`The University of Idaho
`
`IEEE Press Series on Microelectronic Systems
`Stuart K. Tewksbury, Series Editor
`
`IEEE Circuits & Systems Society, Sponsor
`IEEE Solid-State Circuits Society, Sponsor
`
`IEEE
`PRESS
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`The Institute of Electrical and Electronics Engineers, Inc., New York
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`Page 3 of 153
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`

`

`:1
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`·-1
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`\
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`Ii:",,~ e,
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`(\
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`i L
`
`I -
`
`This book and other books may be purchased at a discount
`from the publisher when ordered in bulk quantities. Contact:
`
`IEEE Press Marketing
`Attn: Special Sales
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`© 1998 by the Institute of Electrical and Electronics Engineers, Inc.
`345 East 47th Street, New York, NY 10017-2394
`
`All rights reserved. No part ofthis book may be reproduced in any form,
`nor may it be stored in a retrieval system or transmitted in any form,
`without written permission from the publisher.
`
`Printed in the United States of America
`10
`9
`8
`7
`6
`5
`4
`3
`
`ISBN 0·7803·3416·7
`IEEE Order Number: PC5689
`
`Library of Congress Cataloging-in-Publication Data
`
`Baker, R. Jacob (date)
`CMOS circuit design, layout, and simulation I R. Jacob Baker,
`Harry W. Li, and David E. Boyce.
`p.
`em. -- (IEEE Press series on microelectronic systems)
`Includes bibliographical references and index.
`ISBN 0-7803-3416-7
`I. Metal oxide semiconductors, Complementary-Design and
`construction.
`2. Integrated circuits--Design and construction.
`3. Metal oxide semiconductor field-effect transistors.
`I. Li,
`Harry W.
`II. Boyce, David E.
`III. Title.
`IV. Series
`TK7871.99.M44B35
`1997
`621.3815--DC21
`
`97-21906
`CIP
`
`Page 4 of 153
`
`

`

`Contents
`
`Preface
`
`Part I CMOS Fundamentals
`
`Chapter 1 Introduction
`1.1 The CMOS IC Design Process
`1.1.1 Fabrication
`1.2 Using the LASI Program
`1.2.1 Cells in LASI
`1.2.2 Navigating LASI
`1.2.3 Adding Objects
`1.2.4 Editing Objects
`1.2.5 Placing Cells
`1.2.6 Common Problems
`1.3 MOSIS
`Chapter 2 The Well
`2.1 The Substrate
`2.1.1 Patterning
`2.1.2 Patterning the N-well
`2.2 Laying out the N-well
`
`xix
`
`1
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`3
`3
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`5
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`10
`10
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`12
`14
`15
`23
`23
`24
`27
`27
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`..
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`viii
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`2.2.1 Design Rules for the N-well
`2.2.2 Using the LASIDRC program
`2.3 Resistance Calculation
`2.3.1 The N-well Resistor
`2.4 The N-well/Substrate Diode
`2.4.1 Depletion Layer Capacitance
`2.4.2 Storage Capacitance
`2.4.3 SPICE Modeling
`2.5 The RC Delay Through an N-well
`Chapter 3 The Metal Layers
`3.1 The Bonding Pad
`3.1.1 Laying out the Pad
`3.1.2 Design Rules for Pads
`3.2 Design and Layout Using the Metal Layers
`3.2.1 Design Rules for the Metal Layers
`3.2.2 Parasitics Associated with the Metal Layers
`3.2.3 Current Carrying Limitations
`3.2.4 Parasitics Associated with the Via
`3.3 Crosstalk and Ground Bounce
`3.3.1 Ground Bounce
`3.4 Layout Using Cell Hierarchy
`Chapter 4 The Active and Poly Layers
`4.1 Design Rules
`4.1.1 Design Rules for the n+/p+ Active Layers
`4.1.2 Design Rules for Polyl
`4.2 Layout of a Standard Cell Frame
`4.3 Patterning the Active Layers
`4.4 Layout of the MOSFET
`4.4.1 Parasitics Associated with the Active Layers
`Chapter 5 The MOSFET
`5.1 The MOSFET Capacitances
`5.1.1 Case I: Accumulation
`5.1.2 Case II: Depletion
`
`Contents
`
`28
`30
`30
`32
`32
`33
`35
`37
`38
`45
`45
`45
`48
`, 50
`50
`50
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`55
`56
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`59
`65
`66
`66
`69
`71
`71
`77
`77
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`

`

`Contents
`
`ix
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`86
`87
`88
`93
`94
`96
`98
`98
`99
`100
`102
`107
`109
`" . . . . . . . . . . . . . .. 111
`III
`113
`116
`119
`120
`122
`124
`127
`131
`131
`131
`132
`134
`134
`
`5.1.3 Case III: Strong Inversion
`5.1.4 Summary
`5.2 The Threshold Voltage
`5.3 IV Characteristics of MOSFETs
`5.3.1 MOSFET Operation in the Triode Region
`5.3.2 The Saturation Region
`5.4 SPICE Modeling of the MOSFET
`5.4.1 Levell Model Parameters Related to VTHN
`5.4.2 Levell Model Parameters Related to Transconductance
`5.4.3 SPICE Modeling of the Source and Drain Implants
`5.4.4 Layout of the MOSFET
`Chapter 6 The 8SIM SPICE Model
`6.1 BSIMI Model Parameters
`6.2 BSIMI DC Equations
`6.2.1 The Threshold Voltage
`6.2.2 The Drain Current
`6.2.3 The Subthreshold Current
`6.3 Short Channel MOSFETs
`6.3.1 MOSFET Scaling
`6.3.2 Short Channel Effects
`6.4 The BSIM3 SPICE Model
`6.5 Convergence
`Chapter 7 CMOS Passive Elements
`7.1 The Second Poly Layer (poly2)
`7.1.1 Design Rules for Capacitor Formation
`7.1.2 Parasitics of the Poly Cap
`7.1.3 Other Types of Capacitors
`7.2 Temperature and Voltage Dependence of Capacitors and
`Resistors
`7.2.1 Resistors
`7.2.2 Capacitors
`7.3 Noise in Resistors
`Chapter 8 Design Verification with LASICKT
`8.1 Fundamentals of LASICKT
`
`.
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`134
`140
`141
`149
`150
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`x
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`Contents
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`8.1.1 The Inverter
`8.1.2 Running LASICKT
`8.1.3 Higher-ranking Cells; The OR Gate
`Chapter 9 Analog MOSFET Models
`9.1 Low-Frequency MOSFET Model
`9.1.1 Small-Signal Model of the MOSFET in Saturation
`9.2 High-Frequency MOSFET Model
`9.2.1 Variation of Transconductance with Frequency
`9.3 Temperature Effects in MOSFETs
`9.4 Noise in MOSFETs
`Chapter 10 The Digital Model
`10.1 The Digital MOSFET Model
`10.1.1 Capacitive Effects
`10.1.2 Process Characteristic Time Constant
`10.1.3 De1ay- and Transition-Times
`10.2 Series Connection of MOSFETs
`10.2.1 DC Behavior of Series-Connected MOSFETs
`10.2.2 Delay Through Series-Connected MOSFETs
`Possible Student Projects
`
`Part II CMOS Digital Circuits
`
`151
`157
`160
`165
`165
`166
`171
`173
`175
`178
`185
`185
`187
`188
`189
`192
`192
`194
`196
`
`199
`
`Chapter 11 The Inverter
`11.1 DC Characteristics
`11.1.1 Noise Margins
`11.1.2 Inverter Switching Point
`11.2 Switching Characteristics
`11.2.1 The Ring Oscillator
`11.2.2 Dynamic Power Dissipation
`11.3 Layout of the Inverter
`11.3.1 Latch-up
`11.4 Sizing for Large Capacitive Loads
`11.4.1 Distributed Drivers
`
`201
`202
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`,. . . . . . . . . .. 205
`209
`210
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`Contents
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`xi
`
`11.4.2 Driving Long Lines
`11.5 Other Inverter Configurations
`11.5.1 N-Channel Only Output Drivers
`11.5.2 Inverters with Tri-State Outputs
`11.5.3 The Bootstrapped NMOS inverter
`Chapter 12 Static Logic Gates
`12.1 DC Characteristics of the NAND and NOR Gates
`12.1.1 DC Characteristics of the NAND Gate
`12.1.2 DC Characteristics of the NOR Gate
`12.2 Layout of the NOR and NAND Gates
`12.3 Switching Characteristics
`12.3.1 NAND Gate
`12.3.2 Number oflnputs
`12.4 Complex CMOS Logic Gates
`12.4.1 Cascode Voltage Switch Logic
`12.4.2 Differential Split-Level Logic
`12.4.3 Tri-State Outputs
`Chapter 13 The TG and Flip-Flops
`13.1 The Pass Transistor
`13.2 The CMOS TG
`13.2.1 Layout of the CMOS TG
`13.2.2 Series Connection of Transmission Gates
`13.3 Applications of the Transmission Gate
`13.4 The Flip-Flop
`13.4.1 Clocked Flip-Flops
`Chapter 14 Dynamic Logic Gates
`14.1 Fundamentals of Dynamic Logic
`14.1.1 Charge Leakage
`14.1.2 Simulating Dynamic Circuits
`14.1.3 Nonoverlapping Clock Generation
`14.1.4 CMOS TG in Dynamic Circuits
`14.2 Clocked CMOS Logic
`
`223
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`235
`. . . . . . . . . . . . . . . . . . . . . . . . . . .. 236
`238
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`255
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`

`

`xii
`
`Contents
`
`Chapter 15 VLSI Layout
`15.1 Chip Layout
`,
`15.2 Layout Steps
`Chapter 16 BiCMOS Logic Gates
`16.1 Layout of the Junction-Isolated BIT
`16.2 Modeling the NPN
`16.3 The BiCMOS Inverter
`16.4 Other BiCMOS Logic Gates
`16.5 CMOS and ECL Conversions Using BiCMOS
`Chapter 17 Memory Circuits
`17.1 RAM Memory Cells
`17.1.1 The DRAM Cell
`17.1.2 The SRAM cell
`17.2 The Sense Amplifier
`17.3 Row/Column Decoders
`17.4 Timing Requirements for DRAMs
`17.5 Modern DRAM Circuits
`17.5.1 DRAM Memory Cell Layout
`17.5.2 Folded/Open Architectures
`17.6 Other Memory Cells
`Chapter 18 Special-Purpose Digital Circuits
`18.1 The Schmitt Trigger
`18.1.1 Design of the Schmitt Trigger
`18.1.2 Switching Characteristics
`18.1.3 Applications of the Schmitt Trigger
`18.1.4 High-Speed Schmitt Trigger
`18.2 Multivibrator Circuits
`18.2.1 The Monostable Multivibrator
`18.2.2 The Astable Multivibrator
`18.3 Voltage Generators
`18.3.1 Improving the Efficiency
`18.3.2 Generating Higher Voltages
`18.3.3 Example
`
`289
`290
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`313
`314
`316
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`Page 10 of 153
`
`

`

`Contents
`
`Chapter 19 Digital Phase-Locked Loops
`19.1 The Phase Detector
`19.1.1 The XOR Phase Detector
`19.1.2 Phase Frequency Detector
`19.2 The Voltage-Controlled Oscillator
`19.2.1 The Current-Starved VCO
`19.2.2 Source Coupled VCOs
`19.3 The Loop Filter
`19.3.1 XOR DPLL
`19.3.2 PFD DPLL
`19.4 System Considerations
`19.4.1 Clock Recovery from NRZ Data
`19.5 Delay-Locked Loops
`
`Part III CMOS Analog Circuits
`
`Chapter 20 Current Sources and Sinks
`20.1 The Current Mirror
`20.1.1 The Cascode Connection
`20.1.2 Sensitivity Analysis
`20.1.3 Temperature Analysis
`20.1.4 Transient Response
`20.1.5 Layout of the Simple Current Mirror
`20.1.6 Matching in MOSFET Mirrors
`20.2 Other Current Sources/Sinks
`Chapter 21 References
`21.1 Voltage Dividers
`21.1.1 The Resistor-MOSFET Divider
`21.1.2 The MOSFET-On1y Voltage Divider
`21.2 Current Source Self-Biasing
`21.2.1 Threshold Voltage Referenced Self-Biasing
`21.2.2 Diode Referenced Self-Biasing
`21.2.3 Thermal Voltage Referenced Self-Biasing
`
`xiii
`
`373
`375
`375
`379
`383
`384
`387
`391
`391
`398
`403
`407
`417
`
`425
`
`427
`" 427
`433
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`

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`xiv
`
`Contents
`
`21.3 Bandgap Voltage References
`21.3.1 Bandgap Referenced Biasing
`21.4 Beta Multiplier Referenced Self-Biasing
`21.4.1 A Voltage Reference
`21.4.2 Operation in the Subthreshold Region
`Chapter 22 Amplifiers
`22.1 Gate-Drain Connected Loads
`22.1.1 Common Source Amplifiers
`22.1.2 The Source Follower
`22.1.3 Common Gate Amplifiers
`22.2 Current Source Loads
`22.2.1 The Cascode Connection
`22.2.2 The Push-Pull Amplifier
`22.3 Noise and Distortion in Amplifiers
`22.3.1 Modeling Amplifier Noise
`22.4 A Class AB Amplifier
`Chapter 23 Feedback Amplifiers
`23.1 The Feedback Equation
`23.2 Properties of Negative Feedback on Amplifier Design
`23.2.1 Gain Desensitivity
`23.2.2 Bandwidth Extension
`23.2.3 Reduction in Nonlinear Distortion
`23.2.4 Input and Output Impedance Control
`23.3 Recognizing Feedback Topologies
`23.3.1 Input Mixing
`23.3.2 Output Sampling
`23.3.3 The Feedback Network
`23.3.4 Calculating Open-Loop Parameters
`23.3.5 Calculating Closed-Loop Parameters
`23.4 The Voltage Amp (Series-Shunt Feedback)
`23.5 The Transimpedance Amp (Shunt-Shunt Feedback)
`23.5.1 Simple Feedback Using a Gate-Drain Resistor
`23.6 The Transconductance Amp (Series-Series Feedback)
`23.7 The Current Amplifier (Shunt-Series Feedback)
`
`477
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`

`

`Contents
`
`23.8 Stability
`23.8.1 The Return Ratio
`Chapter 24 Differential Amplifiers
`24.1 The Source Coupled Pair
`24.1.1 Current Source Load
`24.1.2 Common-Mode Rejection Ratio
`24.1.3 Noise
`24.1.4 Matching Considerations
`24.2 The Source Cross-Coupled Pair
`24.2.1 Current Source Load
`24.3 Cascode Loads
`24.4 Wide-Swing Differential Amplifiers
`24.4.1 Current Differential Amplifier
`24.4.2 Constant Transconductance Diff-Amp
`Chapter 25 Operational Amplifiers
`25.1 Basic CMOS Op-Amp Design
`25.1.1 Characterizing the Op-Amp
`25.1.2 Compensating the Op-Amp Without Buffer
`25.1.3 The Cascode Input Op-Amp
`25.2 Operational Transconductance Amplifiers
`25.2.1 Wide-Swing OTA
`25.2.2 The Folded-Cascode OTA
`25.3 The Differential Output Op-Amp
`25.3.1 Fully Differential Folded-Cascode OTA
`25.3.2 Gain Enhancement
`
`Part IV Mixed-Signal Circuits
`
`Chapter 26 Nonlinear Analog Circuits
`26.1 Basic CMOS Comparator Design
`26.1.1 Characterizing the Comparator
`26.2 Adaptive Biasing
`26.3 Analog Multipliers
`
`xv
`
`564
`568
`579
`579
`582
`591
`592
`594
`596
`599
`602
`605
`607
`608
`617
`618
`630
`634
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`674
`
`683
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`685
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`699
`704
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`

`xvi
`
`Contents
`
`26.3.1 The Multiplying Quad
`26.3.2 Level Shifting
`26.3.3 Multiplier Design Using Squaring Circuits
`Chapter 27 Dynamic Analog Circuits
`27.1 The MOSFET Switch
`27.2 Switched-Capacitor Circuits
`27.2.1 Switched-Capacitor Integrator
`27.3 Circuits
`Chapter 28 Data Converter Fundamentals
`28.1 Analog Versus Discrete Time Signals
`28.2 Converting Analog Signals to Digital Signals
`28.3 Sample-and-Hold (S/H) Characteristics
`28.4 Digital-to-Analog Converter (DAC) Specifications
`28.5 Analog-to-Digital Converter (ADC) Specifications
`28.6 Mixed-Signal Layout Issues
`Chapter 29 Data Converter Architectures
`29.1 DAC Architectures
`29.1.1 Digital Input Code
`29.1.2 Resistor String
`29.1.3 R-2R Ladder Networks
`29.1.4 Current Steering
`29.1.5 Charge Scaling DACs
`29.1.6 Cyclic DAC
`29.1.7 Pipeline DAC
`29.2 ADC Architectures
`29.2.1 Flash
`29.2.2 The Two-Step Flash ADC
`29.2.3 The Pipeline ADC
`29.2.4 Integrating ADCs
`29.2.5 The Successive Approximation ADC
`29.2.6 The Oversampling ADC
`Appendix A Orbit's CN20 Process
`A.l Process Specifications
`
`705
`710
`715
`719
`719
`728
`731
`745
`755
`755
`756
`759
`762
`772
`783
`791
`791
`791
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`797
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`813
`818
`823
`827
`832
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`855
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`

`

`Contents
`
`A.l.l Electrical Specifications
`A.l.2 N-Channel SPICE Models
`A.I.3 P-Channel SPICE Models
`A.2 Hand Calculations
`A.2.1 The N-channel MOSFET Equations
`A.2.2 The P-channel MOSFET Equations
`A.3 Design Rules
`Appendix B MOSIS Scalable Design Rules
`Appendix C HP's CMOS14TB
`Index
`About the Authors
`LASI Software
`
`xvii
`
`857
`859
`861
`862
`862
`865
`867
`873
`885
`893
`903
`904
`
`Page 15 of 153
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`

`

`Preface
`
`Over the last ten years the electronics industry has exploded. A recent report by the
`Semiconductor Industry Association (SIA) [1] proclaimed that in 1995 alone, world
`chip revenues increased by 41.7 percent and for the past five years the growth had been
`exponential. By the year 1999, the report estimates that world chip sales will surpass
`$234.5 billion, up from $154 billion in 1996. The largest portion of total worldwide
`sales is dominated by the MOS market. Composed primarily of memory, micro and
`logic sales, the total combined MOS revenue contributed approximately 75 percent of
`total world-wide sales ($114.2 billion), illustrating the strength of CMOS technology.
`The percentage of MOS sales relative to all chip revenues is expected to remain
`constant through 1999, when MOS sales will total $178 billion.
`
`CMOS technology continues to mature, with minimum feature sizes now
`approaching 0.1 lim. Texas Instruments recently announced a 0.18 lim process [2] in
`which the equivalent of 20 high-performance microprocessors could exist on the same
`substrate, with a transistor density of 125 million transistors. This high density allows
`for
`true
`system-level
`integration on a chip, with digital
`signal processors,
`microprocessors or microcontroller cores, memory, analog or mixed-signal functions all
`residing on the same die.
`
`As educators we are often asked by our students, "Isn't analog dead? I thought
`everything was going digital!" How untrue! The prediction of the future demise of
`analog electronics has been around since the mid-1970s. According to the SIA report
`[1], the revenues generated by analog products closely parallel the MOS logic market
`and achieved a 22.5 percent increase in 1995. The analog market expects to reach
`$18.2 billion in 1996 (a 9.5 percent increase) with double-digit growth projected for the
`next three years. In 1999, the total revenues generated by analog sales is forecasted to
`peak at $26.6 billion (11.3 percent of total chip sales!). However, while there is still
`
`Page 16 of 153
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`

`

`xx
`
`Preface
`
`demand for analog designers, their role is definitely changing. As was communicated
`by Paul Gray in [3], the days of pure analog design are over, meaning that very few
`systems remain purely analog. More and more systems are integrated, with increased
`functionality being performed in the digital domain. He goes on to state that the analog
`designer should become broad-based, with analog transistor-level design as the core
`skill. This means that the analog designer should also
`
`Have a good understanding of digital very large scale integration (VLSI) and
`be competent at using the latest computer-aided design (CAD) tools.
`
`know how to apply digital signal processing (DSP), analog signal processing
`(ASP), and filtering concepts to system-level design.
`
`possess insight into system implications of component-level performance.
`
`For example, DSP and transistor-level analog design skills are needed for oversampling
`applications such as data converters, filtering, and a host of relatively new circuit
`topologies based on sigma-delta modulation. Being able to design both analog and
`digital circuits, as well as understand the interactions between the two domains, will
`provide an added dimension to a designer's portfolio that is difficult to match. Analog
`designers are in demand more than ever, simply because the end limitations of digital
`electronics need to be examined under the "analog" microscope to fully understand the
`mechanisms that are occurring. Therefore, this text attempts to combine digital and
`analog IC design in one complete reference.
`
`Layout is the process of physically defining the layers that compose an integrated
`circuit. Typically,
`layouts are constructed using a computer-aided design program.
`CAD companies such as Mentor Graphics, Synopsis, and Cadence specialize in
`providing extremely powerful CAD software for the entire integrated circuit (Ie) design
`process, including design, synthesis, simulation, and layout tools within an integrated
`framework.
`These workstation-based software tools can literally cost millions of
`dollars, but provide convenient and powerful features found nowhere else. CAD tools
`also exist for the PC. Tanner Tool's L-Edit provides a complete IC design CAD
`program for the personal computer. The program discussed in this book, LAyout
`System for Individuals (LASI) (pronounced "LAZY"), also provides the student with the
`ability to layout ICs on a PC and includes design rule checking and design verification
`capability. It is distributed as shareware, free for educational purposes.
`
`With decreases in feature size come added complexities in the design. Layouts
`must now be considered heavily in the design process as matching and parasitic effects
`become the limiting factors in many precision and high-speed applications. The more
`the designer knows about the process with respect to layout and modeling, the more
`performance the engineer can "squeeze" out the design. However, performance is not
`the only reason to consider the layout. The economic impact of IC layouts can be
`detrimental to the circuit's marketing potential.
`In some cases a 20 percent increase in
`chip area can reduce the profits of a chip by several hundreds of thousands of dollars.
`Chip area should be considered as premium real estate. Therefore, much of the first ten
`
`Page 17 of 153
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`

`

`Preface
`
`xxi
`
`chapters of this book is devoted to fundamental
`presented as the need arises.
`
`layout
`
`issues, with other
`
`issues
`
`Modeling is also a key issue. A simulation is only as accurate as its model.
`Although the Berkeley Short-channel IGFET Model (BSIM) model has become the
`industry standard its relatively nonintuitive structure makes hand analysis using BSIM
`model parameters an intimidating process. To many students (and engineers), the
`BSIM parameters are nothing more than sets of numbers at the end of their SPICE
`decks. However, some very useful information can be gleaned from the BSIM model
`which helps make the hand analysis more closely resemble the simulated result.
`Chapter 6 provides a great deal of information that relates the BSIM model
`to
`first-order hand-analysis equations.
`
`A successful CMOS integrated circuit design engineer has knowledge in the
`areas of device operation, circuit design,
`layout, and simulation. Students learning
`CMOS IC design should be trained at a fundamental level in these areas.
`In the past,
`courses on CMOS integrated circuits dealt mainly with circuit design or analysis. Little
`to no time was spent on layout of the integrated circuits. This may have been justified.
`It is difficult to find a reason to layout an entire chip and then not have the chip
`fabricated. However, through the use of the MOSIS 1 program, students can submit their
`chip designs for fabrication through one of the MOSIS contracted vendors.
`In
`approximately ten weeks the chips are returned to the university for evaluation. The
`MOSIS program is an outstanding way of introducing students to the design of ICs.
`
`Although many texts [4-32] are available covering some aspects of CMOS
`analog or digital circuit design, none integrates the coverage of both topics with layout
`and includes layout software as is done in this text. Our focus, when writing this text,
`was on the fundamentals of custom CMOS integrated circuit design.
`It was our goal
`that a student who studies and masters the material
`in this text will possess the
`fundamental skills needed to design high-performance analog and digital CMOS
`circuits and have the basic understanding and problem-solving skills needed to enhance
`the performance of an IC or to determine why an IC doesn't function as simulated.
`
`Use of This Text
`
`This text can be used for two courses. Both courses can be offered at the senior/first(cid:173)
`year graduate level. The first course concentrates on the physical design of CMOS
`digital integrated circuits with prerequisites of junior level Electronics I and a course on
`digital logic design. A possible semester course outline is as follows.
`
`Week I
`
`Week 2
`
`Chs. I & 2, introduction, course requirements, layout and SPICE
`demonstrations, the n-well, sheet resistance.
`
`Chs. 2 & 3, the n-well, pn junction, capacitance, resistance, delay
`through the well, introduction to the metal layers.
`
`1 MOSIS - MOS Implementation System through the Information Sciences Institute at the
`University of Southern California, (310) 822-1511 or http://www.mosis.org
`
`Page 18 of 153
`
`

`

`xxii
`
`Week 3
`
`Week 4
`
`WeekS
`
`Week 6
`
`Week 7
`
`Week 8
`
`Week 9
`
`Week 10
`
`Week 11
`
`Preface
`
`Chs. 3 &4, the metal layers, parasitics, electomigration, layout of the
`padframe, active/poly layers, layout of the MOSFET and standard frame.
`
`Ch. 5, MOSFET operation
`
`Chs. 5 & 6, completion of MOSFET operation, discussion of modeling
`using the BSIM model.
`
`Chs. 6 & 7, completion of BSIM model, layout of a capacitor, MOS temp
`dependence.
`
`Chs. 10 & 11, digital models and the inverter.
`
`Ch. 11, the inverter, switching point voltage and switching times, layout,
`latch-up, and design.
`
`Ch. 12, static logic gates, switching point voltages, speed, and layout.
`
`Chs. 13 & 14, the transmission gate, flip-flops, and dynamic logic gates.
`
`Chs. 15 & 16, VLSI layout and BiCMOS logic.
`
`Week 12
`
`Ch. 17, memory circuits, basic memory cells, and organization.
`
`Week 13
`
`Week 14
`
`Ch. 18, special-purpose digital circuits.
`
`Ch. 19, introduction to digital phase locked loops, phase detectors,
`VCOs.
`
`Week 15
`
`Ch. 19, digital PLL design.
`
`The second course concentrates on CMOS analog circuit design. A possible semester
`course outline is as follows.
`
`Weeks 1 & 2 Review ofChs. 1-6.
`
`Week 3
`
`Week 4
`
`WeekS
`
`Week 6
`
`Week 7
`
`Week 8
`
`Week 9
`
`Chs. 7, CMOS passive elements, noise characteristics.
`
`Ch. 9, analog MOSFET models.
`
`Ch. 20, current sources and sinks.
`
`Ch. 21, references.
`
`Ch. 22, amplifiers.
`
`Ch. 23, selected topics in feedback amplifier design.
`
`Ch. 24, differential amplifiers.
`
`Weeks 10-12 Ch. 25, operational amplifiers.
`
`Week 13
`
`Week 14
`
`Ch. 26, nonlinear analog circuits.
`
`Ch. 27, dynamic analog circuits.
`
`Page 19 of 153
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`

`

`Preface
`
`XXIII
`
`Week 15
`
`Chs. 28 &29, selected topics in data converter design.
`
`This text can also be used as an accompanying text in a VLSI systems course that
`focuses on the implementation of systems rather than circuits. Use of the text in this
`manner is benefited by inclusion of the LASI layout software.
`REFERENCES
`
`[1]
`
`[2]
`
`[3]
`
`Revised Forecast for World Chip Market Shows Growth of 6.7% in 1996, 19%
`by 1999, Semiconductor Forcast Summary 1995-1998, Semiconductor Industry
`Association.
`
`"New TI Technology Doubles Transistor Density," Texas
`Integration Newsletter, Vol. 13, No.5, July 1995.
`
`Instruments
`
`"Possible Analog IC Scenarios
`P. Gray,
`eecs.berkeley.edu/slides.html
`
`for
`
`the 90's," http://kabuki.
`
`Digital Circuits and VLSI System Design
`
`[4]
`
`[5]
`
`[6]
`
`[7]
`
`[8]
`
`[9]
`
`C. Mead and L. Conway, Introduction to VLSI Systems, Addison-Wesley, 1980.
`
`Glasser and Dopperpuhl, The Design and Analysis of VLSI Circuits, Addison
`Wesley, 1985.
`
`M. Annaratone, Digital CMOS Circuit Design, Kluwer,1986.
`
`A. Mukherjee,
`Introduction to NMOS and CMOS VLSI Systems Design,
`Prentice-Hall Publishers, 1986. ISBN 0-13-490947-X
`
`D. A. Hodges and H. G. Jackson, Analysis and Design of Digital Integrated
`Circuits, McGraw-Hill, 2nd ed., 1988. ISBN 0 - 07 - 029158 - 6.
`
`M. Shoji, CMOS Digital Circuit Technology, Prentice-Hall, 1988.
`0-13-138850-9.
`
`ISBN
`
`[10]
`
`J. P. Uyemura, Fundamentals of MOS Digital
`Addison-Wesley, 1988. ISBN 0-201-13318-0.
`
`Integrated Circuits,
`
`[11] R. L. Geiger, P. E. Allen, and N. R. Strader, VLSI - Design Techniques for
`Analog and Digital Circuits, McGraw-Hill, 1990. ISBN 0-07-023253-9.
`
`[12]
`
`J. Y. Chen, CMOS Devices and Technology for VLSI, Prentice-Hall, 1990.
`ISBN 0-13-138082-6.
`
`[13]
`
`Fabricius, Introduction to VLSI Design, McGraw-Hill, 1990.
`
`[14] M. I. Elmasry, Digital MOS Integrated Circuits II,
`0-87942-275-0.
`
`IEEE Press, 1992.
`
`ISBN
`
`[15] N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison
`Wesley, 2nd ed., 1993. ISBN 0-201-53376-6.
`
`Page 20 of 153
`
`

`

`xxiv
`
`Preface
`
`[16]
`
`J. P. Uyemura, Circuit Design for Digital CMOS VLSI, Kluwer, 1992.
`
`[17] D. A. Pucknell and K. Eshraghian, Basic VLSI Design, 3rd ed., Prentice Hall
`Publishers, 1994. ISBN 0-13-079153-9
`
`[18] D. Pucknell, Basic VLSI Design: Systems and Circuits, 3rd ed., Prentice Hall,
`1994. ISBN: 0-13-079153-9
`
`[19] W. Wolf, Modern VLSI Design: A Systems Approach, Prentice Hall, 1994.
`ISBN: 0-13-588377-6
`
`[20]
`
`[21]
`
`[22]
`
`S. Kang and Y. Leblebici, CMOS Digital Integrated Circuits - Analysis and
`Design, McGraw-Hill, 1996. ISBN 0-07-038046-5.
`
`K. Gopalan, Introduction to Digital Microelectronic Circuits, Irwin, 1996.
`ISBN 0-256-12089-7.
`
`J. M. Rabaey, Digital Integrated Circuits - A Design Perspective, Prentice Hall,
`1996, ISBN 0-13-178609-1.
`
`Analog Circuits
`
`[23] A. B. Grebene, Bipolar and MOS Analog Integrated Circuit Design,
`John-Wiley, 1984. ISBN 0-471-08529-4
`
`[24] R. Gregorian and G. C. Ternes, Analog MOS Integrated Circuits for Signal
`Processing, John Wiley, 1986. ISBN 0-471-09797-7.
`
`[25]
`
`[26]
`
`[27]
`
`[28]
`
`P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, Holt, Rinehart
`and Winston, 1987. ISBN 0-03-006587-9.
`
`P. R. Gray, B. A. Wooley and R. W. Broderson, Analog MOS Integrated
`Circuits II, IEEE Press. ISBN 0-87942-246-7.
`
`R. L. Geiger, P. E. Allen, and N. R. Strader, VLSI - Design Techniques for
`Analog and Digital Circuits, McGraw-HilI, 1990. ISBN 0-07-023253-9.
`
`P. R. Gray and R. G. Meyer, Analysis and Design ofAnalog Integrated Circuits,
`3rd ed., John Wiley, Inc., 1993. ISBN 0-471-57495-3.
`
`[29] M. Ismail and T. Fiez, Analog VLSI - Signal and Information Processing,
`McGraw-HilI, Inc. 1994. ISBN 0-07-032386-0.
`
`[30]
`
`K. R. Laker and W. Sansen, Design of Analog Integrated Circuits and Systems,
`McGraw-HilI, 1994. ISBN 0-07-036060-X.
`
`[31] G.A.S. Machado, Low-Power HF Microelectronics a unified approach,
`1996. ISBN 0-85296-874-4.
`
`lEE,
`
`[32] D. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley, 1997.
`ISBN 0-471-14448-7.
`
`Page 21 of 153
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`

`

`Part
`
`I
`
`CMOS Fundamentals
`
`Page 22 of 153
`
`

`

`Page 23 of 153
`
`Page 23 of 153
`
`

`

`Chapter
`
`1
`
`Introduction
`
`the CMOS (complementary metal oxide semiconductor)
`This chapter discusses
`integrated circuit (IC) design process, how to set up the LASI (LAyout System for
`Individuals) layout software, and fabrication of CMOS integrated circuits through
`MOSIS (MOS Implementation Service).
`
`1.1 The CMOS IC Design Process
`
`The CMOS circuit design process consists of defining circuit inputs and outputs, hand
`calculations, circuit simulations, layout of the circuit, simulations including parasitics,
`reevaluation of the circuit inputs and outputs, fabrication, and testing. A flowchart of
`this process is shown in Fig. 1.1. The circuit specifications are rarely set in concrete;
`that is, they can change as the project matures. This can be the result of tradeoffs made
`between cost and performance, changes in the marketability of the chip, or simply
`changes in the customer's needs.
`In almost all cases, major changes after the chip has
`gone into production are not possible.
`
`This text concentrates on custom IC design. A custom-designed chip is often
`called an ASIC (application-specific integrated circuit). Other (noncustom) methods of
`designing chips, including field-programmable-gate-arrays (FPGAs) and standard cell
`libraries, are used when low volume and quick-design turnaround are important. Most
`chips that are mass produced, including microprocessors and memory, are examples of
`chips that are custom designed.
`
`it is
`The task of laying out the IC is often given to a draftsman. However,
`extremely important that the engineer be able to layout a chip (and direct the draftsman
`on how to lay the chip out) and understand the parasitics involved in the layout.
`Parasitics are the stray capacitances, inductances, pn junctions, and bipolar transistors,
`with the associated problems (breakdown, stored charge, latch-up, etc.). A fundamental
`understanding of these problems is important in precision/high-speed design.
`
`Page 24 of 153
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`

`

`4
`
`Part I CMOS Fundamentals
`
`Define circuit inputs
`and outputs
`(Circuit specifications)
`
`Hand calculations
`and schematics
`
`Circuit simulations
`
`No
`
`Layout
`
`Re-Simulate with parasitics
`
`No
`
`Does the circuit
`meet specs?
`
`Yes
`
`Prototype fabrication
`
`Testing and evaluation
`
`No, Fab Problem
`
`Does the circuit
`meet specs?
`
`Yes
`
`Production
`
`No, Spec Problem
`
`Figure 1.1 Flowchart for the CMOS IC design process.
`
`Page 25 of 153
`
`

`

`Chapter 1 Introduction
`
`1.1.1 Fabrication
`
`5
`
`CMOS integrated circuits are fabricated on thin circular slices of silicon called wafers.
`Each wafer contains several
`individual chips or "die" (Fig. 1.2). For production
`purposes each die on a wafer is usually identical. Added to the wafer are test structures
`and process monitor plugs (sections of the wafer used to monitor process parameters).
`
`A -
`
`dice fabricated with other die on the silicon wafer
`-""
`
`D~
`
`D Top
`=
`
`view
`
`Side
`view
`
`Wafer diameter is typically 5 to 8 inches.
`
`Figure 1.2 CMOS integrated circuits are fabricated on and in a silicon wafer.
`
`The ICs we design and layout using LASI can be fabricated through MOSIS [1]
`on what is called a multiproject wafer; that is, the wafer consists of chip designs of
`varying sizes from different sources (educational, private, gover