(12) United States Patent
`Oh
`
`USOO6417549B1
`(10) Patent No.:
`US 6,417,549 B1
`(45) Date of Patent:
`Jul. 9, 2002
`
`(54) STATIC RANDOM ACCESS MEMORY
`DEVICE AND METHOD FOR
`MANUFACTURING THE SAME
`
`(75) Inventor: Chang-bong Oh, Suwon (KR)
`(73) Assignee: Samsung Electronics Co., Ltd. (KR)
`(*) Notice:
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.:
`09/660,571
`Sep. 13, 2000
`(22) Filed:
`Foreign Application Priority Data
`(30)
`(KR) ............................................. 00-1338
`Jan. 12, 2000
`(51) Int. Cl." ................................................ H01L 29/72
`(52) U.S. Cl. ....................... 257/.401; 257/288; 257/314;
`365/63; 365/154; 365/190; 365/203; 365/205;
`365/207; 365/208; 365/233
`(58) Field of Search ................................. 257/.401, 288,
`257/314; 365/63, 203, 205, 207, 208, 190,
`233, 154
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,965,922 A * 10/1999 Matsui ....................... 257/369
`
`* cited by examiner
`
`Primary Examiner Edward Wojciechowicz
`(74) Attorney, Agent, or Firm Mills & Onello LLP
`(57)
`ABSTRACT
`A static random access memory (SRAM) device and a
`method for manufacturing the same are disclosed. In the
`SRAM device including a flip-flop circuit including two
`access transistors and a pair of inverters, connection lines for
`connecting the inputs and outputs of the inverters, and a
`word line, power Supply lines and bit lines are formed of a
`metal interconnection. The resistance of interconnection can
`be reduced and the SRAM device manufacturing process
`can be performed along with CMOS standard logic manu
`facturing process.
`
`25 Claims, 24 Drawing Sheets
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`Qualcomm Incorporated
`EX1004
`Page 1 of 38
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`U.S. Patent
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`Jul. 9, 2002
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`Sheet 1 of 24
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`US 6,417,549 B1
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`Page 2 of 38
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`U.S. Patent
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`Jul. 9, 2002
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`Sheet 9 of 24
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`U.S. Patent
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`U.S. Patent
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`Jul. 9, 2002
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`Sheet 12 of 24
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`Sheet 13 of 24
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`Sheet 14 of 24
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`U.S. Patent
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`Sheet 17 of 24
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`Jul. 9, 2002
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`Sheet 19 of 24
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`US 6,417,549 B1
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`Sheet 20 of 24
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`US 6,417,549 B1
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`Sheet 23 of 24
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`US 6,417,549 B1
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`U.S. Patent
`US. Patent
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`Jul. 9, 2002
`Jul. 9, 2002
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`Sheet 24 of 24
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`US 6,417,549 B1
`US 6,417,549 B1
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`US 6,417,549 B1
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`1
`STATIC RANDOMACCESS MEMORY
`DEVICE AND METHOD FOR
`MANUFACTURING THE SAME
`
`2
`FIG. 2 is a Sectional view showing part of the conven
`tional full CMOS type SRAM cell of FIG. 1, in which the
`input of the first CMOS inverter (the node C5 formed on the
`gate of the first load transistor Q5), the source 16 of the
`Second load transistor O6 and the drain 18 of the second
`access transistor Q2 (which shares the drain 18 with the
`second drive transistor Q4) are connected via the nodes C4
`and C2 by a local interconnection line 22.
`In FIG. 2, reference numeral 10 represents a semiconduc
`tor Substrate, reference numeral 12 represents a field oxide
`layer, reference numeral 14 represents the gate of the first
`load transistor Q5, reference numeral 16 represents the
`Source of the Second load transistor Q6, reference numeral
`18 represents the drain of the Second acceSS transistor Q2
`and the second drive transistor Q4, reference numeral 20
`represents an insulating layer, reference numeral 22 repre
`Sents the local interconnection line, reference numeral 24
`represents a first interlayer dielectric (ILD) film, reference
`numeral 26 represents a word line, reference numeral 28
`represents a second ILD film, reference numeral 30 repre
`Sents a power Supply line, reference numeral 32 represents
`a third ILD film, and reference numeral 34 represents a bit
`line.
`The input (refer to the gate 14 of the first load transistor
`Q5) of the first CMOS inverter is connected via the first local
`interconnection line, which is formed of a bilayer including
`a titanium (Ti) layer and a titanium nitride (TiN) layer, to the
`Source 16 of the second load transistor O6 and the drain 18
`of the Second access transistor Q2 and the Second drive
`transistor Q4. The input (not shown) of the second CMOS
`inverter is connected via a Second local interconnection line
`(not shown) to the source (not shown) of the first load
`transistor Q5 and the drain (not shown) of the first access
`transistor Q1 and the first drive transistor Q3.
`The word line 26 is connected to the gates of the first and
`Second access transistors Q1 (not shown) and Q2. The power
`supply line 30 and the bit lines are formed in different layers
`with a metal interconnection. In FIG. 2, the power Supply
`line 30 extends in the lateral direction and the bit line 34
`extends in the vertical direction.
`Merging the SRAM cell of FIG. 2 with a logic device
`requires additional processes based on a general CMOS
`Standard logic manufacturing process, thereby increasing the
`manufacturing cost due to the need for additional photoli
`thography processes and making the overall proceSS com
`plicated. In particular, as shown in FIG. 2, for the connection
`between the input of the first CMOS inverter and the output
`of the second CMOS inverter, and between the output of the
`second CMOS inverter and the input of the first CMOS
`inverter, the conventional full CMOS type SRAM requires
`the formation of the local interconnection line having a
`bilayer Structure including, for example, a Tilayer and a TiN
`layer, in addition to the general CMOS standard logic
`manufacturing process, and in turn additional masks there
`for.
`The word line 26 is formed of polysilicon, which is also
`used in forming the gate of the load transistor Q5. However,
`Similar to the formation of the local interconnection line,
`additional processes in addition to the general CMOS stan
`dard logic manufacturing proceSS must be carried out for the
`word line 26. Two more masks, one for the word line and the
`other for the contact hole connecting the word line and a
`transistor, are required, rendering the manufacturing process
`complicated.
`Also, when the SRAM cell of FIG. 2 is merged with a
`logic device without performing additional processes, the
`size of the SRAM cell increases beyond a desired size.
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates to a Semiconductor device
`and a method for manufacturing the same, and more
`particularly, to a Static random access memory device
`(SRAM) which can be manufactured by a CMOS standard
`logic manufacturing proceSS and a method for manufactur
`ing the Same.
`2. Description of the Related Art
`Static random access memories (SRAMs) are easy to use
`and operate faster compared to dynamic random acceSS
`memories (DRAM). For these reasons, the SRAMs have
`been used typically as a cache memory or a System memory
`in terminals. Recently, a development tendency of Semicon
`ductor devices towards high performance and composite
`functionality has raised use of SRAM embedded logic
`products, in which SRAMs and logic products are merged in
`one chip.
`Referring to FIG. 1, an equivalent circuit diagram of a unit
`memory cell of a general SRAM device is shown. As shown
`in FIG. 1, the SRAM cell is composed of two access
`transistorS Q1 and Q2 and a flip-flop circuit including a pair
`of CMOS inverters. The first inverter is composed of tran
`sistors Q5 and Q3, and the second inverter is composed of
`transistors O6 and Q4. SRAM cells are classified into one of
`three types including a resistor type SRAM, a thin film
`transistor type SRAM and a pull CMOS type SRAM,
`according to the type of load transistors, i.e., transistors Q5
`and Q6, of the flip-flop. Recently, the increasing need for
`low power Supply Voltage and high-speed products has
`raised interest in the full CMOS type SRAM.
`However, as shown in FIG. 1, the full CMOS SRAM
`requires six transistors Q1 through Q6 and twelve nodes C1
`through C12 to constitute one memory cell. Thus, it has high
`cell area, resulting in the disadvantage of leSS integration
`density, compared to the other two types of cells, which
`require only four transistors.
`In FIG. 1, the first access transistor Q1 and the second
`access transistor Q2 have their gates connected respectively
`via the nodes C9 and C10 to a word line WL, and their
`Sources connected respectively via the nodes C7 and C8 to
`first and Second bit lines BL1 and BL2. The first CMOS
`inverter, which is composed of the first load transistor Q5
`and the first drive transistor Q3, has an input connected via
`nodes C4 and C2, respectively, to the output of the Second
`CMOS inverter and the drain of the second access transistor
`Q2, and an output connected via the nodes C1 and C3,
`respectively, to the drain of the first access transistor Q1 and
`the input (i.e., the node C6) of the second CMOS inverter.
`The second CMOS inverter, which is composed of the
`Second load transistor Q6 and the Second drive transistor Q4,
`has an input (i.e., the node C6) connected via the nodes C3
`and C1, respectively, to the output of the first CMOS inverter
`and the drain of the first acceSS transistor Q1, and an output
`connected via the nodes C2 and C4, respectively, to the drain
`of the Second access transistor Q2 and the input (i.e., the
`node C5) of the first CMOS inverter. Also, the drains of the
`first and second load transistors Q5 and Q6 are connected via
`the node C12 to a first power Supply Voltage Vcc, and the
`Sources of the first and second drive transistors Q3 and Q4
`are connected via the node C11 to a Second power Supply
`Voltage VSS.
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`3
`SUMMARY OF THE INVENTION
`To solve the above problems, it is an object of the present
`invention to provide a Static random access memory
`(SRAM) device which can be manufactured by standard
`CMOS logic manufacturing processes without the need for
`additional masks or processes, wherein an increase in cell
`Size is minimized.
`Another object of the present invention is to provide a
`method for manufacturing an SRAM device by standard
`CMOS logic manufacturing processes without the need for
`additional masks or processes, wherein an increase in cell
`Size is minimized.
`The first object is achieved by a SRAM device compris
`ing: first and Second acceSS transistors each having a gate
`connected to a word line and a Source connected to a bit line.
`The SRAM also includes a first inverter including a first
`drive transistor and a first load transistor and a Second
`inverter including a Second drive transistor and a Second
`load transistor. A first connection line connects the input of
`the first inverter, the output of the second inverter and the
`drain of the Second access transistor. A Second connection
`line connects the input of the Second inverter, the output of
`the first inverter and the drain of the first access transistor.
`In the device of the invention, all conductive layers, other
`than the gates of the two access transistors and the gates of
`the transistors for the first and Second inverters, are formed
`of metal in different layers.
`In one embodiment, the multiple metal layers include a
`first metal layer which forms the first and Second connection
`lines, a Second metal layer which forms the word line, and
`a third metal layer which forms bit lines and power Supply
`lines connected to the first and Second inverters.
`In one embodiment, the multiple metal layers include a
`first metal layer which forms the first and Second connection
`lines, a Second metal layer which forms the word line, a third
`metal layer which forms bit lines, and a fourth metal layer
`which forms power Supply lines connected to the first and
`Second inverters.
`In another aspect, the SRAM device according to the
`present invention includes a flip-flop circuit including two
`access transistors and a pair of inverters. The SRAM device
`comprises a Semiconductor Substrate in which parallel first
`and Second active regions of a first conductive type are
`arranged and third and fourth active regions of a Second
`conductive type are arranged between the first and Second
`active regions. First conductive layers act as the gates of the
`first acceSS transistor and the first drive transistor which
`extend perpendicular to the first active region for Serial
`connection between the first access and drive transistors, as
`the gates of the Second access transistor and the Second drive
`transistors which extend perpendicular to the Second active
`region for Serial connection between the Second access and
`drive transistors, as the gate of the first load transistor which
`extends perpendicular to the third active region, and as the
`gate of the Second load transistor which extends perpen
`dicular to the fourth active region. Second conductive layers
`act as a first connection line which connects the drain of the
`first access transistor and the first drive transistor, the gate of
`the Second drive transistor, the gate of the Second load
`transistor connected to the gate of the Second drive
`transistor, and the Source of the first load transistor, and as
`a Second connection line which connects the drain of the
`Second acceSS transistor and the Second drive transistor, the
`gate of the first drive transistor, the gate of the first load
`transistor connected to the gate of the first drive transistor,
`and the Source of the Second load transistor. A third con
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`ductive layer acts as a word line connected to the gate of the
`first access transistor and the gate of the Second access
`transistor. Fourth conductive layerS act as a first power
`Supply line connected to the drain of the first load transistor
`and the drain of the Second load transistor, as a Second power
`Supply line connected to the Source of the first drive tran
`Sistor and the Source of the Second drive transistor, as a first
`bit line connected to the Source of the first access transistor,
`and as a Second bit line connected to the Source of the Second
`access transistor.
`In one embodiment of this aspect of the invention, the first
`and Second active regions are formed acroSS a cell in a bar
`shape, and the third and fourth active regions are arranged
`in a Staggered manner parallel to the first and Second active
`regions. The first active region can have a wider width at
`regions overlapped by the gate of the first drive transistor
`than at regions overlapped by the gate of the first access
`transistor, and the Second active region can have a wider
`width at regions overlapped by the gate of the Second drive
`transistor than at regions overlapped by the gate of the
`Second access transistor.
`In addition, in one embodiment of this aspect of the
`invention, the gate of the first drive transistor arranged
`perpendicular to the first active region and the gate of the
`first load transistor arranged perpendicular to the third active
`region are laterally connected to cover one end of the fourth
`active region, and the gate of the Second drive transistor
`arranged perpendicular to the Second active region and the
`gate of the Second load transistor arranged perpendicular to
`the fourth active region are laterally connected to cover one
`end of the third active region.
`The gate of the first acceSS transistor, the gate of the
`Second drive transistor and the gate of the Second load
`transistor can be located in a line, and the gate of the Second
`access transistor, the gate of the first drive transistor and the
`gate of the first load transistor can be located in another line
`parallel to the gates of the first acceSS transistor, Second drive
`transistor and Second load transistor.
`The first connection line and the Second connection line
`can be arranged, not overlapping each other, and the ele
`ments connected to the Second connection line are not
`overlapped by the first connection line, and the elements
`connected to the first connection line are not overlapped by
`the Second connection line.
`The first connection line can connect the drain of the first
`access transistor and the first drive transistor, the gate of the
`Second drive transistor, the gate of the Second load transistor,
`and the Source of the first load transistor via a contact hole
`C1/C3 formed on the drain of the first access transistor and
`the first drive transistor and a contact hole C6 formed over
`the gate of the Second load transistor overlapped by the one
`end of the third active region, and the Source of the first load
`transistor, and the Second connection line can connect the
`drain of the Second access transistor and the Second drive
`transistor, the gate of the first drive transistor, the gate of the
`first load transistor and the Source of the Second load
`transistor via a contact hole C2/C4 formed on the drain of
`the Second access transistor and the Second drive transistor
`and a contact hole C5 formed over the gate of the first load
`transistor overlapped by one end of the fourth active region,
`and the Source of the Second load transistor. The first and
`Second connection lines can be formed of polysilicon, amor
`phous Silicon, aluminum (Al), tungsten (W), titanium (TI),
`cobalt (Co) or copper (Cu).
`The word line can be connected to a first pad layer C9
`which is formed of the first conductive layer and is con
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`nected to the gate of the first access transistor, and a first pad
`layer C10 which is formed of the first conductive layer and
`is connected to the gate of the Second access transistor. The
`word line may be arranged parallel to the gates of the
`transistors and acroSS a cell in a bar shape.
`In one embodiment, the first power line, the Second power
`line, the first bit line and the Second bit line are arranged
`perpendicular to the word line. The first power Supply line
`can be arranged between and parallel to the first and Second
`bit lines, and the Second power Supply lines can be arranged
`between and parallel to the first and second bit lines between
`which the first power Supply line is not formed.
`The first power Supply line can Supply the Supplying
`power Supply Voltage to the drains of the first and Second
`load transistors, respectively, via a first pad layer C12
`formed of the second conductive layer over the drain of the
`first load transistor and via a Second pad layer C12 formed
`of the third conductive layer over the drain of the second
`load transistor. The Second power Supply line can Supply
`ground Voltage to the Sources of the first and Second drive
`transistors, respectively, via a first pad layer C11 formed of
`the second conductive layer over the source of the first drive
`transistor and via a second pad layer C11 formed of the third
`conductive layer over the Source of the Second drive tran
`sistor. The first bit line can supply a bit line or bit line bar
`Voltage to the Source of the first access transistor via a first
`pad layer C7 formed of the second conductive layer and a
`first pad layer C7 formed of the third conductive layer over
`the Source of the first access transistor. The Second bit line
`can Supply a bit line bar orbit line Voltage to the Source of
`the Second access transistor via a first pad layer C8 formed
`of the Second conductive layer and a Second pad layer C8
`formed of the third conductive layer over the source of the
`Second access transistor.
`In one embodiment, the Second through fourth conductive
`layers are a metal layer.
`In another aspect of the invention, there is provided an
`SRAM including a flip-flop circuit including two acceSS
`transistors and a pair of inverters. The device includes a
`Semiconductor Substrate in which parallel first and Second
`active regions of a first conductive type are arranged and
`third and fourth active regions of a Second conductive type
`are arranged between the first and Second active regions.
`First conductive layers act as (i) the gates of the first access
`transistor and the first drive transistor which extend perpen
`dicular to the first active region for Serial connection
`between the first access and drive transistors, (ii) the gates
`of the Second acceSS transistor and the Second drive tran
`Sistors which extend perpendicular to the Second active
`region for Serial connection between the Second access and
`drive transistors, (iii) the gate of the first load transistor
`which extends perpendicular to the third active region, and
`(iv) the gate of the Second load transistor which extends
`perpendicular to the fourth active region. Second conductive
`layerS formed of a metal layer act as a first connection line
`which connects the drain of the first access transistor and the
`first drive transistor, the gate of the Second drive transistor,
`the gate of the Second load transistor connected to the gate
`of the Second drive transistor, and the Source of the first load
`transistor, and as a Second connection line which connects
`the drain of the Second access transistor and the Second drive
`transistor, the gate of the first drive transistor, the gate of the
`first load transistor connected to the gate of the first drive
`transistor, and the Source of the Second load transistor. A
`third conductive layer formed of a metal layer acts as a word
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`line connected to the gate of the first access transistor and the
`gate of the Second access transistor. Fourth conductive
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`layerS formed of a metal layer act as a first bit line connected
`to the Source of the first access transistor and as a Second bit
`line connected to the Source of the Second access transistor.
`Fifth conductive layers formed of a metal layer act as a first
`power Supply line connected to the drain of the first and
`Second load transistors, and as a Second power Supply line
`connected to the Source of the first and Second drive tran
`Sistors.
`The second object is achieved by a method for manufac
`turing a static random access memory (SRAM) device
`including a flip-flop including two access transistors and a
`pair of inverters. In accordance with the method, first and
`Second active regions are defined in a Semiconductor Sub
`Strate parallel to each other, and third and fourth active
`regions are simultaneously arranged between the first and
`Second active regions parallel to each other. A gate oxide
`layer is formed on the Substrate having the first through
`fourth active regions, and the gates of the first access
`transistor and the first drive transistor are formed perpen
`dicular to the first active region for Serial connection
`between the first access transistor and the first drive tran
`Sistor. The gates of the Second access transistor and the
`Second drive transistor are formed perpendicular to the
`Second active region for Serial connection between the
`Second access transistor and the Second drive transistor. The
`gate of the first load transistor is formed perpendicular to the
`third active region, and the gate of the Second load transistor
`is formed perpendicular to the fourth active region. Then, a
`first interlayer dielectric (ILD) film is formed on the Sub
`Strate having the gates of the transistors, and the first ILD
`film is selectively etched to form (i) a contact hole C1/C3
`over the drain of the first access transistor and the first drive
`transistor, (ii) a contact hole C6 over the gate of the second
`load transistor and the Source of the first load transistor
`connected to the gate of the Second drive transistor, (iii) a
`contact hole C2/C4 over the drain of the second access
`transistor and the first drive transistor, and (iv) a contact hole
`C5 over the gate of the first load transistor and the source of
`the Second load transistor connected to the gate of the first
`drive transistor. A Second conductive layer is formed and
`Selectively patterned to form a first connection line for
`connecting the drains of the first access transistor and first
`drive transistor, the gates of the Second drive transistor and
`Second load transistor, and the Source of the first load
`transistor via the contact holes C1/C3 and C6 and to form a
`Second connection line for connecting the drains of the
`Second access transistor and Second drive transistor, the
`gates of the first drive transistor and first load transistor, and
`the Source of the Second load transistor via the contact holes
`C2/C4 and C5. Then, a second ILD film is formed and then
`selectively patterned to form a first via hole C9 over the gate
`of the first access transistor and a first via hole C10 over the
`gate of the Second acceSS transistor. A third conductive layer
`is formed and then selectively patterned to form a word line
`connected to the gates of the first access transistor and the
`Second access transistor via the first via holes C9 and C10,
`respectively. A second ILD film is formed and selectively
`patterned to form a second via hole C12 over the drain of the
`first and Second load transistors, a Second via hole C11 over
`the Source of the first and Second drive transistors, a Second
`via hole C7 over the Source of the first access transistor, and
`a Second via hole C8 over the Source of the Second access
`transistor. Then, a fourth conductive layer is formed and
`Selectively patterned to form a first power Supply line
`connected to the drain of the first and Second load transistors
`via the Second via hole C12, a Second power Supply line
`connected to the Source of the first and Second drive tran
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`sistors via the Second via hole C11, a first bit line connected
`to the Sour