(12) United States Patent
`Jin
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,534,805 B1
`Mar. 18, 2003
`
`USOO6534.805B1
`
`(54) SRAM CELL DESIGN
`(75) Inventor: Bo Jin, Campbell, CA (US)
`(73) Assignee: Cypress Semiconductor Corp., San
`Jose, CA (US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(*) Notice:
`
`(21) Appl. No.: 09/829,510
`(22) Filed:
`Apr. 9, 2001
`(51) Int. Cl. .......................... H01L 27/10; H01L 21/84
`(52) U.S. Cl. ....................... 257/206; 257/211; 257/369;
`438/153
`(58) Field of Search ................................. 257/204, 206,
`257/211,369,390, 393; 438/152, 153,
`238
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4/1997 Ohno ......................... 257/288
`5,621,232 A
`5,654.915 A 8/1997 Stolmeijer et al. .......... 365/156
`5,804,477 A * 9/1998 Lien .................... ... 438/210
`6,103,579 A * 8/2000 Violette ........
`... 438/279
`6,150,685. A 11/2000 Ashida et al. .............. 257/296
`FOREIGN PATENT DOCUMENTS
`
`JP
`JP
`JP
`
`11-195716
`2000243858
`2001168211
`
`....... HO1 L/21/8244
`* 7/1999
`* 9/2000 ....... HO1 L/21/8244
`6/2001
`....... HO1 L/21/8244
`
`OTHER PUBLICATIONS
`Ueshima et al., “A 5-lum Full-CMOS Cell for High-Speed
`SRAMs Utilizing an Optical-Proximity-Effect Correction
`(OPC) Technology,” 1996, pp. 146-147.
`
`
`
`Woo et al., “A High Performance 3.97 um CMOS SRAM
`Technology Using Self-Aligned Local Interconnect and
`Copper Interconnect Metallization,' 2 pgs.
`
`* cited by examiner
`
`Primary Examiner Mary Wilczewski
`ASSistant Examiner Toniae M. Thomas
`(74) Attorney, Agent, or Firm--Kevin L. Daffer; Conley,
`Rose & Tayon P.C.
`(57)
`
`ABSTRACT
`
`An embodiment of a memory cell includes a Series of four
`Substantially oblong parallel active regions, arranged side
`by-Side Such that the inner active regions of the Series
`include Source/drain regions for p-channel transistors, and
`the outer active regions include Source/drain regions for
`n-channel transistors. Another embodiment of the memory
`cell includes Six transistors having gates Substantially par
`allel to one another, where three of the gates are arranged
`along a first axis and the other three gates are arranged along
`a Second axis parallel to the first axis. In another
`embodiment, the memory cell may include Substantially
`oblong active regions arranged Substantially in parallel with
`one another, with Substantially oblong local interconnects
`arranged above and Substantially perpendicular to the active
`regions. A method for fabricating a memory cell may include
`forming Substantially oblong active regions within a Semi
`conductor Substrate, and forming Substantially oblong local
`interconnects above and perpendicular to the active regions.
`
`10 Claims, 3 Drawing Sheets
`
`Qualcomm Incorporated
`EX1001
`Page 1 of 14
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`U.S. Patent
`US. Patent
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`Mar. 18, 2003.
`Mar. 18, 2003
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`Sheet 1 of 3
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`US 6,534,805 B1
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`U.S. Patent
`US. Patent
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`Mar. 18, 2003
`Mar. 18, 2003
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`Sheet 2 of 3
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`U.S. Patent
`US. Patent
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`Mar. 18, 2003
`Mar. 18, 2003
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`Sheet 3 of 3
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`US 6,534,805 B1
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`US 6,534,805 B1
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`1
`SRAM CELL, DESIGN
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`BACKGROUND OF THE INVENTION
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`1. Field of the Invention
`This invention relates to Semiconductor memory device
`fabrication, and more particularly to an improved Static
`Random Access Memory (SRAM) cell design and method
`of manufacture.
`2. Description of the Related Art
`The proliferation of computers and other microprocessor
`based devices has contributed to an increasing demand for
`Semiconductor memory. Microprocessors are present not
`only in computers, but in a diverse range of products
`including automobiles, cellular telephones and kitchen
`appliances. A conventional microprocessor executes a
`Sequence of instructions and processes information.
`Frequently, both the instructions and the information reside
`in Semiconductor memory. Therefore, an increased require
`ment for memory has accompanied the microprocessor
`boom.
`There are various types of Semiconductor memory,
`including Read Only Memory (ROM) and Random Access
`Memory (RAM). ROM is typically used where instructions
`or data must not be modified, while RAM is used to store
`instructions or data which must not only be read, but
`modified. ROM is a form of non-volatile storage- i.e., the
`information stored in ROM persists even after power is
`removed from the memory. On the other hand, RAM storage
`is generally volatile, and must remain powered-up in order
`to preserve its contents.
`A conventional Semiconductor memory device Stores
`information digitally, in the form of bits (i.e., binary digits).
`The memory is typically organized as a matrix of memory
`cells, each of which is capable of Storing one bit. The cells
`of the memory matrix are accessed by Wordlines and bit
`lines. Wordlines are typically associated with the rows of the
`memory matrix, and bitlines with the columns. Raising a
`Wordline activates a given row; the bitlines are then used to
`read from or write to the corresponding cells in the currently
`active row. Memory cells are typically capable of assuming
`one of two voltage States (commonly described as “on” or
`“off”). Information is stored in the memory by setting each
`cell in the appropriate logic State. For example, to Store a bit
`having the value 1 in a particular cell, one would set the State
`of that cell to “on; similarly, a 0 would be stored by setting
`the cell to the “off” state. (Obviously, the association of “on”
`with 1 and “off” with 0 is arbitrary, and could be reversed.)
`The two major types of semiconductor RAM, Static
`Random Access Memory (SRAM) and Dynamic Random
`Access Memory (DRAM), differ in the manner by which
`their cells represent the state of a bit. In an SRAM, each
`memory cell includes transistor-based circuitry that imple
`ments a bistable latch. A bistable latch relies on transistor
`gain and positive (i.e. reinforcing) feedback to guarantee
`that it can only assume one of two states “on” or “off.” The
`latch is stable in either state (hence, the term “bistable”). It
`can be induced to change from one State to the other only
`through the application of an external Stimulus, left
`undisturbed, it will remain in its original State indefinitely.
`This is just the Sort of operation required for a memory
`circuit, Since once a bit value has been written to the memory
`cell, it will be retained until it is deliberately changed.
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`In contrast to the SRAM, the memory cells of a DRAM
`employ a capacitor to store the “on”/“off voltage state
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`representing the bit. A transistor-based buffer drives the
`capacitor. The buffer quickly charges or discharges the
`capacitor to change the State of the memory cell, and is then
`disconnected. Ideally, the capacitor then holds the charge
`placed on it by the buffer and retains the stored voltage level.
`DRAMs have at least two drawbacks compared to
`SRAMs. The first of these is that leakage currents within the
`Semiconductor memory are unavoidable, and act to limit the
`length of time the memory cell capacitors can hold their
`charge. Consequently, DRAMs typically require a periodic
`refresh cycle to restore Sagging capacitor Voltage levels.
`Otherwise, the capacitive memory cells would not maintain
`their contents. Secondly, changing the State of a DRAM
`memory cell requires charging or discharging the cell
`capacitor. The time required to do this depends on the
`amount of current the transistor-based buffer can Source or
`Sink, but generally cannot be done as quickly as a bistable
`latch can change State. Therefore, DRAMs are typically
`slower than SRAMs. DRAMs offset these disadvantages by
`offering higher memory cell densities, Since the capacitive
`memory cells are intrinsically Smaller than the transistor
`based cells of an SRAM.
`AS microprocessors have become more Sophisticated,
`greater capacity and Speed are demanded from the associ
`ated memory. SRAMs are widely used in applications where
`Speed is of primary importance, Such as cache memory
`supporting the Central Processing Unit (CPU) in a personal
`computer. Like most Semiconductor devices, SRAMs are
`fabricated en masse on Semiconductor wafers.
`Fabrication of a metal-oxide-semiconductor (MOS) inte
`grated circuit involves numerous processing Steps. A gate
`dielectric, typically formed from silicon dioxide (“oxide'),
`is formed on a semiconductor Substrate which is doped with
`either n-type or p-type impurities. Conductive regions and
`layers of the device may be isolated from one another by an
`interlevel dielectric. For each MOS field effect transistor
`(MOSFET) being formed, a gate conductor is formed over
`the gate dielectric, and dopant impurities are introduced into
`the Substrate to form a Source and drain. Frequently, the
`integrated circuit will employ a conducting layer to provide
`a local interconnect function as well. A pervasive trend in
`modern integrated circuit manufacture is to produce tran
`Sistors that are as fast as possible and thus have feature sizes
`as Small as possible. Many modern day processes employ
`features, Such as gate conductors and interconnects, which
`have less than 1.0 lim critical dimension. AS feature size
`decreases, the sizes of the resulting transistor and the inter
`connect between transistorS also decrease. Fabrication of
`Smaller transistorS allows more transistors to be placed on a
`Single monolithic Substrate, thereby allowing relatively large
`circuit Systems to be incorporated on a Single, relatively
`Small die area.
`However, integrated circuits become increasingly difficult
`to manufacture as their dimensions are reduced. Integrated
`circuits with complex geometries may be particularly diffi
`cult to manufacture as dimensions are reduced.
`Consequently, integrated circuit designs without complex
`geometries are preferable. Further, reducing the number of
`Steps in an integrated circuit's manufacturing proceSS flow is
`desired. Reducing the number of processing Steps often
`results in higher profits. Clearly, it would be desirable to
`have an improved circuit design and method of manufacture
`to facilitate fabrication of Smaller and faster SRAMS.
`SUMMARY OF THE INVENTION
`The problems outlined above may be addressed by an
`improved circuit design and method of fabrication disclosed
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`3
`herein for an integrated circuit, specifically a Semiconductor
`memory device. In the embodiments considered herein, the
`Semiconductor memory device is a Static random acceSS
`memory (SRAM) device, but it is believed that principles
`disclosed herein are applicable to other types of integrated
`circuits as well. For example, any device requiring local
`interconnection of multiple active regions and gates may be
`Suitable.
`A memory cell is disclosed herein including a Series of
`four Substantially oblong parallel active regions. The active
`regions are arranged Such that the inner active regions
`comprise Source/drain regions for p-channel transistors,
`while the outer active regions comprise Source/drain regions
`for n-channel transistors. Substantially oblong polysilicon
`Structures may be arranged above and Substantially perpen
`dicular to the active regions. Substantially oblong local
`interconnects may also be arranged above and Substantially
`perpendicular to the active regions. Each active region may
`include Source/drain regions for no more than two transis
`tors. Source/drain contacts to the Source/drain regions of the
`transistors may include at least one shared contact, Such that
`the shared contact is connected to a polysilicon Structure as
`well as an inner Source/drain region. A shared contact may
`be connected to a Source/drain contact using a local inter
`connect. In an embodiment, the local interconnect is dielec
`trically Spaced above the Substrate. In an alternate
`embodiment, the local interconnect may have an upper
`Surface Substantially commensurate with the upper Surface
`of at least one respective contact.
`A memory cell including six transistors with gates that are
`Substantially parallel to one another is also disclosed. Three
`of the gates are arranged along a first axis, and the other
`three are arranged along a second axis parallel to the first
`axis. Two of the gates along an axis may be arranged within
`a single polysilicon Structure. Of these two, one may be a
`gate for a p-channel transistor and the other may be a gate
`for an n-channel transistor. The third gate along an axis may
`be arranged within another polysilicon Structure. This Sec
`ond polysilicon Structure may be electrically coupled to a
`respective local wordline. Each of the two local wordlines
`may be electrically coupled to a global wordline, which in
`an embodiment comprises metal. Also included in the
`memory cell may be a shared contact arranged between the
`axes and in contact with a Source/drain region of a p-channel
`transistor along one axis and a polysilicon Structure along
`the other axis. In an embodiment, the memory cell may also
`include an active region Substantially perpendicular to the
`axes and electrically coupled to a bitline where the bitline
`extends acroSS the entire length of the memory cell. The
`bitline may be Substantially parallel to the active region, and
`the length of the bitline may be less than a third of the width
`of the cell.
`In an embodiment, a memory cell is disclosed having
`Substantially oblong active regions arranged Substantially in
`parallel with one another within a Semiconductor Substrate.
`The memory cell also has multiple local interconnects
`arranged above and Substantially perpendicular to the active
`regions, where the interconnects are also Substantially
`oblong and in parallel with one another. In an embodiment,
`the memory cell may also include Substantially Square local
`interconnects Such that all interconnects are either Substan
`tially oblong or Substantially Square. In an embodiment, the
`memory cell may also include a shared contact that is
`electrically coupled to an active region and a polysilicon
`Structure abutting Said active region.
`Also disclosed herein is a method of fabricating a memory
`cell including forming Substantially oblong active regions
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`arranged Substantially in parallel with one another within a
`Semiconductor Substrate. The method also includes forming
`Substantially oblong local interconnects arranged above the
`Semiconductor Substrate where the interconnects are Sub
`Stantially in parallel with one another and Substantially
`perpendicular to the active regions. In an embodiment,
`forming the local interconnects may include etching a trench
`through a dielectric material and depositing a conductive
`material into the trench. The method may include forming
`Substantially oblong polysilicon Structures arranged above
`the Semiconductor Substrate where the polysilicon Structures
`are Substantially in parallel with one another and Substan
`tially perpendicular to the active regions. Forming the poly
`Siliconstructures may include forming an acceSS polysilicon
`Structure for each of two access transistor gates within the
`memory cell, where the access polysilicon Structures do not
`extend acroSS the entire memory cell. In an embodiment,
`forming the memory cell may include forming a global
`wordline, where the wordline is dielectrically spaced above
`the active regions and where the Wordline is electrically
`coupled to the access polysilicon Structures.
`The improved circuit design and method of fabrication
`disclosed herein may provide numerous advantages. This
`circuit design may be improved because the memory cell
`layout may allow the features to be arranged in Such a way
`as to minimize cell size. Another advantage of the improved
`circuit design is the Substantially parallel features that
`reduce manufacturing complexities, particularly in photoli
`thography. As a result of the Substantially parallel layout,
`reducing feature sizes to increase device Speeds and/or to
`minimize memory cell Size may be facilitated. In addition,
`the Substantially parallel layout may change the aspect ratio
`of the memory cell Such that the bitlines may be reduced in
`length, thus advantageously decreasing bitline resistivity
`and increasing memory cell performance. Furthermore, this
`circuit design may be improved because of the Symmetrical
`the layout design, which may improve noise margins. Yet
`another advantage of the improved circuit design is the
`elimination of polysilicon wordlines that traverse the
`entirety of the memory cell. Elimination of Such polysilicon
`Wordlines may minimize cell size by reducing the density of
`features required on the polysilicon layer of the cell. Reduc
`ing the amount of polysilicon in the wordlines may also
`result in increased use of a metal layer to perform the
`Wordline function, thus advantageously decreasing Wordline
`resistivity and increasing memory cell performance. A fur
`ther advantage of the improved circuit design is that the
`improved polysilicon layer may partially perform local
`interconnecting functions. Therefore, the Subsequent local
`interconnect layer may be greatly Simplified and the local
`interconnects may also be arranged Substantially in parallel.
`The improved layout may further enable the use of a trench
`local interconnect layer, thus reducing the number of pro
`cessing Steps.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`Other objects and advantages of the invention will
`become apparent upon reading the following detailed
`description and upon reference to the accompanying draw
`ings in which:
`FIG. 1 shows the transistor configuration of an embodi
`ment of an improved SRAM memory cell;
`FIG. 2 represents a layout of the active regions and
`polysilicon structures for the embodiment of FIG. 1; and
`FIG.3 represents a layout of the local interconnect for the
`regions and structures shown in FIG. 2.
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`US 6,534,805 B1
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`S
`While the invention is susceptible to various modifica
`tions and alternative forms, specific embodiments thereof
`are shown by way of example in the drawings and will
`herein be described in detail. It should be understood,
`however, that the drawings and detailed description thereto
`are not intended to limit the invention to the particular form
`disclosed, but on the contrary, the intention is to cover all
`modifications, equivalents and alternatives falling within the
`Spirit and Scope of the present invention as defined by the
`appended claims.
`
`6
`voltage and node 12 is at the ground potential (VSS), when
`the wordline 17 is brought to a high voltage, the pull-down
`transistor 3 and the access transistor 4 are both turned on and
`will thus pull the bitline “/Bit 15 down toward the ground
`potential Vss. Moreover, the load transistor 5 and the access
`transistor 1 are also tuned on; thus the bitline “Bit 16 will
`be pulled up towards the Vcc potential. Thus the state of the
`cell 10 (either “1” or “0”) can be determined by sensing the
`difference in potential between the bitlines 15 and 16.
`Conversely, writing a “1” or a “0” into the cell 10 can be
`accomplished by forcing the bitline 15 or the bitline 16 to
`either Vcc or VSS and then raising the wordline 17. The
`potential placed on either the bitline “/Bit 15 or the bitline
`“Bit 16 will then be transferred to the node 11 or 12,
`respectively, forcing the cell 10 into either a corresponding
`“1” state or a “0” state.
`Shown in FIG. 2 is an embodiment of a layout 20 that may
`be used to form in silicon the memory cell 10 represented in
`FIG. 1. (Elements appearing in more than one figure retain
`the same item numbers throughout the figures.) FIG. 2
`presents a top-down view of an exemplary memory cell
`layout 20. Layout 20 illustrates the active regions, isolation
`regions, polysilicon Structures, and contact Structures that
`may be used to form the typical metal oxide Semiconductor
`(MOS) transistors, NMOS and PMOS, used in a typical
`CMOS SRAM. In the embodiment of FIG. 2, NMOS
`transistors 1-4 are formed within active regions 21 and 24,
`and PMOS transistors 5 and 6 are formed within active
`regions 22 and 23. The active regions are formed within a
`Semiconductor Substrate. The Semiconductor Substrate may
`preferably be a Silicon Substrate doped n-type and p-type in
`the vicinity of the p-channel transistors and the n-channel
`transistors, respectively. More specifically, the Semiconduc
`tor Substrate may include n-type and p-type well regions
`formed in a monocrystalline Silicon Substrate, or in an
`epitaxial Silicon layer grown on a monocrystalline Silicon
`Substrate.
`Active regions, i.e., areas where active transistors are to
`be formed, are labeled 21-24 and are arranged side-by-side
`and Substantially parallel to each other. Diffusion regions are
`also to be formed within the active regions 21-24. For
`example, diffusion regions may be lightly doped drain
`regions and heavily doped Source/drain regions formed in
`active regions adjacent to the transistor gate Structures.
`Dielectric isolation regions such as 29 and 30 separate active
`regions from one another. Isolation regions may be formed
`by a number of techniqueS Such as shallow trench isolation
`(STI), recessed oxide isolation (ROI), or local oxidation of
`silicon (LOCOS). Isolation regions may therefore be field
`oxide regions, which Serve to isolate Separate active regions
`on the Semiconductor layer from one another.
`In the embodiment of FIG. 2, NMOS active regions 21
`and 24 are utilized for the formation of two transistors each,
`a pass transistor and a latch transistor. PolySilicon Structures
`25 and 27 are arranged above active region 21 to form gates
`of pass transistor 1 and latch transistor 2, respectively.
`Similarly, above active region 24, polysilicon Structures 28
`and 26 are arranged to form gates of pass transistor 4 and
`latch transistor 3, respectively. Consequently, active regions
`21 and 24 each have two gate conductors arranged above
`them. In this embodiment, no active region has more than
`two gate conductors arranged above it, and therefore no
`active region forms more than two transistors.
`In the embodiment of FIG. 2, the active regions are
`Substantially oblong, and in Some cases may be Substantially
`rectangular as well. For example, PMOS active regions,
`
`DETAILED DESCRIPTION OF PREFERRED
`EMBODIMENTS
`A circuit diagram for an improved double wordline
`SRAM memory cell is shown in FIG. 1. Generally stated,
`SRAM memory cells may be formed by interconnecting two
`CMOS inverters together so that the input of a first inverter
`is tied to the output of a Second inverter and Vice versa to
`form a positive feedback orientation. Such configuration of
`two inverters is commonly referred to as a bi-stable latch as
`described above. The inverters include transistors com
`monly referred to as latch transistors. In the embodiment of
`FIG. 1, transistors 2 and 5 form the first inverter, transistors
`3 and 6 form the Second inverter, the node representing the
`input of the first inverter is labeled 12, and the node
`representing the input of the Second inverter is labeled 11.
`Thus, the memory cell 10 comprises four latch transistors 2,
`3, 5, and 6 and two access transistors 1 and 4, each of which
`has a drain, Source and gate. The latch transistorS 2, 3, 5, and
`6 include a pair of n-channel pull-down transistorS 2 and 3
`and a pair of p-channel load transistorS 5 and 6.
`The inverters are connected as follows to form the
`bi-stable latch of FIG. 1. A drain 2d of pull-down transistor
`2 is coupled to a drain 5d of load transistor 5 at node 11 and
`a drain 3d of a pull-down transistor 3 is coupled to a drain
`6d of load transistor 6 at node 12. These nodes 11 and 12
`Store opposite logic States (i.e., one is a logic “1” while the
`other is a logic “0”). Sources 5s and 6s of transistors 5 and
`6 are coupled to a common power line 13 (hereinafter
`referred to as a “Vcc line”) while sources. 2s and 3s of
`pull-down transistors 2 and 3 are coupled to a common
`ground line 14 (hereinafter referred to as a “Vss line”). Gates
`2g and 5g of transistors 2 and 5 are coupled together and
`connected to the node 12 and gates 3g and 6g of transistors
`3 and 6 are coupled together and connected to node 11.
`Such interconnections create positive feedback, which
`allows the memory cell to store data as either a “high” or
`“low” input (i.e., a logic “1” or “0”). Data is stored in these
`memory cells during a “write cycle” and that data is Sub
`Sequently read during a “read cycle. The n-channel acceSS
`transistors 1 and 4 are coupled to the memory cell 10 to
`allow communication between the cell 10 and an external
`device through a pair of complementary bitlines 15 and 16.
`With respect to the access transistorS 1 and 4, each Source 1S
`and 4S is coupled to nodes 11 and 12, respectively. A drain
`1d of access transistor 1 is coupled to a bitline 16, referred
`to as “Bit,” which operates as a data line to read data from
`and write data into the memory cell 10. A drain 4d of a
`Second acceSS transistor 4 is similarly coupled to a comple
`mentary bitline 15 called “/Bit,” In addition, both gates 1g
`and 4g are coupled to wordline 17.
`Applying a positive Voltage to the Wordline 17 turns on
`both access transistorS 1 and 4, thus accessing memory cell
`10. This allows one of the two bitlines 15 and 16 to sense the
`contents of the memory cell 10 based on the voltage at either
`node 11 or 12. For example, if node 11 is at a high (Vcc)
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`Such as active regions 22 or 23 shown in FIG. 2, may have
`a length that is Substantially constant acroSS the width of the
`region, as well as a width that is Substantially constant along
`the length of the region. However, if an NMOS active region
`is forming an access transistor and a latch transistor, it may
`have Some variation in width although the length may be
`Substantially constant acroSS the width of the region. For
`example, active regions 21 and 24 as shown in FIG. 2 are
`each forming access transistorS 1 and 4, respectively, and
`latch transistorS 2 and 3, respectively. By design, acceSS
`transistors frequently have widths that are Smaller than those
`of adjacent latch transistors. The active region is thus
`designed to ensure the stability of the SRAM. This design
`feature is commonly referred to as the “beta ratio.” A beta
`ratio is defined as the width of the latch transistor divided by
`the width of the pass transistor. To ensure circuit stability, the
`beta ratio should be >1. In an embodiment, the beta ratio is
`approximately 1.5. Therefore, in an embodiment, the width
`of the access transistor is approximately 73 the width of the
`latch transistor. Consequently, an NMOS active region may
`be considered to be substantially oblong if the length of the
`region is Substantially constant and if the width of the region
`varies by approximately /3 or leSS along the length of the
`region. Further, an NMOS active region may be considered
`to be Substantially oblong if the length of the region is
`Substantially constant and the width of the region by design
`varies only with the respective widths of the access and latch
`transistors. In an embodiment, “Substantially oblong may
`refer to any region or Structure having a length that is greater
`than or equal to approximately three times its maximum
`width. Active regions as described above are oblong with
`respect to, for example, the markedly “L-shaped” regions
`formed in layouts for which two transistors are arranged at
`right angles to each other.
`Each transistor includes a gate electrode formed above an
`active region, arranged between a pair of Source/drain
`regions, and Separated from the Substrate by a relatively thin
`dielectric. In a preferred embodiment, gate electrodes are
`arranged within polysilicon structures 25-28 to form tran
`sistors 1-6 as shown in FIG. 2. The polysilicon may be
`deposited by, for example, using chemical vapor deposition
`(CVD) of silicon from a silane source. However, the gate
`electrodes may comprise any Suitable conductive material
`Such as polysilicon, aluminum, or copper. Therefore Struc
`tures 25-28 are not limited to polysilicon. For example, the
`gate electrodes may include multiple layers of material, Such
`as a doped polysilicon and a Silicide. A Silicide may be
`formed from a polysilicon layer upon which a layer of
`refractory metal Such as cobalt or titanium has been formed.
`Upon heating the refractory metal, a reaction between the
`polysilicon and the cobalt or titanium may result in the
`formation of a Silicide Such as cobalt Silicide or titanium
`Silicide. In an embodiment, the width of the gate electrode
`(or channel length of the transistor) may be approximately
`0.12 microns, but may also be larger or Smaller depending
`on the transistor that is being formed.
`Many SRAMs are single wordline cells, meaning that
`there is only one local wordline arranged within each cell. It
`therefore follows that a double wordline cell has two local
`wordlines arranged within each cell. The two local word
`lines are coupled either within the cell or outside the cell.
`Frequently, Single wordline cells and double wordline cells
`have some similarities. Both cells may have wordlines that
`are polysilicon and that extend continuously from one side
`of the cell to the other. However, the embodiment of FIG. 2
`presents a split double wordline cell. That is, the local
`wordlines of the embodiment of FIG. 2 do not extend
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`continuously from one side of the memory cell to the other.
`For example, polysiliconstructures 25 and 28 each comprise
`local wordlines and each couples to global wordline 17 (not
`shown). However, neither polysiliconstructure extends con
`tinuously from one side of the memory cell to the other.
`Thus, polysilicon structures 25 and 28 are coupled together
`and to global wordline 17 outside of cell layout 20. Poly
`silicon structures 25 and 28 are coupled such that they rise
`and fall in potential together.
`The split double wordline of the embodiment of FIG. 2
`may allow the memory cell size to be reduced while also
`improving memory cell performance. Each wordline
`coupled polysilicon structure 25 and 28 may be electrically
`coupled to a polysilicon Structure arranged within an imme
`diately adjacent cell. However, an entire row of memory
`cells would not be coupled together by one or two continu
`ous polysilicon wordlines as is frequently found in SRAM
`circuits. For example, a continuous conductive wordline is
`frequently formed when the gate electrodes are formed.
`Because this type of continuous wordline is eliminated in the
`embodiment of FIG. 2, the density of the features required
`by the polysilicon layer of the memory cell is reduced.
`Consequently, the die Size required to accommodate the
`polysilicon layer may be reduced, and the layout of the
`remaining polysilicon features may be improved to provide
`a more manufacturable memory cell. Further, the perfor
`mance of the memory cell may be improved, as memory cell
`addressing times may no longer be limited by the resistivity
`of continuous polysilicon wordlines. AS noted above, Split
`local wordline polysilicon structures 25 and 28 are each
`electrically coupled to the global wordline 17. Except for
`those areas where global wordline 17 is electrically coupled
`to polysiliconstructures 25 and 28, global wordline 17 may
`be a metal dielectrically spaced from the polysilicon Struc
`tureS.
`Conductive regions and layers of the memory cell may be
`isolated from one another by dielectrics. Examples of dielec
`trics may include Silicon dioxide (SiO2), tetraethylorthosili
`cate glass (TEOS), silicon nitride (Si,N), silicon oxynitride
`(SiON,(H)), and silicon dioxide/silicon nitride/silicon
`dioxide (ONO). The dielectrics may be grown or may be
`deposited by physical deposition Such as Sputtering or by a
`variety of chemical deposition methods and chemistries Such
`as chemical vapor deposition. Additionally, the dielectrics
`may be undoped or may be doped, for example with boron,
`phosphorus, boron and phosphorus, or fluorine, to form a
`doped dielectric