UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`INTEL CORPORATION,
`Petitioner,
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`v.
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`FG SRC LLC,
`Patent Owner.
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`IPR2020-01449
`Patent No. 7,149,867
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`DECLARATION OF VOJIN G. OKLOBDZIJA, PH.D., IN
`SUPPORT OF FG SRC LLC’S PRELIMINARY RESPONSE
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`I, Dr. Vojin G. Oklobdzija, under the penalty of perjury under the laws of
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`the United States, declare that the following is true and correct based on the best of
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`my ability.
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`Date: 4 December 2020
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`Signed:
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`______________________
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`VOJIN G. OKLOBDZIJA, PH.D.
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`Patent Owner FG SRC LLC
`IPR2020-001449, Ex. 2001, p. 1
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`INTEL CORPORATION,
`Petitioner,
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`v.
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`FG SRC LLC,
`Patent Owner.
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`
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`
`IPR2020-01449
`Patent No. 7,149,867
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`
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`
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`DECLARATION OF VOJIN G. OKLOBDZIJA, PH.D., IN
`SUPPORT OF FG SRC LLC’S PRELIMINARY RESPONSE
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`
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`I, Dr. Vojin G. Oklobdzija, under the penalty of perjury under the laws of
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`the United States, declare that the following is true and correct based on the best of
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`my ability.
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`Date: 4 December 2020
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`Signed:
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`______________________
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`VOJIN G. OKLOBDZIJA, PH.D.
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`Patent Owner FG SRC LLC
`IPR2020-001449, Ex. 2001, p. 1
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`1.
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`I have been retained by DiMuro Ginsberg, P.C., as an independent
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`technical expert in the Expert in the Inter Partes Review dispute between FG SRC,
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`and Intel Corp, case, No. IPR2020-01449 which involves U.S. Patent No.
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`7,149,867 (“the ’867 Patent”).
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`2.
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`I have been paid for my work as a technical expert at my rate of $500
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`per hour. My compensation does not in any way depend on the outcome of this
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`review, and I have no personal interest in the outcome of this review.
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`I.
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`Qualifications
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`3.
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`I am an expert in the field of digital integrated circuit design. I have
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`over 45 years of relevant design experience working in the field of electrical
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`engineering: analog and digital design, processor and microprocessor design,
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`testing, optimization and performance.
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`4.
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`I hold a Master of Science (1978) and PhD (1982) in Computer
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`Sciences with minor in Electronics, from UCLA, and a Dipl. Ing. (MSEE
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`equivalent), in Electronics and Telecommunications, from the University of
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`Belgrade, Yugoslavia (1971).
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`5. My career spans 4 years at Xerox Microelectronics, 9 years at IBM T.
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`J. Watson Research Center, over 20 years in academia, and 28 years as a
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`consultant. At IBM I have been involved in two parallel computer projects: GF-
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`11, which was 560 processor parallel computer, which held a world record in 1989
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`2
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`Patent Owner FG SRC LLC
`IPR2020-001449, Ex. 2001, p. 2
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`of 11 Giga Flop peak performance, and TF-1, the first machine to achieve 1 Terra-
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`Flop peak performance, containing 32,000 processors.
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`6.
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`I have consulted extensively in the areas of microprocessor design and
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`architecture for the Silicon Valley companies such as Sun Microsystems, Bell
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`Laboratories, Texas Instruments, Hitachi, Fujitsu, Siemens, Sony, Intel, Samsung,
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`and others that are listed in my CV.
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`7.
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`I am currently a Professor Emeritus at the University of California,
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`Davis, continuing my research activities, reviewing papers, and attending
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`conferences and seminars. In academia I have taught courses in computer
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`architecture, digital design, high-performance computer architecture and specialty
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`courses in computer engineering at several prestigious universities world-wide (see
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`my CV, Attachment A.).
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`8.
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`I have been designing microprocessors for over 40 years. My current
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`work involves design and optimization of processors used in machine learning. I
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`have done extensive work on the CPU and memory architecture while working for
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`Skyera Inc, a Silicon Valley startup company.
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`9.
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`From 1991 to 2006, I was a tenured Full Professor at the University of
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`California, Davis. While there, I established a Computer Engineering (CE)
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`program in the Electrical Engineering Department, which later became the
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`Electrical and Computer Engineering Department to reflect the addition of
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`3
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`Patent Owner FG SRC LLC
`IPR2020-001449, Ex. 2001, p. 3
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`Computer Engineering. I taught all the important courses in the CE curriculum,
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`such as Digital Systems I and Digital Systems II, Computer Architecture,
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`Assembly Language and Computer Organization, Digital Integrated Circuits, and
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`graduate courses, such as Advanced Logic Design, Computer Architecture, High-
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`Performance Computer Architecture and Computer Arithmetic. During my tenure
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`at other universities, I also taught courses in Computer Architecture, VLSI Design,
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`Low-Power VLSI Circuits Design, and Digital Logic Design.
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`10.
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`I established digital design laboratory at U.C. Davis where FPGA
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`chips were used to implement student design projects. I supervised and created
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`laboratory exercises including use of FPGA. In 1995 I attended the first Workshop
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`on FPGA held at Napa Valley and I wrote a funding proposal for a project in
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`reconfigurable computing. I proposed reconfigurable computing elements which
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`will adopt to the most optimal topology as the computation requirements change.
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`11.
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`I started the Advanced Computer System Engineering Laboratory
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`(ACSEL), at the University of California, Davis in 1992. ACSEL consisted of my
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`graduate students, professors associated with the group, industrial researchers, and
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`past doctoral students. ACSEL has been working on the problems associated with
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`computer system design.
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`12. Since 1995, I have been a Fellow of IEEE (Institute of Electrical and
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`Electronics Engineers), a professional organization with over 400,000 members in
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`Patent Owner FG SRC LLC
`IPR2020-001449, Ex. 2001, p. 4
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`more than 160 countries. IEEE states: “IEEE Fellow is a distinction reserved for
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`select IEEE members whose extraordinary accomplishments in any of the IEEE
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`fields of interest are deemed fitting of this prestigious grade elevation.” No more
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`than 0.1% of the IEEE voting membership on record may be elevated to Fellow in
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`a year. Since 2015, I have been a Life Fellow of IEEE.
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`13. From 2014 to 2016, I served as President of IEEE Circuits and
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`Systems Society, one of the oldest IEEE Societies. I served for 8 years on the
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`IEEE Technical Activities Board, as Vice President for Technical Activities, and
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`Chair of Vision Committee of IEEE Circuits and Systems Society prior to 2014.
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`14. Upon my retirement as a university professor in 2012, I returned to
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`work full-time in the industry. I joined Skyera Inc. (Skyera), a startup in San Jose,
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`California, where I had the title of Senior Director, Processor Design. I managed a
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`group of engineers involved in designing a proprietary processor for Skyera Inc.
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`Skyera processor consisted of many CPUs on the chip and an efficient memory
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`architecture was very important.
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`15. When Skyera was acquired in 2014 by Hitachi, I started working as a
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`consultant for Wave Semi Inc., again on the multi CPU chip design. My work was
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`on the CPU and arithmetic elements of the processor.
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`16.
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`In December of 2015 I started working with Esperanto Technologies
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`Inc. (Esperanto Tech.), a startup company working on a “machine-learning” chip
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`Patent Owner FG SRC LLC
`IPR2020-001449, Ex. 2001, p. 5
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`which I officially joined in June 2016. During my work at Esperanto Tech.,
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`Personally worked on CPU and memory design.
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`17.
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`In April of 2018 I switched jobs and joined SambaNova Systems Inc.
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`(SNS Inc.), a Palo Alto based startup that is one of the three leading companies in
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`machine learning. I have been working on the CPU design for a chip containing
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`tens of thousands of processors. I designed specialized CPU tailored for machine
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`learning.
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`18. My qualifications for forming the opinions set forth in this report are
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`listed in this section and in my curriculum vitae, which is attached hereto as
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`Exhibit A. Exhibit A also includes a list of my publications, identifies each person
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`or entity from whom I have received compensation or funding for work in my area
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`of expertise or to whom I have provided professional services, including a list of
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`all other cases in which I have testified during at least the previous five years.
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`19.
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`I base my opinions below on my professional training and experience
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`and my review of documents and materials produced in this review.
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`II. Bases Of Opinions
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`20. The basis and reasoning of my opinions include my education,
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`training, and experience as an engineer, including my 45 years of experience
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`designing microprocessors. In the course of conducting my analysis and forming
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`my opinions, I have considered the materials listed below:
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`6
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`Patent Owner FG SRC LLC
`IPR2020-001449, Ex. 2001, p. 6
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`a. U.S. Patent No. 7,149,867 to Daniel Poznanovic, et al., filed June16,
`2004, and issued on December12, 2006 (“’867 patent”) and its file
`history;
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`b. X. Zhang et al., Architectural Adaptation of Application-Specific
`Locality Optimizations, IEEE (1997) (“Zhang”);
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`c. R. Gupta, Architectural Adaptation in AMRM Machines, IEEE (2000)
`(“Gupta”);
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`d. A. Chien and R. Gupta, MORPH: A System Architecture for Robust
`Higher Performance Using Customization,” IEEE (1996)(“Chien”);
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`e. Chien et al., Safe and Protected Execution for the Morph/AMRM
`Reconfigurable Processor, IEEE (1999);
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`f. Declaration of Stanley Shanfield, Ph.D.;
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`g. Declaration of Rajesh K. Gupta;
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`h. Declaration of J. Munford;
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`i. Provision Application No. 60-479,339;
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`j. 2020-08-10 Intel's Petition for IPR Review of U.S. Patent No.
`7,149,867;
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`k. U.S. Patent 8,713,518;
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`l. Book: John L. Hennessy and David A. Patterson, “Computer
`Architecture: A Quantitative Approach” (The Morgan Kaufmann Series
`in Computer Architecture and Design); and
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`m. Book: David Culler, “Parallel Computer Architecture: A
`Hardware/Software Approach” (The Morgan Kaufmann Series in
`Computer Architecture and Design);
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`n. Intel’s IPR petition in this matter and its exhibits;
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`o. Declaration Of Ryan Kastner, Ph.D. In Support Of FG SRC LLC’s
`Opening Claim Construction Brief in FG SRC LLC v. Intel Corp., No.
`6:20-cv-00315-ADA (W.D. Texas), filed April 24, 2020;
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`p. and any other materials referenced herein.
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`7
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`Patent Owner FG SRC LLC
`IPR2020-001449, Ex. 2001, p. 7
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`21. My opinions in this declaration are based on the understanding of a
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`person of ordinary skill in the art at the time of the invention of the claims in
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`the’867 Patent.
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`22.
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`In assessing the level of skill of a person of ordinary skill in the art, I
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`have considered the type of problems encountered in the art, the prior solutions to
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`those problems found in the prior art references, the rapidity with which
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`innovations are made, the sophistication of the technology, the level of education
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`of active workers in the field, and my own experience working with those of skill
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`in the art at the time of the invention.
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`23. A person of ordinary skill in the art (“POSITA”) at the time of the
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`filing of the ’867 patent would typically have at least an MS Degree in Computer
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`Engineering, Computer Science, or Electrical Engineering, or equivalent work
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`experience, along with at least three years of experience related specifically to
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`computer architecture, hardware design, and reconfigurable processors. In
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`addition, a POSITA would be familiar with hardware description languages and
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`design tools and methodologies used to program a reconfigurable processor.
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`24.
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`I am very familiar with this level of skill. In the course of my 45
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`years of processor design and research, I have supervised and worked with
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`engineers in this field having the level of skill identified above.
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`Patent Owner FG SRC LLC
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`25.
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`I understand that the words of a claim are generally given their
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`ordinary and customary meaning, that is, the meaning that the term would have to
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`a person of ordinary skill in the art in question at the time of the invention
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`26.
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`I understand that a claim term that does not use the word “means” is
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`presumed not to be a means-plus-function term. I understand that a term that does
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`not use the word “means” would be construed as a means-plus-function term if it
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`does not describe structure to a POSITA. Conversely, I understand that if a term
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`describes structure to a POSITA, itis not a means-plus-function term.
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`III. Legal Framework
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`27. A patent has several components, including an abstract, drawings, a
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`written description detailing different embodiments of the invention (i.e., the
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`specification), and numbered claims at the end of the patent. It is the numbered
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`claims that define metes and bounds of the properties that the patentee has the right
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`to exclude other from infringing.
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`28. A patent, once issued or granted, is entitled to a presumption of
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`validity. See Pfizer, Inc. v. Apotex, Inc., 480 F.3d 1348, 1359-60 (Fed. Cir. 2007).
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`However, this presumption can be overcome by clear and convincing evidence to
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`the contrary. Id. Validity is routinely challenged post-issuance, and courts often
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`invalidate the patent, on the ground that the patent fails to meet one or more
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`statutory requirements, e.g., by claiming a non-patentable subject matter, such as
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`an abstract idea, in violation of 35 U.S.C. § 101; by being not novel and anticipated
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`by prior art under § 102; by being obvious in view of prior art under § 103; and/or
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`lacking sufficient disclosures or being indefinite, in violation of § 112.
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`29. Section 102 first defines “prior art” that would anticipate and, thus,
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`invalidate the patent. The term “prior art” is a patent term of art for the technology
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`that was known or used before the filing of the patent. For example, if the subject
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`matter of the invention was already patented or described in a printed publication
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`anywhere in the world before the invention claimed in the patent, such prior art
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`would invalidate the patent. 35 U.S.C. § 102(a) (pre-AIA).
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`30. Section 103 is broader than § 102 in a sense that § 103 forbids
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`issuance of a patent even if “the invention is not identically disclosed or described
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`as set forth in section 102, if the differences between the subject matter sought to
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`be patented and the prior art are such that the subject matter as a whole would have
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`been obvious at the time the invention was made to a person having ordinary skill
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`in the art to which said subject matter pertains.” 35 U.S.C. § 103(a) (pre-AIA).
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`31. Measuring the obviousness under § 103, a court determines “the scope
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`and content of the prior art,” ascertains “differences between the prior art and the
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`claims at issue,” and resolves “the level of ordinary skill in the pertinent art.”
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`Graham v. John Deere Co., 383 U.S. 1, 17 (1966). Secondary considerations such
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`as “commercial success, long felt but unsolved needs, failure of others . . . might
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`be utilized to give light to the circumstances surrounding the origin of the subject
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`matter sought to be patented.” Id. at 17-18; see KSR Int’l Co. v. Teleflex Inc., 550
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`U.S. 398, 415 (2007) (“Graham set forth a broad inquiry and invited courts, where
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`appropriate, to look at any secondary considerations that would prove
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`instructive.”).
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`32.
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`It is my understanding that the information that is used to evaluate
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`whether an invention is new and not obvious is generally referred to as “prior art.”
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`Prior art generally includes U.S. and foreign patents and U.S. and foreign printed
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`publications (e.g., published patent applications (before issued as a patent), books,
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`journal publications, presentation files, posters, articles on websites, product
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`manuals, etc.) that existed before the earliest filing date (the “effective filing date”)
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`of the claims in the patent. A patent will be prior art if it was filed before the
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`effective filing date of the claimed invention, while a printed publication will be
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`prior art if it was publicly available before that date.
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`33.
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`In addition to the patents and printed publications, a product used in
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`public or on sale in the U.S. more than one year prior to the effective filing date of
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`a patent can be prior art to that patent. I understand that a product is considered
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`“on sale” when (i) the product embodying the invention is offered for commercial
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`sale, and (ii) the invention was ready for patenting. An invention is shown to be
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`“ready for patenting” when there is proof of a reduction to practice or proof that
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`prior to the critical date the inventor had prepared drawings or other descriptions of
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`the invention that were sufficiently specific to enable a person skilled in the art to
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`practice the invention.
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`34.
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`It is my understanding that a claimed invention is not patentable if it
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`would have been obvious to a person of ordinary skill in the field of the invention
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`at the time the invention was made.
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`35.
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`It is my understanding that the following standards govern the
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`determination of whether a claim in a patent is obvious. I have applied these
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`standards in my evaluation of whether the claims of the ’933 and ‘976 Patents that
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`were asserted in the E.D. Tex. Litigation would have been considered obvious in
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`light of the prior art.
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`36.
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`It is my understanding that to find a claim in a patent obvious, one
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`must make certain findings regarding the claimed invention and the prior art.
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`Specifically, the obviousness question requires consideration of four factors
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`(although not necessarily in the following order):
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`the scope and content of the prior art;
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`the differences between the prior art and the claims at issue;
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`the knowledge of a person of ordinary skill in the pertinent art; and
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` whatever objective factors indicating obviousness or non-obviousness may
`be present in any particular case.
`37.
`It is my understanding that the obviousness inquiry should not be
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`done in hindsight, but must be done using the perspective of a person of ordinary
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`skill in the relevant art as of the effective filing date of the patent claim. The
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`prohibition against using hindsight applies to both the invention and the
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`identification of the problem that the invention solves.
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`38.
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`It is my understanding that the obviousness inquiry may also consider
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`certain objective indicia of non-obviousness. Such objective factors indicating
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`obviousness or non-obviousness may include: commercial success of products
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`covered by the patent claims; a long-felt need for the invention; failed attempts by
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`others to make the invention; copying of the invention by others in the field;
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`unexpected results achieved by the invention; praise of the invention by the
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`infringer or others in the field; the taking of licenses under the patent by others;
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`expressions of surprise by experts and those skilled in the art at the making of the
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`invention; and the patentee proceeded contrary to the accepted wisdom of the prior
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`art.
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`39.
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`It is my understanding that the fact finder must determine whether
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`potential evidence of secondary considerations is relevant. With respect to
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`evidence offered for each secondary consideration, the fact finders must ascertain
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`whether there is a nexus between the claimed invention and the evidence
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`establishing the secondary consideration (commercial success, industry praise, etc.)
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`and determine the probative value of secondary-considerations evidence for
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`rebutting a prima facie case of obviousness.
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`40.
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`I understand that the obviousness analysis requires a comparison of
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`the properly construed claim language to the prior art on a limitation-by-limitation
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`basis. The Supreme Court in KSR elaborated upon the framework for analyzing
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`obviousness it had set forth in previous cases. See 550 U.S. 398. KSR rejected the
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`Federal Circuit’s rigid application of the teaching, suggestion, or motivation test
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`for obviousness in favor of an expansive and flexible approach using common
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`sense. See id. at 415-22. KSR specifically cautioned against granting patents that
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`claim nothing more than combinations of known elements driven by non-
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`innovative factors such as market demands. Id. at 415-19. The Court there also
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`stressed the need for caution before upholding the validity of patents that are
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`merely combinations of elements found in the prior art. Id. The Court has
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`observed that, if a person of ordinary skill in the art can implement the claimed
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`invention as a predictable variation of a known invention, it is obvious. Id. Also,
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`“hindsight” reconstruction cannot be used to combine references together to reach
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`a conclusion of obviousness. Id. at 421.
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`41.
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`It is my understanding that exemplary rationales that may support a
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`conclusion of obviousness include:
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` combining prior art elements according to known methods to yield
`predictable results;
` simple substitution of one known element for another to obtain predictable
`results;
` use of known techniques to improve similar devices (methods or products)
`in the same way;
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` applying a known technique to a known device (method or product) ready
`for improvement to yield predictable results;
` “obvious to try,” i.e., choosing from a finite number of identified,
`predictable solutions with a reasonable expectation of success;
` known work in one field of endeavor may prompt variations of it for use in
`either the same field or a different one based on design incentives or other
`market forces if the variations would have been predictable to one of
`ordinary skill in the art; and
` some teaching, suggestion, or motivation in the prior art that would have led
`one of ordinary skill to modify the prior art reference or to combine prior art
`reference teachings to arrive at the claimed invention.
`42. Thus, when considering a prior art reference for purposes of an
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`obviousness analysis, the reference must be taken for everything it teaches.
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`43.
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`I understand that a claim might be obvious in light of a single
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`reference, without the need to combine references, if the elements of the claim that
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`are not found explicitly or inherently in the reference can be supplied by the
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`knowledge of one skilled in the art, including the common sense of one of skill in
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`the art.
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`44. An obviousness evaluation can also be based on a combination of
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`multiple prior art references. The prior art references themselves may provide a
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`suggestion, motivation, or reason to combine, but other times the nexus linking two
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`or more prior art references is simple common sense. I further understand that an
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`obviousness analysis recognizes that market demand, rather than scientific
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`literature, often drives innovation, and that a motivation to combine references may
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`be supplied by the direction of the marketplace.
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`45.
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`I understand that practical and common-sense considerations should
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`guide a proper obviousness analysis, because familiar items may have obvious uses
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`beyond their primary purposes. A person of ordinary skill in the art looking to
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`overcome a problem will often be able to fit the teachings of multiple publications
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`together like pieces of a puzzle. An obviousness analysis, therefore, takes into
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`account the inferences and creative steps that a person of ordinary skill in the art
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`would employ under the circumstances.
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`46.
`
`I understand that a particular combination may be proven obvious
`
`merely by showing that it was obvious to try the combination. For example, when
`
`there is a design need or market pressure to solve a problem and there are a finite
`
`number of identified, predictable solutions, a person of ordinary skill has good
`
`reason to pursue the known options within his or her technical grasp because the
`
`result is likely the product not of innovation but of ordinary skill and common
`
`sense which led to a reasonable expectation of success.
`
`47.
`
`It is my understanding that the combination of familiar elements
`
`according to known methods is likely to be obvious when it does no more than
`
`yield predictable results. When a work is available in one field of endeavor, design
`
`incentives and other market forces can prompt variations of it, either in the same
`
`field or a different one.
`
`
`
`16
`
`Patent Owner FG SRC LLC
`IPR2020-001449, Ex. 2001, p. 16
`
`
`
`
`
`
`
`48.
`
`I understand that when a patent simply arranges old elements with
`
`each performing the same function it had been known to perform and yields no
`
`more than one of ordinary skill in the art would reasonably expect from such an
`
`arrangement, the combination is obvious. A proper obviousness analysis focuses
`
`on what was known or obvious to a person of ordinary skill in the art, not just the
`
`patentee. Accordingly, any need or problem known in the field of endeavor at the
`
`time of invention and addressed by the patent can provide a reason for combining
`
`the elements in the manner claimed.
`
`49.
`
`In sum, it is my understanding that prior art teachings are properly
`
`combined where a person of ordinary skill in the art, having the understanding and
`
`knowledge reflected in the prior art and motivated by the general problem facing
`
`the inventor, would have been led to make the combination of elements recited in
`
`the claims. Under this analysis, the prior art references, or any need or problem
`
`known in the relevant field at the time of the invention, can provide a reason for
`
`combining the elements of multiple prior art references in the claimed manner.
`
`But, as stated previously, I understand that “hindsight” reconstruction cannot be
`
`used to combine references together to reach a conclusion of obviousness.
`
`50.
`
`It is my understanding that the “basic rule of patent misuse [is] that
`
`the patentee may exploit his patent but may not ‘use it to acquire a monopoly not
`
`embraced in the patent.’” Princo Corp. v. Int’l Trade Comm’n, 616 F.3d 1318,
`
`
`
`17
`
`Patent Owner FG SRC LLC
`IPR2020-001449, Ex. 2001, p. 17
`
`
`
`
`
`
`
`1327 (Fed. Cir. 2010). Thus, I understand that patent misuse occurs when “the
`
`patentee has impermissibly broadened the ‘physical or temporal scope’ of the
`
`patent grant with anticompetitive effect.” Windsurfing Int’l Inc. v. AMF, Inc., 782
`
`F.2d 995, 1001 (Fed. Cir. 1986). The Supreme Court explained that “[t]here is
`
`nothing in the right granted the patentee to keep others from using, selling, or
`
`manufacturing his invention which empowers him to insist on payment not only
`
`for use but also for producing products which do not employ his discoveries at all.”
`
`Zenith Radio Corp. v. Hazeltine Research, Inc., 395 U.S. 100, 139 (1969).
`
`IV. Conventional Computer Architecture
`
`51. Conventional computers utilize general purpose processors /
`
`microprocessors employing a Von Neumann architecture. In a conventional
`
`computer, hardware is fixed and cannot be changed after manufacturing. To
`
`execute a software program, the processor goes through a fixed routine of steps
`
`called the fetch-execute cycle consisting of instruction fetch, instruction decode,
`
`instruction execution, data memory access, and data write back.
`
`52. Since 1965, the speed of processors has risen exponentially, which
`
`predicted that the number of transistors on processors would double nearly every
`
`24 months (Moore’s law). Moore’s law held true until the early 2000s, when
`
`microprocessor manufacturers were no longer able to dramatically increase
`
`processor performance by increasing transistor density. Focus shifted to multicore
`
`
`
`18
`
`Patent Owner FG SRC LLC
`IPR2020-001449, Ex. 2001, p. 18
`
`
`
`
`
`
`
`chips to continue improving processor performance. This has resulted in
`
`microprocessors with much higher power consumption, which has made electricity
`
`a considerable operating expense for large computing centers.
`
`53. At the time of the ’867 patent, there was considerable pressure in the
`
`industry for computing systems with drastically higher performance, lower
`
`operating expense, lower power usage, and lower space requirements. The
`
`inventions of the ’867 patent very drastically improved all of these areas. It is my
`
`understanding that addressing a long-felt industry need is an important indication
`
`of non-obviousness which must be considered in any obviousness analysis.
`
`54. The ’867 patent relates to the use of reconfigurable processors such as
`
`FPGAs. Ex. 1001, 1:16-24, 5:26-29. An FPGA is a reprogrammable integrated
`
`circuit that contains an array of programmable logic blocks and memory elements
`
`connected via programmable interconnect. FPGA are programmable to perform
`
`specific functions. Programming an FPGA creates a hardware accelerated
`
`implementation of a particular algorithm that efficiently executes the algorithm.
`
`Hardware is thus able to adapt to the requirements of the software. A binary file
`
`called bitstream is used to configure an FPGA. Reconfigurable processors like
`
`FPGA’s thus do not use software “instructions” like a conventional CPU.
`
`55. Conventional CPUs, on the other hand, execute an algorithm by
`
`performing a sequence of software instructions. This allows great flexibility in a
`
`
`
`19
`
`Patent Owner FG SRC LLC
`IPR2020-001449, Ex. 2001, p. 19
`
`
`
`
`
`
`
`conventional CPU; it can implement any software. But it is unable to be
`
`customized towards the any particular algorithm, because the hardware is fixed.
`
`Therefore, while a conventional CPU is more versatile, FPGAs are much more
`
`efficient at the particular algorithm for which their hardware is configured.
`
`56. A simple memory requests data when it is required for computation.
`
`Prefetching, in contrast, requests data before it is required, so that it is available
`
`when needed. To perform this task, the prefetch unit must be configured to know
`
`what data to retrieve, and when.
`
`V. The Prior Art
`
`57. Dr. Shanfield testifies that “unlike general-purpose processors, which
`
`have fixed hardware, FPGA processors have user-programmable functional units
`
`and interconnections that are customizable for whatever particular software
`
`application is to be run on the processor. See EX1001, 6:5-19. Thus, instead of
`
`adapting a program’s instructions to match the requirements of the computer
`
`hardware resources as in a conventional general-purpose processor, the hardware
`
`resources of an FPGA (or related programmable logic technology) are
`
`essentially adapted to conform to the program (and specifically, to perform the
`
`algorithms in the program using reconfigurable hardware logic circuits).” Ex.
`
`1006, ¶ 73 (emphasis added).
`
`
`
`20
`
`Patent Owner FG SRC LLC
`IPR2020-001449, Ex. 2001, p. 20
`
`
`
`
`
`
`
`58. Thus, according to Dr. Shanfield, a FPGA does not have program
`
`instructions, and instead is adapted to conform to the program. This disqualifies
`
`Zhang, Chien, and Gupta, as they are all dealing with a fixed hardware CPU which
`
`runs under the program instructions, according to Dr. Shanfield’s own declaration.
`
`Dr. Shanfield further opines that “some of the names given to computer processors
`
`that are implemented in FPGA include “FPGA processors,” “reconfigurable
`
`processors,” “soft processors,” and “soft processor cores.” Id. This matches the
`
`terminology used in the ’867 patent. In contrast, Zhang, Chien, and Gupta are
`
`referring to a “fixed function hard wired CPU or processor” operating under the
`
`program’s instructions, i.e., conventional CPUs.
`
`59. Dr. Shanfield recognizes that the ’867 patent includes a reconfigurable
`
`processor:
`
`The ’867 patent seeks to accomplish this by employing a ‘data
`prefetch unit’ to prefetch from memory ‘only data required for
`computation … within
`the memory hierarchy’ of the
`reconfigurable processor before the data is needed for
`processing. Id., 7:23-8:41. Logic block 300 is ‘a simple logic
`block’ that may include computational functional units 301,
`control functional units (not shown), and data access units 302,
`303 and 403. Id., 7:25-28. Logic block 300 can read and write
`data stored on ‘memory device 305 or block RAM memory
`307’ of the reconfigurable processor. Id., 7:28-32. Also
`attached to the reconfigurable processor is the external
`memory at the top of Figure 5.”
`
`Ex. 1006, ¶ 79 (emphasis added). This differentiates the ’867 patent substantially
`
`from the asserted prior art in Chien, Zhang, and Gupta.
`
`
`
`21
`
`Patent Owner FG SRC LLC
`IPR2020-001449, Ex. 2001, p. 21
`
`
`
`
`
`
`
`60. The very same argument was cited as a reason for Allowance issued
`
`on July
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