Paper No. 12
`January 13, 2021
`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`INTEL CORPORATION,
`Petitioner,
`v.
`FG SRC LLC,
`Patent Owner.
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`
`IPR2020-01449
`Patent No. 7,149,867
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`PATENT OWNER’S SUR-REPLY TO
`PETITIONER’S REPLY TO PRELIMINARY RESPONSE
`
`
`January 13, 2021
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`
`
`INTEL CORPORATION,
`Petitioner,
`v.
`FG SRC LLC,
`Patent Owner.
`
`
`
`
`
`
`
`IPR2020-01449
`Patent No. 7,149,867
`
`
`
`
`
`
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`
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`
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`PATENT OWNER’S SUR-REPLY TO
`PETITIONER’S REPLY TO PRELIMINARY RESPONSE
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`
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`LIST OF EXHIBITS
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`2004
`
`2005
`
`2006
`
`2007
`2008
`
`Exhibit No. Descriptions
`Declaration of Dr. Vojin Oklobdzija
`2001
`Cray, Britannica Online Encyclopedia
`2002
`Declaration of Brandon Freeman dated 10/25/18
`2003
`SRC Labs LLC and Saint Regis Mohawk Tribe v. Microsoft
`Corporation, No. 2:18-cv-00321-JLR, Dkt. 125 (W.D. Wash. Oct.
`25, 2018)
`Plaintiff’s Original Complaint For Patent Infringement in FG SRC
`LLC v. Intel Corp., No. 6:20-cv-00315-ADA (W.D. Texas), filed
`April 24, 2020
`Plaintiff’s First Amended Complaint For Patent Infringement in
`FG SRC LLC v. Intel Corp., No. 6:20-cv-00315-ADA (W.D.
`Texas), filed April 24, 2020
`Declaration of Mark Wollgast dated 09/10/18
`Xilinx, Inc. v. Saint Regis Mohawk Tribe, IPR2018-0195
`COTS Journal, UAVs Lead Push for Embedded Supercomputing
`Press Release: SRC Computers Chosen by Lockheed Martin for
`U.S. Army Program
`Declaration of Henning Schmidt
`Declaration of Henning Schmidt, Exhibit A, IEEE Xplore:
`Advanced Search
`Declaration of Henning Schmidt, Exhibit B, IEEE Xplore:
`Advanced Search Results
`Declaration Of Ryan Kastner, Ph.D. In Support Of FG SRC
`LLC’s Opening Claim Construction Brief in FG SRC LLC v. Intel
`Corp., No. 6:20-cv-00315-ADA (W.D. Texas), filed April 24,
`2020
`Peter McMahon, High Performance Reconfigurable Computing for
`Science and Engineering Applications (Thesis Oct. 2006).
`Caliga, Delivering Acceleration: The Potential for Increased HPC
`Application Performance Using Reconfigurable Logic
`D. A. Buell, D. Caliga, J. P. Davis, G. Quan, “The DARPA
`boolean equation benchmark on a reconfigurable computer,”
`Proceedings of the Military and Aerospace Programmable Logic
`Devices (MAPLD) Conference, Washington, DC, 8-10 September
`
`2009
`2009-1
`
`2009-2
`
`2010
`
`2011
`
`2012
`
`2013
`
`
`
`i
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`
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`Exhibit No. Descriptions
`2004
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`2014
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`2015
`
`2016
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`2017
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`2018
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`2019
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`2020
`
`2021
`
`2022
`2023
`
`2024
`
`2025
`
`2026
`
`El-Araby, The Promise of High-Performance Reconfigurable
`Computing
`FG SRC LLC’s Opening Claim Construction Brief in FG SRC
`LLC v. Intel Corp., No. 6:20-cv-00315-ADA (W.D. Texas),
`filed April 24, 2020
`Kerr Machine Co. d/b/a Kerr Pumps v. Vulcan Industrial
`Holdings, LLC, No. 6:20-cv-00200, Text Order dated Aug. 2, 2020
`(W.D. Tex.)
`MultiMedia Content Mgmt LLC v. Dish Network L.L.C., No. 6:18-
`cv-00207, Dkt. 73 (W.D. Tex.)
`Solas OLED v. Dell Techs. Inc., No. 6:19-cv-00514, Text Order
`dated June 23, 2020
`Kerr Machine Co. v. Vulcan Indus. Holdings, LLC, No. 6:20-cv-
`200, Dkt. 28 (W.D. Tex. July 31, 2020)
`Kerr Machine Co. v. Vulcan Indus. Holdings, LLC, No. 6:20-cv-
`200, Dkt. 24 (W.D. Tex. June 14, 2020)
`Kerr Machine Co. v. Vulcan Indus. Holdings, LLC, No. 6:20-cv-
`200, Dkt. 12 (W.D. Tex., June 14, 2020)
`Email from J. Yi to Counsel (Aug. 3, 2020)
`FG SRC LLC v. Intel Corp., No. 1:20-cv-00834, Dkt. 48 (W.D.
`Tex. Nov. 23, 2020) (Amended Schedule)
`Continental Intermodal Group - Trucking LLC v. Sand Revolution
`LLC, No. 7:18-cv-00147, Text Order dated July 22, 2020 (W.D.
`Tex.)
`Solas OLED v. Dell Techs. Inc., No. 6:19-cv-00515, Text Order
`dated Jun. 23, 2020
`2019-07-11 - DirectStream MSFT - Huppenthal Declaration
`
`ii
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`
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`I.
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`INSTITUTION SHOULD BE DENIED UNDER FINTIV
`Fintiv Factor 1 strongly favors denial because Petitioner’s unsupported
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`speculation that the Court might grant a post-institution stay (Paper 11, 1) is
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`contradicted by Patent Owner’s direct evidence that a stay is highly unlikely. Paper
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`9, 3-4. Regarding Factors 2-3, trial is set for November 8, 2021, and “the Court will
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`not move the trial date except in extreme situations.” Order Governing Proceedings
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`for Patent Cases (v3.2), available at https://tinyurl.com/y4nxokvz. Even assuming
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`the “extreme situation” of a continuance of the trial date (commensurate with the
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`one-month Markman extension), the related litigation will go to trial in December
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`2021, two months before a final written decision. This schedule strongly favors
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`denying institution. Philip Morris Prod., S.A. v. RAI Strategic Holdings, Inc.,
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`IPR2020-00921, Paper 9, at 14-15 (PTAB Nov. 16, 2020). Petitioner’s Reply does
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`not address the remaining Factors, which also favor denial.
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`Given the specific factual circumstances here, an IPR would not be an
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`“expeditious, efficient, and less expensive alternative to district court litigation,” as
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`these proceedings would be needlessly duplicative of the district court action.
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`II. THE PRINTED PUBLICATION STANDARD HAS NOT BEEN MET
`Petitioner’s Reply merely reinforces that Dr. Gupta only “believes” Zhang,
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`Gupta, and Chien may have been disseminated based on an undefined “general
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`practice in the scientific and engineering community.” This contrasts sharply with
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`1
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`cases in which the declarant unequivocally testified as to the specific practices of the
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`specific organization, including that he actually received a copy of the asserted
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`publication. Laboratory Corp. of America Holdings v. Quest Diagnostics, IPR2019-
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`00738, Paper 14 at 13 (PTAB Sept. 4, 2019); IPR2019-00738, Ex. 1002, ¶34.
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`As to online publication, typical direct evidence of publication is not present
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`here. See Hulu, LLC v. Sound View Innovations, LLC, IPR2018-01039, Paper 39 at
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`18 (PTAB POP Dec. 20, 2019) (online publication supported by “office manager of
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`the Internet Archive”). An online search for the asserted publication is probative
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`evidence if it includes terms that appear in the challenged patent’s specification. In
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`re Lister, 583 F.3d 1307, 1315 (Fed. Cir. 2009). Patent Owner demonstrated that
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`such an online search here is fruitless. Paper 9, 30-31. Under Lister and its progeny,
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`Petitioner’s online publication theory therefore fails. See Acceleration Bay, LLC v.
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`Activision Blizzard, Inc., 908 F.3d 765, 774 (Fed. Cir. 2018).
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`Mr. Munford’s testimony likewise falls short. In Quest, the petitioner
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`submitted a declaration containing specific information about the particular library
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`and unequivocal testimony that a copy of the reference was actually received.
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`IPR2019-00738 at 12-15. No such evidence is presented here. Petitioner’s assertion
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`that shelving of a reference is unimportant (Paper 11, 4) is wrong: “[P]articularly for
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`manuscripts or dissertations stored in libraries, courts may inquire whether a
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`reference was sufficiently indexed, catalogued, and shelved.” Hulu, IPR2018-01239
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`2
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`at 9. Petitioner’s other authority does not relate to references stored in a library at
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`all. Medtronic, Inc. v. Barry, 891 F.3d 1368, 1380-81 (Fed. Cir. 2018).
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`III. PETITIONER MISCHARACTERIZES THE “RECONFIGURABLE
`PROCESSOR”
`Petitioner mischaracterizes the agreed construction of “reconfigurable
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`processor” by omitting key language that contradicts its position. Paper 11, 4. The
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`complete and correct construction is “a computing device
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`that contains
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`reconfigurable components such as FPGAs and can, through reconfiguration,
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`instantiate an algorithm as hardware.” Conventional processors cannot instantiate an
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`algorithm as hardware. Ex. 2001, ¶51 (“conventional computers utilize general
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`purpose processors [whose] hardware is fixed.”); Id., ¶77 (Zhang “relies on a
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`conventional processor, and does not disclose or even consider the use of
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`reconfigurable processors as that term is used in the ’867 Patent. For that reason,
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`Zhang’s application remains in software.”).
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`Petitioner’s argument that a conventional processor can be a reconfigurable
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`processor simply by utilizing the “small blocks of programmable logic implemented
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`into key elements of a baseline architecture” to enable “the customization of
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`architectural mechanisms and policies to match an application” is wrong for multiple
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`reasons. First, Petitioner’s interpretation is indefinite because it is unclear how much
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`reconfigurable
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`logic
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`is needed
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`to convert a conventional processor
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`to
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`“reconfigurable processor.”
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`3
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`Second, the ’867 Patent itself defines “reconfigurable processor” as: (1) a
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`computing device that “contains reconfigurable components such as FPGAs,” and
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`(2) a computing device that “can, through reconfiguration, instantiate an algorithm
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`as hardware.” Even if a conventional processor utilized some reconfigurable
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`components, it would not meet the second criteria because it is the computing
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`device—i.e., the processor—that must instantiate an algorithm as hardware, which
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`a conventional processor cannot do.
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`Third, the specification of the ’867 Patent leaves no doubt that its
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`“reconfigurable processor” must comprise a computational unit (i.e., computing
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`device or processor) that is indeed reconfigurable, in addition to other reconfigurable
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`components, such as a memory hierarchy: “A reconfigurable processor (RP) 100
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`implements direct executable logic (DEL) to perform computation, as well [as] a
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`memory hierarchy.” Ex. 1001, 5:59-61; see also id., Abstract; id., 6:15-16 (“The
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`reconfigurable processor 100 also implements user-defined computational logic . . .
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`constructed by programming an FPGA to implement a particular interconnection of
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`computational functional units.”); id., Figs. 1 and 2; id., 4:2-3 (“the computational
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`unit [is] configured by a program”); id., 4:24-26 (same).
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`Fourth, the ’867 Patent explicitly contrasts the prior art (conventional
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`microprocessor) with the invention (reconfigurable computational unit):
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`In the common case in which static computing hardware resources are
`used (e.g., a conventional microprocessor), the computer program is
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`4
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`compiled into . . . [executable code that] is generated specifically for a
`particular hardware platform. In this manner, the computer program is
`adapted to conform to the limitations of the static hardware platform.
`However, the compilation process makes many compromises based on
`the limitations of the static hardware platform. … Alternatively, an
`algorithm can be defined in a high-level language then compiled into
`DEL. . . . Computation is performed by reconfiguring a reconfigurable
`processor with the DEL and flowing data through the computation.
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`Ex. 1001, 6:32-46 (emphasis added). Nowhere does the ’867 Patent or Petitioner’s
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`expert indicate that the computational unit of its RP may be a conventional
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`processor. In fact, “the ’867 Patent teaches the use of reconfigurable processors in
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`lieu of
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`conventional microprocessors
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`/ CPUs,”
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`i.e.,
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`“[conventional]
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`microprocessors/CPUs are
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`replaced with application
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`specific
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`functional
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`units/computational elements implemented in reconfigurable logic.” Ex. 2001, ¶66
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`(emphasis added); id., at ¶133. Petitioner’s interpretation is explicitly contradicted
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`by the patent itself as well as the only expert testimony on record.
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`Zhang, by contrast, explicitly teaches away from “the use of reconfigurable
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`logic for application-specific functional units or computational logic.” Ex. 2001, ¶66
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`(emphasis added). Zhang explicitly uses a conventional processor, and “envisions
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`only small hardware adaptations in processor functional units (perhaps in the
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`peripheral components).”
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`Id., ¶65. Petitioner’s argument
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`that Zhang’s
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`“computational algorithms, including Zhang’s matrix multiplication algorithms, . . .
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`are implemented in reconfigurable processing elements” (Paper 11, 5) is
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`demonstrably false. Only the prefetching for the multiplication algorithm is
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`5
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`implemented in reconfigurable processing elements; the actual matrix multiplication
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`runs on the host microprocessor. Ex. 2001, ¶79. Petitioner’s citations (Paper 11, 5)
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`lend no support. See Paper 1, 42-43 (concerning only prefetch algorithm, not matrix
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`multiplication; id., 64 (discussing only “computational unit” that runs on
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`conventional CPU shown in Zhang Fig. 2); id., 67-68 (matrix multiplication not
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`addressed at all).
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`Petitioner’s new file history argument (Paper 11 at 4) is waived because it is
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`a new argument in a Reply. CTPG at 14. Regardless, the Examiner noted that Paulraj
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`shows reconfigurable logic “within” its CPU. Ex. 1002-105. Zhang does not.
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`Paulraj, Fig. 6
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`Zhang, Ex. 1003, Fig. 2
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`Notably, Paulraj was unsuccessfully asserted as prior art to the ’867 Patent in SRC
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`Labs, LLC et al., v. Amazon Web Services, Inc., et al., No. 2:18-cv-00317 (W.D.
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`Washington), filed Feb. 26, 2018.
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`Petitioner’s remaining arguments are contrary to the evidence: the claim
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`language explicitly requires that “first memory and data prefetch unit are configured
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`to conform to needs of the algorithm” (Ex. 1001, 12:51-52); the characterization of
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`6
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`Zhang (Paper 11, 6-7) is wrong because either the application remains in software
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`and is executed on general purpose hardware, or it is used to render special purpose
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`hardware, and Petitioner’s argument completely eliminates the difference between
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`static and reconfigurable computing. Patent Owner’s positions (Paper 11, 7) are
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`based on Zhang itself (Ex. 1003, Table 1) and expert testimony (Ex. 2001, ¶106(c)
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`(“Zhang only discloses L1 and L2 cache line sizes of 32 or 64 bytes versus the matrix
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`element size of 40 bytes.”); see also id., ¶¶92, 95, and 130).
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`IV. PATENT OWNER HAS DEMONSTRATED A NEXUS
`The nexus between the success of Patent Owner’s MAP supercomputer and
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`the ’867 Patent is directly established by the evidence. The ability to automatically
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`instantiate algorithms resulted in improved processing capacity, such as giving “the
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`MAP the ability to get data from a variety of memories, having different data widths,
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`and reformat that data into the width of the function that is consuming it before it
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`needs to consume it.” Ex. 2026, ¶73. The invention is thus directly responsible for
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`performance improvements including, for example, processing speed gains because
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`“a new data value can be input into the function unit every clock [cycle].” Ex. 2012,
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`8. These advantages directly translated
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`into commercial success: “These
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`performance, size and power consumption improvements continue to demonstrate
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`SRC/DirectStream’s leading edge capabilities that Lockheed Martin’s own
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`procurement process showed no other vendor could match.” Ex. 2006, ¶¶20, 21.
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`7
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`Respectfully submitted,
`
`
`/s/ Jay P. Kesan
`
`DiMuroGinsberg, PC-
`DGKeyIP Group
`Jay P. Kesan
`Reg. No. 37,488
`Cecil E. Key (admission pro hac vice
`pending)
`1750 Tysons Blvd., Suite 1500
`Tysons Corner, VA 22102
`Phone: 703-289-5118
`jkesan@dimuro.com
`ckey@dimuro.com
`
`Michael W. Shore
`mshore@shorechan.com
`Alfonso G. Chan
`achan@shorechan.com
`Ari B. Rafilson
`arafilson@shorechan.com
`SHORE CHAN DEPUMPO LLP
`901 Main Street, Suite 3300
`Dallas, Texas 75202
`Telephone: 214-593-9110
`Facsimile: 214-593-9111
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`8
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`CERTIFICATE OF SERVICE
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`Pursuant to 37 C.F.R. §§ 42.6(e)(4) and 42.25(b), the undersigned certifies
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`that on January 13, 2021, a complete copy of Patent Owner’s Sur-Reply to
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`Petitioner’s Reply to Preliminary Response was filed electronically through the
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`Patent Trial and Appeal Board’s PTABE2E System and provided, via electronic
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`service, to the Petitioner by serving the correspondence address of record as
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`follows:
`
`Brian C. Nash, brian.nash@pillsburylaw.com
`PILLSBURY WINTHROP SHAW PITTMAN LLP
`401 Congress Avenue, Ste. 1700
`Austin, Texas 78701
`
`Evan Finkel, evan.finkel@pillsburylaw.com
`PILLSBURY WINTHROP SHAW PITTMAN LLP
`725 South Figueroa Street, Ste. 2800
`Los Angeles, CA 90017-5406
`
`
`Matthew W. Hindman, matthew.hindman@pillsburylaw.com
`PILLSBURY WINTHROP SHAW PITTMAN LLP
`2550 Hanover Street
`Palo Alto, CA 94304
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`/s/ Cecil E. Key
`Cecil E. Key
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`9
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`
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