IPR2020-01449
`U.S. Patent No. 7,149,867
`Patent Owner, FG SRC LLC
`
`Oral Argument Demonstratives
`
`Patent Trial and Appeal Board
`January 6, 2022
`
`Demonstrative Exhibits – Not Evidence
`
`1
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`EX2031
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`
`U.S. Patent No. 7,149,867
`Patent Owner, FG SRC LLC
`
`Oral Argument Demonstratives
`
`Patent Trial and Appeal Board
`January 6, 2022
`
`Demonstrative Exhibits – Not Evidence
`
`1
`
`EX2031
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`
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`The Revised Amended Claims
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`•Petitioner challenges ALL 19 claims
`
`•PO offers 4 Revised Amended Claims
`•claims 20 and 21 replacing claim 1
`•claim 28 replacing claim 9
`•claim 32 replacing claim 13
`
`•The remaining claims are amended only by
`virtue of depending from an amended claim
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`Demonstrative Exhibits – Not Evidence
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`2
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`EX2031
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`
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`THE REVISED
`AMENDED CLAIMS
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`Demonstrative Exhibits – Not Evidence
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`3
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`EX2031
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`
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`The Revised Amended Claims
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`• 20. A reconfigurable processor that instantiates an algorithm as hardware
`comprising:
`• a first memory having a first characteristic memory bandwidth and/or memory
`utilization; and
`• a data prefetch unit coupled to the memory, wherein the data prefetch unit is
`configured to retrieves only computational data required by the algorithm from
`a second memory of second characteristic memory bandwidth and/or memory
`utilization and places the retrieved computational data in the first memory
`wherein the data prefetch unit operates independent of and in parallel with logic
`blocks using the computational data, and wherein at least the first memory and
`data prefetch unit are configured to conform to needs of the algorithm, and the
`data prefetch unit is configured to match format and location of data in the
`second memory,
`• wherein the reconfigurable processor is neither integrated within nor
`comprises a conventional microprocessor, and
`• wherein the reconfigurable processor operates independent of and in
`parallel with a conventional microprocessor.
`Demonstrative Exhibits – Not Evidence
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`4
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`EX2031
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`
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`The Revised Amended Claims
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`• 21. A reconfigurable processor that instantiates an algorithm as hardware
`comprising:
`• a first memory having a first characteristic memory bandwidth and/or memory
`utilization; and
`• a data prefetch unit coupled to the memory, wherein the data prefetch unit is
`configured to retrieves only computational data required by the algorithm from
`a second memory of second characteristic memory bandwidth and/or memory
`utilization and places the retrieved computational data in the first memory
`wherein the data prefetch unit operates independent of and in parallel with logic
`blocks using the computational data, and wherein at least the first memory and
`data prefetch unit are configured to conform to needs of the algorithm, and the
`data prefetch unit is configured to match format and location of data in the
`second memory,
`• wherein the reconfigurable processor is neither integrated within nor
`comprises a conventional microprocessor, and
`• wherein the reconfigurable processor operates independent of and in
`parallel with a conventional microprocessor.
`Demonstrative Exhibits – Not Evidence
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`5
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`
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`The Revised Amended Claims
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`• 28. A reconfigurable hardware system, comprising:
`• a common memory; and
`• one or more reconfigurable processors that can instantiate an algorithm as
`hardware coupled to the common memory, wherein at least one of the
`reconfigurable processors includes a data prefetch unit to read and write only
`data required for computations by the algorithm between the data prefetch unit
`and the common memory wherein the data prefetch unit operates independent
`of and in parallel with logic blocks using the computational data, and wherein
`the data prefetch unit is configured to conform to needs of the algorithm and
`match format and location of data in the common memory,
`• wherein data required for computations by the algorithm comprises only
`data required for the instantiation and execution of the algorithm, and
`• wherein the at least one of the reconfigurable processors is neither
`integrated within nor comprises a conventional microprocessor, and
`• wherein the at least one of the reconfigurable processors operates
`independent of and in parallel with a conventional microprocessor.
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`Demonstrative Exhibits – Not Evidence
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`6
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`EX2031
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`
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`The Revised Amended Claims
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`32. A method of transferring data comprising:
`transferring data between a memory and a data prefetch unit in a
`reconfigurable processor, and
`transferring the data between a computational unit and the data access
`unit, wherein the computational unit and the data access unit, and the data
`prefetch unit are configured to conform to needs of an algorithm
`implemented on the computational unit and transfer only data necessary
`for computations by the computational unit, and wherein the prefetch unit
`operates independent of and in parallel with the computational unit,
`wherein data necessary for computations by the computational unit
`comprises only data necessary for the configuration and execution of
`computations by the computational unit, and
`wherein the computational unit is neither integrated within nor
`comprises a conventional microprocessor, and
`wherein the reconfigurable processor operates independent of and in
`parallel with a conventional microprocessor.
`Demonstrative Exhibits – Not Evidence
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`7
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`EX2031
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`A REASONABLE NUMBER
`OF CLAIMS ARE AMENDED
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`Demonstrative Exhibits – Not Evidence
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`8
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`EX2031
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`A REASONABLE NUMBER OF CLAIMS ARE AMENDED
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`Demonstrative Exhibits – Not Evidence
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`9
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`EX2031
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`A REASONABLE NUMBER OF CLAIMS ARE AMENDED
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`- 19 claims are challenged
`- 4 substitute claims are offered
`- (two for claim 1, and one each for claims 9 and 13)
`- 3 claims are canceled
`
`- The proposed amendments are similar and are
`therefore “reasonable as it would not present an
`undue burden on the Board.” Compliance v. Testing,
`No. IPR2020-00923, 2021 WL 1833328, at *2
`(P.T.A.B. May 7, 2021).
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`Demonstrative Exhibits – Not Evidence
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`10
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`EX2031
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`A REASONABLE NUMBER OF CLAIMS ARE AMENDED
`
`- the only difference between amended claims 20 and
`21 is the “is configured to” added in claim 21
`- to explicitly clarify what is already implicitly required by
`original claim 1:
`- reconfigurable hardware must first be configured before it
`can function as a data prefetch unit that “retrieves only
`computational data required by the algorithm” as claimed
`- Petitioner agrees: “Zhang necessarily uses information
`to instantiate an algorithm as hardware” and “Zhang-
`Gupta necessarily uses information to configure its
`reconfigurable components.” Paper 45 at 24, 25.
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`Demonstrative Exhibits – Not Evidence
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`11
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`EX2031
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`A REASONABLE NUMBER OF CLAIMS ARE AMENDED
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`- Revised amended claims 20 and 21 are necessary
`alternative versions of claim 1
`- the Board has rejected every instance in which PO
`modified the original claim language for clarification
` there was a need to propose an alternative revised
`amended claim without that modification
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`Demonstrative Exhibits – Not Evidence
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`12
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`EX2031
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`A REASONABLE NUMBER OF CLAIMS ARE AMENDED
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`- Proposed claims 23 and 24 (original claim 3), and 25 and
`26 (original claim 4) are amended only by virtue of
`depending from revised amended claims 20 & 21
`- There are no further substantive amendments in these
`dependent claims
`- 3 claims are cancelled, thereby maintaining 19 claims in
`the patent
`- adidas AG v. NIKE, Inc., IPR2013-00067, Paper 69 at 14-15,
`(P.T.A.B. Sep. 18, 2021) (canceling other claims can overcome
`presumption against presenting more than one substitute
`claim for an original claim)
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`Demonstrative Exhibits – Not Evidence
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`13
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`Proposed Revised Amended Claim 20
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`Demonstrative Exhibits – Not Evidence
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`14
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`Proposed Revised Amended Claims
`Respond To Grounds For Institution
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`Demonstrative Exhibits – Not Evidence
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`15
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`The Amendments Respond To Grounds For Institution
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`• Petitioner alleges that every element of each
`challenged claim is disclosed under 35 U.S.C. §103
`• The Board thus found that “Petitioner has shown
`sufficiently that Zhang in combination with Gupta
`would have rendered claims 1, 2, 4–8, 13–19
`obvious.” Paper 13, at 71.
`• Adding new substantive limitations is responsive to
`this ground for institution
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`Demonstrative Exhibits – Not Evidence
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`16
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`EX2031
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`
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`Proposed Revised Amended Claims
`Are Narrowing
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`Demonstrative Exhibits – Not Evidence
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`17
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`EX2031
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`The Revised Amended Claims Are Narrowing
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`• No limitations are deleted
`• New limitations are added
`• No existing limitation is broadened
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`Demonstrative Exhibits – Not Evidence
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`18
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`EX2031
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`The Revised Amended Claims Are Narrowing
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`• ALL revised amended claims include the two new limitations
`• “the reconfigurable processor operates independent of and in parallel
`with a conventional microprocessor” and
`• “the reconfigurable processor is neither integrated within nor comprises
`a conventional microprocessor”
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`Demonstrative Exhibits – Not Evidence
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`19
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`EX2031
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`
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`The Revised Amended Claims Are Narrowing
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`• The first new limitation “explicitly excludes the use of a conventional
`CPU as the computational unit of the claimed reconfigurable
`processor together with only limited reprogrammable peripheral
`components from the claim scope.” EX2030 ¶ 22.
`• The second new limitation further narrows claim scope by requiring
`that the reconfigurable processor operate independent of and in
`parallel with a conventional microprocessor and is similarly limiting. Id.
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`Demonstrative Exhibits – Not Evidence
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`20
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`EX2031
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`Proposed Revised Amended Claims Are
`Supported By The Written Description
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`Demonstrative Exhibits – Not Evidence
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`21
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`EX2031
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`The Written Description Supports The Revised Amendments
`
`• “the reconfigurable processor operates independent of and in
`parallel with a conventional microprocessor” and
`• “the reconfigurable processor is neither integrated within nor
`comprises a conventional microprocessor”
`• the ’867 Patent teaches that the RP is in the memory subsystem
`• “a number of RPs 100 are implemented within a memory Subsystem of a conventional
`computer, such as on devices that are physically installed in dual inline memory module
`(DIMM) sockets of a computer. In this manner the RPs 100 can be accessed by memory
`operations and so coexist well with a more conventional hardware platform”
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`Demonstrative Exhibits – Not Evidence
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`22
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`The Written Description Supports The Revised Amendments
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`• the RP is in the memory subsystem, which is
`• separate and apart from the primary conventional processor, and thus
`• operates independent of and in parallel with the primary conventional
`processor
`• Further written description support is found at ’867 Patent at
`abstract; 3:64-4:3; 5:19-29; 5:34-37; 5:59-6:4; 6:5-31, 6:47-
`58; Figs. 1-7 and related the descriptions
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`Demonstrative Exhibits – Not Evidence
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`23
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`EX2031
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`Proposed Revised Amended Claims Are
`Patentable Over The Prior Art
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`Demonstrative Exhibits – Not Evidence
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`24
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`EX2031
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`The Proposed Revised Amended Claims Are Patentable
`
`• The proposed amendments are not taught by Zhang, Gupta, Chien, or
`Trimberger
`• “By requiring that the reconfigurable processor is neither integrated
`within nor comprises a conventional microprocessor, the amendment
`excludes from the claim scope the use of a conventional CPU
`together with only limited reprogrammable peripheral components as
`well as “reconfigurable system” which has a CPU integrated in it.”
`EX2030 ¶21.
`• “In other words, the reconfigurable processor that instantiates an
`algorithm as hardware does not utilize a conventional microprocessor
`in any way for the purposes of said algorithm.” Id.
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`Demonstrative Exhibits – Not Evidence
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`25
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`EX2031
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`The Proposed Revised Amended Claims Are Patentable
`
`• Both new limitations are directly responsive to the Zhang, Gupta, and
`Chien prior art, which relies on the use of a CPU together with only
`“small pockets of reprogrammable logic.” EX2030 ¶22 (citing Ex.
`1003, at 13, col. 2:44-49).
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`Demonstrative Exhibits – Not Evidence
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`26
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`EX2031
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`The Proposed Revised Amended Claims Are Patentable
`
`• As shown by Dr. Mangione-
`Smith, Zhang discloses that
`“the processor running the
`main application is a
`conventional CPU, not a
`reconfigurable processor.”
`EX2030 ¶23 (citing Ex.
`1003, Fig. 2).
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`Demonstrative Exhibits – Not Evidence
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`27
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`EX2031
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`The Proposed Revised Amended Claims Are Patentable
`
`• Zhang simulation is based on a conventional processor:
`• “We perform cycle-based system-level simulation using a program-driven
`simulator based on MINT [22) that interprets program binaries and models
`configurable logic blocks behaviorly.” EX1003 at 15.
`• MINT is based on a conventional MIPS R3000 processor. This is not a
`reconfigurable processor. (see https://www.computer.org/csdl/proceedings-
`article/mascot/1994/00284422/12OmNxwnchJ.)
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`Demonstrative Exhibits – Not Evidence
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`28
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`EX2031
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`The Proposed Revised Amended Claims Are Patentable
`
`• Zhang discloses the use of programmable logic (i.e., an FPGA) “only
`as means to deliver data for use by that conventional CPU.
`• Zhang specifically states that it includes only ‘small blocks of
`programmable logic implemented into key elements of a baseline
`architecture’ to enable ‘the customization of architectural mechanisms
`and policies to match an application.’” EX2030 ¶23 (citing Ex. 1003,
`at 13, col. 2:44-49).
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`Demonstrative Exhibits – Not Evidence
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`29
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`EX2031
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`
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`The Proposed Revised Amended Claims Are Patentable
`
`• Zhang’s small blocks of programmable hardware facilitate movement
`of data between memory hierarchies to reduce latency at the point of
`data consumption. Id.
`• Unlike the ’867 Patent however, the final consumer is a conventional
`CPU, not a reconfigurable processor. Id.
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`Demonstrative Exhibits – Not Evidence
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`30
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`EX2031
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`The Proposed Revised Amended Claims Are Patentable
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`• Gupta builds on Zhang and proposes a CPU based prototype to
`implement the simulations performed by Zhang.
`• The purpose of the proposed Adaptive Memory Reconfiguration
`Management (AMRM) prototype board is to simulate a range of
`memory hierarchies for applications running on a host processor (a
`conventional CPU). Ex. 1004, at 9.
`• Like Zhang, Gupta only uses small bits of programmable logic in the
`AMRM prototype board, which is used for “configuration” of the
`memory controller. Id.
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`Demonstrative Exhibits – Not Evidence
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`31
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`EX2031
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`The Proposed Revised Amended Claims Are Patentable
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`• A description of the command interface is provided as well as the
`command execution. Ex. 1004, at 10.
`• This is the conventional way of requesting data with a CPU:
`• (1) the CPU requests data;
`• (2) if available in the cache, data is returned to the CPU;
`• (3) if not, a cache miss triggers prefetching a whole line into cache; and then
`• (4) data is returned to the CPU.
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`Demonstrative Exhibits – Not Evidence
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`32
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`EX2031
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`The Proposed Revised Amended Claims Are Patentable
`
`• The prefetch data unit is not modified to conform to the needs of the
`particular application/algorithm. Ex. 2028, ¶105.
`• Like Zhang, in Gupta and Chien, the main application remains in
`software (executed on the CPU). Ex. 2028, ¶70.
`• Gupta this relies on the operation of a CPU which is expressly
`excluded by the new claim limitation of this proposed amended claim.
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`Demonstrative Exhibits – Not Evidence
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`33
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`EX2031
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`
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`The Proposed Revised Amended Claims Are Patentable
`
`• Similarly, Trimberger, “teaches a tightly integrated conventional
`microprocessor that is augmented with a reconfigurable component
`for implementing special purpose instructions. Thus, Trimberger is
`intended to extend the instruction set of a conventional
`microprocessor.” EX2030 ¶25.
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`Demonstrative Exhibits – Not Evidence
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`34
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`EX2031
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`
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`The Proposed Revised Amended Claims Are Patentable
`
`• The Board’s citation to Trimberger’s disclosure of “the use of field
`programmable gate array (FPGA) logic configured as a co-processor
`attached to the same bus as the host processor” with “the field
`programmable co-processor execut[ing] [a] sub-routine” similarly
`describes a microprocessor tightly coupled to a reconfigurable
`instruction execution unit. Paper 38 at 16 (citing Trimberger).
`• The new limitation of the proposed amended claims specifically
`excludes such tightly coupled arrangement.
`
`Demonstrative Exhibits – Not Evidence
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`35
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`EX2031
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`
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`The Proposed Revised Amended Claims Are Patentable
`
`• The newly cited Poznanovic reference (EX1046) by Daniel
`Poznanovic—the same inventor of the challenged ’867 Patent—
`similarly fails does not disclose revised proposed amended Claim 20
`• Poznanovic—titled Interface For Integrating Reconfigurable
`Processors Into A General Purpose Computing System—discloses a
`RISC processor that is closely integrated with the reconfigurable
`hardware:
`• “[0062] The MAPs interface is controlled by commands in the ComList . . .
`[which] correspond directly to instructions in a reduced instruction set
`computer (‘RISC’) processor.” EX1046 at ¶ 62.
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`Demonstrative Exhibits – Not Evidence
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`36
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`EX2031
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`The Proposed Revised Amended Claims Are Patentable
`
`• This disclosure teaches that MAPs comprise a RISC processor
`• Further confirmed by [0092]:
`• “Register-to-Register Data Register Arithmetic/Logic Commands do register-
`to-register integer add and subtract operations, and OR, AND, and XOR
`bitwise logical operations.” EX1046 at ¶92
`• Therefore, Poznanovic discloses a reconfigurable processor that is
`tightly integrated with and dependent upon a general-purpose RISC
`processor
`• The presence of another conventional processor that is not integrated
`with the reconfigurable hardware is irrelevant
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`Demonstrative Exhibits – Not Evidence
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`37
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`EX2031
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`The Proposed Revised Amended Claims Are Patentable
`
`• In Poznanovic, the MAP hardware is a conventional processor of the
`“RISC” type.
`• Thus, Poznanovic does not disclose a reconfigurable processor
`“wherein the reconfigurable processor is neither integrated within nor
`comprises a conventional microprocessor,” and “wherein the
`reconfigurable processor operates independent of and in parallel with
`a conventional microprocessor.”
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`Demonstrative Exhibits – Not Evidence
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`38
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`EX2031
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`Proposed Revised Amended Claim 21
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`Demonstrative Exhibits – Not Evidence
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`39
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`EX2031
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`Proposed Revised Amended Claim 21
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`• Identical to proposed amended claim 20 with the addition of the self-
`evident statement that the data prefetch unit must be “configured”
`before it can retrieve data
`• Makes explicit what is already implied in original claim 1, which is that
`the “data prefetch unit [is] configured to conform to needs of the
`algorithm” before it can retrieve data as claimed
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`Demonstrative Exhibits – Not Evidence
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`40
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`EX2031
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`Proposed Revised Amended Claim 21
`
`• The limitation makes explicit the truism that the data prefetch unit
`must first be “configured” before it can “retrieve only computational
`data required by the algorithm from a second memory
`• The revised proposed amended claim element “configured to” does
`not broaden claim scope, and it does not “remov[e] restrictions on the
`type of the data that the data prefetch unit retrieves.” Paper 45 at 12.
`• This is nonsensical because the reconfigurable hardware must—by
`definition—be configured before it can operate
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`Demonstrative Exhibits – Not Evidence
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`41
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`EX2031
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`
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`Proposed Revised Amended Claim 21
`
`• Petitioner agrees: “Zhang necessarily uses information to instantiate
`an algorithm as hardware.” Paper 45 at 24; see also “Zhang-Gupta
`necessarily uses information to configure its reconfigurable
`components.” Id. at 25.
`• Petitioner thus admits that the claim limitation that the data prefetch
`unit “retrieve only computational data required by the algorithm”
`necessarily includes configuration data to first configure the
`reconfigurable hardware to instantiate a data prefetch unit in the first
`place.
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`Demonstrative Exhibits – Not Evidence
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`42
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`EX2031
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`
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`Proposed Revised Amended Claim 21
`
`• Petitioner argues that “PO appears to argue both that reconfigurable
`hardware cannot operate unless configured but also that
`reconfigurable hardware necessarily operates to retrieve configuration
`data” BUT
`• Petitioner fails to explain how any reconfigurable hardware can be
`configured before operating
`• It is undisputed that the reconfigurable hardware must be “configured”
`before it can instantiate an algorithm as hardware – this implies that
`the reconfigurable hardware must always retrieve configuration data
`first
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`Demonstrative Exhibits – Not Evidence
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`43
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`EX2031
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`Proposed Revised Amended Claim 28
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`Demonstrative Exhibits – Not Evidence
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`44
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`EX2031
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`Proposed Revised Amended Claim 28
`
`• Claim 28 includes the additional claim element “wherein data
`required for computations by the algorithm comprises only data
`required for the instantiation and execution of the algorithm”
`• This limits the scope by “exclud[ing] any other kind of information
`being read or written that might otherwise be considered
`computational data.” EX2030 ¶36.
`• The combination of Zhang, Gupta, Chien, and Trimberger does not
`teach or suggest this proposed amended limitations and therefore
`does not render obvious proposed amended claim 28.
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`Demonstrative Exhibits – Not Evidence
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`45
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`EX2031
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`
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`Proposed Revised Amended Claim 28
`
`• Written description support is found, for example, in the ’867 Patent’s
`descriptions of its preferred embodiments
`• a “reconfigurable processor is a computing device that contains reconfigurable
`components such as FPGAs and can, through reconfiguration, instantiate an
`algorithm as hardware.” ’867 Patent at 5:26-29.
`• The Patent so teaches that the reconfigurable hardware must be
`configured by instantiating an algorithm.
`• This is confirmed throughout the ’867 Patent, by teaching, for
`example, that “the data prefetch unit is configured by a program
`executed on the system.” ’867 Patent at 4:17-18.
`
`Demonstrative Exhibits – Not Evidence
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`46
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`EX2031
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`
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`Proposed Revised Amended Claim 28
`
`• Common sense as well as the entirety of the ’867 Patent confirms that
`this configuration is required before computations can be executed on
`the now-configured reconfigurable hardware. See, e.g., id. at
`Abstract; 3:64-4:26; 5:19-25; 5:26-29; 5:30-33; 5:34-37; 5:51-54; 5:59-
`6:4; 6:5-31, 6:47-58; 6:58-7:4; 7:23-32; 7:49-62; 7:63-8:41; Figs. 1-7
`and related descriptions (reconfigurable processor); Figs. 3, 8-14
`(prefetch and memory configurations).
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`Demonstrative Exhibits – Not Evidence
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`47
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`EX2031
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`
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`Proposed Revised Amended Claim 32
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`Demonstrative Exhibits – Not Evidence
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`48
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`EX2031
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`
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`Proposed Revised Amended Claim 32
`
`• Claim 32 includes the additional claim element “wherein data
`necessary for computations by the computational unit comprises
`only data necessary for the configuration and execution of
`computations by the computational unit”
`• This limits the scope by “exclud[ing] any other kind of information
`being read or written that might otherwise be considered
`computational data.” EX2030 ¶36.
`• The combination of Zhang, Gupta, Chien, and Trimberger does not
`teach or suggest this proposed amended limitations and therefore
`does not render obvious proposed amended claim 32.
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`Demonstrative Exhibits – Not Evidence
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`49
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`EX2031
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`
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`Proposed Revised Amended Claim 32
`
`• Written description support is found, for example, in the ’867 Patent’s
`descriptions of its preferred embodiments
`• a “reconfigurable processor is a computing device that contains reconfigurable
`components such as FPGAs and can, through reconfiguration, instantiate an
`algorithm as hardware.” ’867 Patent at 5:26-29.
`• The Patent so teaches that the reconfigurable hardware must be
`configured by instantiating an algorithm.
`• This is confirmed throughout the ’867 Patent, by teaching, for
`example, that “the data prefetch unit is configured by a program
`executed on the system.” ’867 Patent at 4:17-18.
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`Demonstrative Exhibits – Not Evidence
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`50
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`EX2031
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`
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`Proposed Revised Amended Claim 32
`
`• Common sense as well as the entirety of the ’867 Patent confirms that
`this configuration is required before computations can be executed on
`the now-configured reconfigurable hardware. See, e.g., id. at
`Abstract; 3:64-4:26; 5:19-25; 5:26-29; 5:30-33; 5:34-37; 5:51-54; 5:59-
`6:4; 6:5-31, 6:47-58; 6:58-7:4; 7:23-32; 7:49-62; 7:63-8:41; Figs. 1-7
`and related descriptions (reconfigurable processor); Figs. 3, 8-14
`(prefetch and memory configurations).
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`Demonstrative Exhibits – Not Evidence
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`51
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`EX2031
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`
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`END OF PRESENTATION REGARDING
`Revised Amended Claims
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`Demonstrative Exhibits – Not Evidence
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`52
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`EX2031
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`
`
`THE ORIGINAL CLAIMS
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`Demonstrative Exhibits – Not Evidence
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`53
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`EX2031
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`PRINTED PUBLICATION
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`Demonstrative Exhibits – Not Evidence
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`54
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`EX2031
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`Patent Owner FG SRC LLC’s Response to Petition for IPR2020-01449
`
`• Petitioner Has Failed To Meet Its Burden In Establishing Zhang, Gupta, And
`Chien As Printed Publications.
`A. Legal Standards for Establishing Printed Publication.
`Petitioner’s evidence establishes no more than “the only people who know
`how to find [the references] are the ones who created [them],” which fails to carry
`the burden of establishing that Zhang, Gupta, and Chien can be considered
`printed publications. Samsung, 929 F.3d at 1370-1373.
`
`Demonstrative Exhibits – Not Evidence
`
`55
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`Patent Owner FG SRC LLC’s Response to Petition for IPR2020-01449
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`B. Petitioner Has Not Met The Standards For Establishing Zhang, Gupta and
`Chien as Printed Publications.
`Petitioner has presented three theories as to why Zhang, Gupta, and Chien
`qualify as printed publications – each of these theories fails.
`• Conference distribution: the evidence does not support that Gupta was ever
`circulated at a conference and, if so, when and at which one
`• IEEE Xplore Website: Petitioner has shown no more than someone could
`theoretically find the reference because they were technically accessible
`• Online Library Records: the records identify only the name or general subject
`matter of the conference at which the substance of the reference was
`purportedly presented, and the information only shows when the references
`were catalogued, i.e., entered into the library’s system
`
`Demonstrative Exhibits – Not Evidence
`
`56
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`Patent Owner FG SRC LLC’s Response to Petition for IPR2020-01449
`
`• Petitioner has failed the burden of showing with particularity that the asserted
`references are likely to qualify as printed publications. Hulu, IPR2018-01039, Paper
`29, at 13.
`• without this, its asserted grounds fail. Intelligent Bio-Systems, Inc. v. Illumina
`Cambridge Ltd., 821 F.3d 1359, 1369 (Fed. Cir. 2016)
`
`Demonstrative Exhibits – Not Evidence
`
`57
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`
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`CLAIM CONSTRUCTIONS
`
`Demonstrative Exhibits – Not Evidence
`
`58
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`
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`Patent Owner FG SRC LLC’s Response to Petition for IPR2020-01449
`
`• Patent Owner’s Claim Constructions
`A. Agreed Terms
`
`Term
`“reconfigurable processor”
`
`“data prefetch unit”
`
`Agreed Construction
`A computing device that contains
`reconfigurable components such as
`FPGAs and can, through
`reconfiguration, instantiate an
`algorithm as hardware. Ex. 1001,
`5:26-28.
`A functional unit that moves data
`between members of a memory
`hierarchy. The movement may be as
`simple as a copy, or as complex as an
`indirect indexed strided copy into a
`unit stride memory. Ex. 1001, 5:40-43.
`
`Demonstrative Exhibits – Not Evidence
`
`59
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`Patent Owner FG SRC LLC’s Response to Petition for IPR2020-01449
`
`• Patent Owner’s Claim Constructions
`A. Agreed Terms
`
`Term
`“data access unit”
`
`“functional unit”
`
`“memory hierarchy”
`
`Agreed Construction
`A functional unit that accesses a
`component of a memory hierarchy, and
`delivers data directly to computational
`logic. Ex. 1001, 5:44-46.
`A set of logic that performs a specific
`operation. The operation may for example
`be arithmetic, logical, control, or data
`movement. Functional units are used as
`building blocks of reconfigurable logic. Ex.
`1001, 5:34-37.
`A collection of memories. Ex. 1001, 5;39.
`
`Demonstrative Exhibits – Not Evidence
`
`60
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`Patent Owner FG SRC LLC’s Response to Petition for IPR2020-01449
`
`• Patent Owner’s Claim Constructions
`In the co-pending district court litigation, the parties have additionally agreed to
`the following constructions:
`
`Term
`
`Agreed Construction
`
`Preamble:“A reconfigurable processor that instantiates an
`algorithm as hardware”
`“common memory ”
`
`“computational unit”
`
`“the data prefetch unit receives processed data”
`
`“configured to conform to needs of the algorithm”
`
`“reconfigurable logic”
`
`Preamble is limiting.
`
`An external memory shared by processors in a
`multiprocessor system.
`A functional unit of a reconfigurable processor that
`performs a computation.
`The data prefetch unit receives the results of the algorithm.
`
`Configured in reconfigurable logic to conform to the needs
`of the algorithm.
`Reconfigurable logic is composed of an interconnection of
`functional units, control, and storage that implements an
`algorithm and can be loaded into a Reconfigurable
`Processor.
`
`61
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`Patent Owner FG SRC LLC’s Response to Petition for IPR2020-01449
`
`• Patent Owner’s Claim Constructions
`A. Agreed Terms
`
`Term
`“data access unit”
`
`“functional unit”
`
`“memory hierarchy”
`
`Agreed Construction
`A functional unit that accesses a
`component of a memory hierarchy, and
`delivers data directly to computational
`logic. Ex. 1001, 5:44-46.
`A set of logic that performs a specific
`operation. The operation may for example
`be arithmetic, logical, control, or data
`movement. Functional units are used as
`building blocks of reconfigurable logic. Ex.
`1001, 5:34-37.
`A collection of memories. Ex. 1001, 5;39.
`
`Demonstrative Exhibits – Not Evidence
`
`62
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`
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`Patent Owner FG SRC LLC’s Response to Petition for IPR2020-01449
`
`• Patent Owner’s Claim Constructions
`A. Agreed Terms
`
`Term
`“data access unit”
`
`“functional unit”
`
`“memory hierarchy”
`
`Agreed Construction
`A functional unit that accesses a
`component of a memory hierarchy, and
`delivers data directly to computational
`logic. Ex. 1001, 5:44-46.
`A set of logic that performs a specific
`operation. The operation may for example
`be arithmetic, logical, control, or data
`movement. Functional units are used as
`building blocks of reconfigurable logic. Ex.
`1001, 5:34-37.
`A collection of memories. Ex. 1001, 5;39.
`
`Demonstrative Exhibits – Not Evidence
`
`63
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`Patent Owner FG SRC LLC’s Response to Petition for IPR2020-01449
`
`1. “retrieves only computational data required by the algorithm from a
`second memory… and places the retrieved computational data in the first
`memory”
`This term should be accorded its plain and ordinary meaning, which is “retrieves
`from a second memory that computational data which is required by the algorithm
`and no other computational data … and places the retrieved computational data in
`the first memory.” The plain meaning requires that no superfluous computational
`data is transferred to the first memory, that is, of the computational data that
`resides in the second memory, only the computational data that is actually used
`by the algorithm is transferred. Maximum efficiency is achieved by avoiding the
`transfer of computational data that is not actually required.
`
`Demonstrative Exhibits – Not Evidence
`
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`Patent Owner FG SRC LLC’s Response to Petition for IPR2020-01449
`
`2. “read and write only data required for computations by the algorithm
`between the data prefetch unit and the common memory”
`
`This term should be accorded its plain and ordinary meaning, which is “read,
`using the data prefetch unit, only data required for computations by the
`algorithm from common memory and write, using the data prefetch unit, only
`data required for computations by the algorithm.”
`
`Demonstrative Exhibits – Not Evidence
`
`65
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`
`
`GROUNDS
`
`Demonstrative Exhibits – Not Evidence
`
`66
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`Patent Owner FG SRC LLC’s Response to Petition for IPR2020-01449
`
`IX. Petitioner Has Failed To Demonstrate A Reasonable Likelihood Of Prevailing As
`To Any Challenged Claim.
`A. Ground 1: Claims 1-2, 4-8 And 13-19 Are Not Obvious Over Zhang And
`Gupta.
`1. The combination does not render obvious a “reconfigurable processor that
`instantiates an algorithm as hardware.”
`
`Demonstrative Exhibits – Not Evidence
`
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`Patent Owner FG SRC LLC’s Response to Petition for IPR2020-01449
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`2. The combination does not render obvious a “data prefetch unit.”
`
`Demonstrative Exhibits – Not Evidence
`
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`Patent Owner FG SRC LLC’s Response to Petition for IPR2020-01449
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`3. The combination does not render obvious a data prefetch unit “wherein the
`data prefetch unit retrieves only computational data required by the algorithm.”
`
`Demonst
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