UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`INTEL CORPORATION,
`Petitioner,
`v.
`FG SRC LLC,
`Patent Owner.
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`IPR2020-01449
`Patent No. 7,149,867
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`PATENT OWNER FG SRC LLC’S
`REPLY IN SUPPORT OF REVISED MOTION TO AMEND
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`
`Exhibit No.
`2001
`2002
`2003
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`2004
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`2005
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`2006
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`2007
`2008
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`2009
`2009-1
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`2009-2
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`2010
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`2011
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`2012
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`2013
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`LIST OF EXHIBITS
`
`Descriptions
`Declaration of Dr. Vojin Oklobdzija
`Cray, Britannica Online Encyclopedia
`Declaration of Brandon Freeman dated 10/25/18
`SRC Labs LLC and Saint Regis Mohawk Tribe v. Microsoft
`Corporation, No. 2:18-cv-00321-JLR, Dkt. 125 (W.D. Wash. Oct.
`25, 2018)
`Plaintiff’s Original Complaint For Patent Infringement in FG SRC
`LLC v. Intel Corp., No. 6:20-cv-00315-ADA (W.D. Texas), filed
`April 24, 2020
`Plaintiff’s First Amended Complaint For Patent Infringement in
`FG SRC LLC v. Intel Corp., No. 6:20-cv-00315-ADA (W.D.
`Texas), filed April 24, 2020
`Declaration of Mark Wollgast dated 09/10/18
`Xilinx, Inc. v. Saint Regis Mohawk Tribe, IPR2018-0195
`COTS Journal, UAVs Lead Push for Embedded Supercomputing
`Press Release: SRC Computers Chosen by Lockheed Martin for
`U.S. Army Program
`Declaration of Henning Schmidt
`Declaration of Henning Schmidt, Exhibit A, IEEE Xplore:
`Advanced Search
`Declaration of Henning Schmidt, Exhibit B, IEEE Xplore:
`Advanced Search Results
`Declaration Of Ryan Kastner, Ph.D. In Support Of FG SRC
`LLC’s Opening Claim Construction Brief in FG SRC LLC v. Intel
`Corp., No. 6:20-cv-00315-ADA (W.D. Texas), filed April 24,
`2020
`Peter McMahon, High Performance Reconfigurable Computing for
`Science and Engineering Applications (Thesis Oct. 2006).
`Caliga, Delivering Acceleration: The Potential for Increased HPC
`Application Performance Using Reconfigurable Logic
`D. A. Buell, D. Caliga, J. P. Davis, G. Quan, “The DARPA
`Boolean equation benchmark on a reconfigurable computer,”
`Proceedings of the Military and Aerospace Programmable Logic
`Devices (MAPLD) Conference, Washington, DC, 8-10 September
`2004
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`i
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`Exhibit No.
`2014
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`2015
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`2016
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`2017
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`2018
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`2019
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`2020
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`2021
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`2022
`2023
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`2024
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`2025
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`2026
`2027
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`2028
`
`2029
`2030
`
`Descriptions
`El-Araby, The Promise of High-Performance Reconfigurable
`Computing
`FG SRC LLC’s Opening Claim Construction Brief in FG SRC LLC
`v. Intel Corp., No. 6:20-cv-00315-ADA (W.D. Texas), filed April
`24, 2020
`Kerr Machine Co. d/b/a Kerr Pumps v. Vulcan Industrial Holdings,
`LLC, No. 6:20-cv-00200, Text Order dated Aug. 2, 2020 (W.D. Tex.)
`
`Multimedia Content Mgmt. LLC v. Dish Network L.L.C., No. 6:18-
`cv-00207, Dkt. 73 (W.D. Tex.)
`Solas OLED v. Dell Techs. Inc., No. 6:19-cv-00514, Text Order
`dated June 23, 2020
`Kerr Machine Co. v. Vulcan Indus. Holdings, LLC, No. 6:20-cv-
`200, Dkt. 28 (W.D. Tex. July 31, 2020)
`Kerr Machine Co. v. Vulcan Indus. Holdings, LLC, No. 6:20-cv-
`200, Dkt. 24 (W.D. Tex. June 14, 2020)
`Kerr Machine Co. v. Vulcan Indus. Holdings, LLC, No. 6:20-cv-
`200, Dkt. 12 (W.D. Tex., June 14, 2020)
`Email from J. Yi to Counsel (Aug. 3, 2020)
`FG SRC LLC v. Intel Corp., No. 1:20-cv-00834, Dkt. 48 (W.D.
`Tex. Nov. 23, 2020) (Amended Schedule)
`Continental Intermodal Group - Trucking LLC v. Sand Revolution
`LLC, No. 7:18-cv-00147, Text Order dated July 22, 2020 (W.D.
`Tex.)
`Solas OLED v. Dell Techs. Inc., No. 6:19-cv-00515, Text Order
`dated Jun. 23, 2020
`2019-07-11 - DirectStream MSFT - Huppenthal Declaration
`Declaration of William Mangione-Smith, Ph.D., In Support of FG
`SRC LLC’s Motion to Amend
`Declaration of Dr. William Mangione-Smith in support of Patent
`Owner Response
`Deposition Transcript of Dr. Stanley Shanfield
`Declaration of William Mangione-Smith, Ph.D., In Support of FG
`SRC LLC’s Revised Motion to Amend
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`ii
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`I.
`II.
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`TABLE OF CONTENTS
`INTRODUCTION .................................................................................................... 1
`A REASONABLE NUMBER OF CLAIMS ARE AMENDED. ............................ 1
`A.
`In Light Of The Board’s Findings Regarding The Original Claims
`And The Proposed Amended Claims, Patent Owner’s Revised
`Proposed Amended Claims Are Needed........................................................ 1
`III. THE PROPOSED AMENDED CLAIMS DO NOT INTRODUCE NEW
`SBJECT MATTER. .................................................................................................. 3
`IV. THE PROPOSED AMENDED CLAIMS ARE PATENTABLE............................ 4
`A.
`Proposed Amended Claim 20 (Replacing Original Claim 1) ........................ 4
`B.
`Proposed Amended Claim 21 (Replacing Claim 1)....................................... 7
`C.
`Proposed Amended Claim 28 (Replacing Claim 9)....................................... 9
`D.
`Proposed Amended Claim 32 (Replacing Claim 13)................................... 11
`CONCLUSION ...................................................................................................... 12
`V.
`APPENDIX A – COMPARISON OF CLAIMS 20 AND 21 .......................................... 16
`APPENDIX B - PROPOSED AMENDED CLAIM 20 ................................................... 17
`APPENDIX C – PROPOSED AMENDED CLAIM 21 .................................................. 18
`APPENDIX D – PROPOSED AMENDED CLAIM 28 .................................................. 19
`APPENDIX E – PROPOSED AMENDED CLAIM 32 .................................................. 20
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`iii
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`CASES:
`
`TABLE OF AUTHORITIES
`
`Aqua Products, Inc. v. Matal,
`, 872 F.3d 1290 (Fed. Cir. 2017) ............................................................................... 4
`Ariad Pharms., Inc. v. Eli Lilly & Co.,
`, 598 F.3d 1336 (Fed. Cir. 2010) ............................................................................... 3
`ADMINISTRATIVE ORDERS:
`
`Compliance v. Testing,
`Case IPR2020-00923, 2021 WL 1833328, at *2 (P.T.A.B. May 7, 2021) .......... 3
`Lectrosonics, Inc. v. Zaxcom, Inc.,
`IPR2018-01129, Paper 15 (PTAB, February 25, 2019) .................................2, 4, 6
`Nichia Corp. v. Emcore Corp.,
`IPR2012-00005, Paper 27 (PTAB June 3, 2013)..................................................... 3
`STATUTES:
`
`35 U.S.C. § 101 ................................................................................................................. 5
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`35 U.S.C. § 103 ...................................................................................................... 5, 8, 11
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`35 U.S.C. § 112 ................................................................................................................. 5
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`35 U.S.C. § 316 ................................................................................................................. 2
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`REGULATIONS:
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`37 C.F.R. § 42.121 ............................................................................................................. 1
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`37 C.F.R. § 42.24 (a)(1)(vi) ............................................................................................. 5
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`iv
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`INTRODUCTION
`I.
`Patent Owner submits its Reply ISO Its Revised Motion to Amend (“RMTA”)
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`requesting amendment of certain claims of U.S.P. 7,149,867 (“’867 patent).
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`II. A REASONABLE NUMBER OF CLAIMS ARE AMENDED.
`Petitioner challenges claims 1 through 19. SRC proposes only 4 substantive
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`substitute claims (two for claim 1 and one each for claims 9 and 13) and cancels 3
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`claims. 35 U.S.C.A. § 316 (Patent Owner may “cancel a challenged claim or propose
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`a reasonable number of substitute claims.”) The proposed amendments in the
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`proposed substitute claims are similar and are therefore “reasonable as it would not
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`present an undue burden on the Board. Compliance v. Testing, No. IPR2020-00923,
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`2021 WL 1833328, at *2 (P.T.A.B. May 7, 2021).
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`In Light Of The Board’s Findings Regarding The Original Claims
`A.
`And The Proposed Amended Claims, Patent Owner’s Revised Proposed
`Amended Claims Are Needed.
`Petitioner grossly exaggerates the de minimis difference between the two
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`alternative amended claims for claim 1. As illustrated in Appendix A, the only
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`difference between amended claims 20 and 21 is the “is configured to” added to
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`explicitly clarify what is already implicitly required by original claim 1, which is
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`that the reconfigurable hardware must first be configured as a data prefetch unit
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`before it can function as a data prefetch unit that “retrieves only computational data
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`required by the algorithm” as claimed. Indeed, Petitioner inadvertently admits this
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`point, as explained below. However, given that the Board’s preliminary guidance
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`1
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`found every single instance in which Patent Owner attempted to modify the original
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`claim language for clarification broadening, there was a need to propose an
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`alternative revised amended claim without that modification. Should the Board find
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`that Patent Owner’s bona fide attempt to clarify the original claim language in
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`revised proposed amended claim 21 is improper, it should simply proceed to analyze
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`the claim without the offending language in revised proposed amended claim 20.
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`Revised amended claims 23 and 24 (original claim 3), and 5 and 6 (original
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`claim 4) are amended only by virtue of depending from revised amended claims 20
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`and 21. There are no further substantive amendments in these dependent claims.
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`Finally, Patent Owner’s RMTA cancels three claims, thereby maintaining 19
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`claims in the patent. “Here is a circumstance where the presumption against
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`presenting more than one substitute claim for each original claim is overcome by the
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`total number of canceled claims and the manifest reasonableness of the number of
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`proposed substitute claims offered in lieu of those canceled claims.” adidas AG v.
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`NIKE, Inc., IPR2013-00067, Paper 69 at 14-15, (P.T.A.B. Sep. 18, 2021) (proposed
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`substitution of two claims in place of one original claim, and cancellation of forty-
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`six original claims constitutes a presentation of a reasonable number of substitute
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`claims). Here, only two substitute claims (20 and 21) are being offered for original
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`claim (1) (and only with a minor difference). The only other revised amended claims
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`are substituted for one original claim each (revised amended claim 29 for original
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`2
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`claim 9, and revised amended claim 32 for original claim 13). No other claims are
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`substantively amended.
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`III. THE PROPOSED AMENDED CLAIMS DO NOT INTRODUCE NEW
`SBJECT MATTER.
`Petitioner raises multiple form-over-substance complaints about Patent
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`Owner’s written description support in the revised motion to amend. First, Petitioner
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`complains that “PO improperly relegates its purported support for each proposed
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`claim to Appendix A’s claim listing, not the motion itself.” Paper 45 at 5 (citing
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`Lectrosonics, Paper 15 at 8). However, Petitioner quotes Lectrosonics out of
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`context. There, the Board made clear that “the claim listing may be filed as an
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`appendix to the motion to amend and shall not count toward the page limit for the
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`motion.” Lectrosonics, Paper 15 at 8. The requirement to set the written description
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`support forth in the motion itself is aimed to prevent parties from skirting the 25-
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`page limit of a Motion to Amend. 37 C.F.R. § 42.24 (a)(1)(vi). Patent Owner’s
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`RMTA included its written description support on pages 20-24, well within the limit.
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`Paper 29 at 20-24. Whether or not the written description support is provided within
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`that 25-page limit before or after he headline “Appendix” is truly the definition of a
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`form-over-substance argument.
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`Second, Petitioner complains that “PO’s Appendix A cites to the issued patent
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`rather than to the original application’s disclosure.” Paper 45 at 5-6. This complaint
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`is also irrelevant because the cited art predates both the ’867 Patent (filed June 16,
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`3
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`2004) as well as the provisional (filed June 18, 2003). Petitioner’s primary
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`references Chien (EX1006), Zhang (EX1004), and Gupta (EX1005) are dated 1996,
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`1997, and 2000, respectively. Similarly, Petitioner’s additional prior art Trimberger
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`(EX1037) and Poznanovic (EX1046) are dated 1998 and Mar. 6, 2003, respectively.
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`Thus, without disclaiming priority to the provisional application if it were to make a
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`difference for some as yet uncited prior art reference, citation to the actual patent
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`disclosure is sufficient for the purposes of this IPR. Petitioner’s complaint that “PO
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`fails to set forth support in the Provisional’s disclosure and thus fails to show benefit
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`to that earlier filing date” is rendered asinine for the same reason.
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`Finally, Petitioner’s complaint that “PO proposes fifteen substitute dependent
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`claims without proffering any written description support for those claims.” This
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`misrepresents the RMTA which provides written description support for each
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`element of each independent claim which is, of course, incorporated by reference in
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`the dependent claims which are amended only by virtue of depending from that
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`revised proposed amended independent claim. Petitioner’s head-in-the-sand
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`approach should be fully discounted.
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`IV. THE PROPOSED AMENDED CLAIMS ARE PATENTABLE.
`Proposed Amended Claim 20 (Replacing Original Claim 1)
`A.
`Written description support for the proposed amended claim elements is
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`found, for example, in the ’867 Patent’s descriptions of its preferred embodiments.
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`Specifically, the ’867 Patent teaches that
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`4
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`a number of RPs 100 are implemented within a memory Subsystem of
`a conventional computer, such as on devices that are physically
`installed in dual inline memory module (DIMM) sockets of a
`computer. In this manner the RPs 100 can be accessed by memory
`operations and so coexist well with a more conventional hardware
`platform.
`’867 Patent at 6:20-25. This description clarifies that the RP is in the memory
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`subsystem, separate and apart from the primary conventional processor, and operates
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`independent of and in parallel. Further written description support for this proposed
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`claim element is found at ’867 Patent at abstract; 3:64-4:3; 5:19-29; 5:34-37; 5:59-
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`6:4; 6:5-31, 6:47-58; Figs. 1-7 and related the descriptions.
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`Revised amended claim 20 narrows original claim 1 for the reasons set forth
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`in the RMTA. Petitioner does not challenge this in its Response.
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`Revised amended claim 20 is responsive to a ground for institution for the
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`reasons set forth in the RMTA. Petitioner’s Response does not challenge this.
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`The cited prior art in the Petition and Petitioner’s Response to Patent Owners
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`Motion to Amend does not teach or suggest the proposed amended limitation and
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`does not render obvious proposed amended claim 20 for the reasons set forth in the
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`RMTA. Further, the Zhang simulation is based on a conventional processor: “We
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`perform cycle-based system-level simulation using a program-driven simulator
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`based on MINT [22) that interprets program binaries and models configurable logic
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`5
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`blocks behaviorly.” EX1003 at 15. MINT is based on a conventional MIPS R3000
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`processor.1 This is not a reconfigurable processor.
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`The newly cited Poznanovic reference (EX1046) (“Poznanovic”), by Daniel
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`Poznanovic—the same inventor of the challenged ’867 Patent—similarly fails to
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`anticipate or render obvious revised proposed amended Claim 20. This makes sense
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`since the same inventor, Mr. Poznanovic, filed for and was granted another different
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`patent—the ’867 Patent. Specifically, Poznanovic—titled Interface For Integrating
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`Reconfigurable Processors Into A General Purpose Computing System—discloses
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`a RISC processor that is closely integrated with the reconfigurable hardware:
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`[0062] The MAPs interface is controlled by commands in the ComList
`or direct commands issued by an instruction processor or another
`MAP. . . . Commands in the ComList correspond directly to
`instructions in a reduced instruction set computer (“RISC”)
`processor. These instructions are a small set of simple instructions
`for moving data, testing conditions, and branching. FPGA control
`processors can be reconfigured to function with various instruction
`sets, depending upon implementation needs.
`EX1046 at ¶ 62. This disclosure teaches that MAPs comprise a RISC processor, as
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`confirmed further by the disclosure that “[0092] Register-to-Register Data Register
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`Arithmetic/Logic Commands do register-to-register integer add and subtract
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`operations, and OR, AND, and XOR bitwise logical operations.” Id. at ¶ 92.
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`Therefore, the newly disclosed prior-art application described in Poznanovic
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`discloses a reconfigurable processor that is tightly integrated with and dependent
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`1 https://www.computer.org/csdl/proceedings-article/mascot/1994/00284422/12OmNxwnchJ.
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`upon a general-purpose RISC processor. Just because the reconfigurable processor
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`may be independent of some conventional processors in that system, as the one shown
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`in figure 1 for example, does not mean that it is not dependent on another
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`conventional processor in the system. Indeed, the Poznanovic reprogrammable
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`processor is fully dependent upon a conventional RISC processor. That the same
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`system happens to contain another conventional processor that is not integrated with
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`the reconfigurable hardware does not negate the fact that the reconfigurable hardware
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`is indeed integrated with a conventional processor. Such a conventional RISC
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`processor necessarily includes conventional instructions including to branch a
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`program, load, and store values to memory, and do arithmetic and logical operations
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`on data stored in registers. In Poznanovic, the MAP hardware is disclosed to do all
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`of these. Not only does Poznanovic claim that it uses a RISC processor (as explained
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`above), it also discloses all of the elements necessary to make it a conventional
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`processor of the “RISC” type. Thus, Poznanovic does not disclose a reconfigurable
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`processor “wherein the reconfigurable processor is neither integrated within nor
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`comprises a conventional microprocessor,” and “wherein the reconfigurable
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`processor operates
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`independent of and
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`in parallel with a conventional
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`microprocessor.”
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`Proposed Amended Claim 21 (Replacing Claim 1)
`B.
`Revised proposed amended claim 21 is proper for the same reasons as revised
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`proposed amended claim 20. The only difference between proposed amended claim
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`21 and proposed amended claim 20 is the addition of the claim requirement that the
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`data prefetch unit must be “configured” before it can retrieve data. The purpose of
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`this correction is to make explicit what is already implied in original claim 1, which
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`is that the “data prefetch unit [is] configured to conform to needs of the algorithm”
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`before it can retrieve data as claimed. The limitation makes explicit the truism that
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`the data prefetch unit must first be “configured” before it can “retrieve only
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`computational data required by the algorithm from a second memory.” This new
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`limitation does not broaden claim scope and is directly responsive to the cited ground
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`for institution because it adds a new claim limitation.
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`Written description support for the claim elements is found for the reasons set
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`forth regarding revised proposed amended claim 20 above. See Section IV.A.
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`Revised proposed amended claim 21 narrows the scope of original claim 1 for
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`the reasons set forth in the RMTA. Petitioner argues that the revised proposed
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`amended claim element “configured to” broadens claim scope by removing
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`restrictions on the type of the data that the data prefetch unit retrieves. Paper 45 at
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`12. This is nonsensical because the reconfigurable hardware must—by definition—
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`be configured before it can operate. The proposed revision simply states what is
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`already inherently true, that the reconfigurable hardware must necessarily be
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`configured to implement a data prefetch unit before it can operate as a data prefetch
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`unit and retrieve only computational data required by the algorithm. Importantly,
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`Petitioner inadvertently admits that reconfigurable hardware must necessarily
`8
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`retrieve configuration data in order to instantiate an algorithm as hardware and
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`perform its computations in its opposition to the revised motion to amend: “Zhang
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`necessarily uses information to instantiate an algorithm as hardware.” Paper 45 at
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`24; see also “Zhang-Gupta necessarily uses information
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`to configure
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`its
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`reconfigurable components.” Id. at 25. Petitioner thus admits that the claim
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`limitation that the data prefetch unit “retrieve only computational data required by
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`the algorithm” necessarily includes configuration data to first configure the
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`reconfigurable hardware to instantiate a data prefetch unit in the first place.
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`Revised proposed amended claim 21 is responsive to a ground for institution
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`for the reasons set forth in the RMTA. Adding new claim limitations, by definition,
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`is responsive to a finding of obviousness or anticipation. Petitioner does not
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`challenge this in its Response in any detail.
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`The cited prior art in the Petition and Petitioner’s Response to Patent Owners
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`Motion to Amend does not teach or suggest the proposed amended limitation and
`
`does not render obvious proposed amended claim 21 for the reasons set forth
`
`regarding revised proposed amended claim 20 above. See Section IV.A.
`
`Proposed Amended Claim 28 (Replacing Claim 9)
`C.
`Written description support for the proposed amended claim elements
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`“wherein the at least one of the reconfigurable processors is neither integrated within
`
`nor comprises a conventional microprocessor” and “wherein the at least one of the
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`reconfigurable processors operates independent of and in parallel with a
`9
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`

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`conventional microprocessor” is found is found for the reasons set forth regarding
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`revised proposed amended claim 20 above. See Section IV.A.
`
`Written description support for the proposed amended claim element
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`“wherein data required for computations by the algorithm comprises only data
`
`required for the instantiation and execution of the algorithm” is found, for example,
`
`in the ’867 Patent’s descriptions of its preferred embodiments. Specifically, the ’867
`
`Patent teaches that a “reconfigurable processor is a computing device that contains
`
`reconfigurable components such as FPGAs and can, through reconfiguration,
`
`instantiate an algorithm as hardware.” ’867 Patent at 5:26-29. The Patent so teaches
`
`that the reconfigurable hardware must be configured by instantiating an algorithm.
`
`This is confirmed throughout the ’867 Patent, by teaching, for example, that “the
`
`data prefetch unit is configured by a program executed on the system.” ’867 Patent
`
`at 17-18. Common sense as well as the entirety of the ’867 Patent confirms that this
`
`configuration is required before computations can be executed on the now-
`
`configured reconfigurable hardware. See, e.g., id. at Abstract; 3:64-4:26; 5:19-25;
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`5:26-29; 5:30-33; 5:34-37; 5:51-54; 5:59-6:4; 6:5-31, 6:47-58; 6:58-7:4; 7:23-32;
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`7:49-62; 7:63-8:41; Figs. 1-7 and related descriptions (reconfigurable processor);
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`Figs. 3, 8-14 (prefetch and memory configurations).
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`Revised amended claim 28 narrows the scope of original claim 9 for the
`
`reasons set forth in the RMTA. By definition, additional limitations narrow claim
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`scope.
`
`10
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`Revised amended claim 28 adds new limitations that are responsive to a
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`finding of obviousness or anticipation.
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`The cited prior art in the Petition and Petitioner’s Response to Patent Owners
`
`Motion to Amend does not teach or suggest the proposed amended limitation and
`
`does not render obvious proposed amended claim 21 for the reasons set forth
`
`regarding revised proposed amended claim 20 above. See Section IV.A.
`
`Proposed Amended Claim 32 (Replacing Claim 13)
`D.
`Written description for the elements “wherein the computational unit is
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`neither integrated within nor comprises a conventional microprocessor” and
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`“wherein the reconfigurable processor operates independent of and in parallel with
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`a conventional microprocessor” is found in section IV.A (claim 20).
`
`Written description support for the proposed amended claim element
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`“wherein data necessary for computations by the computational unit comprises only
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`data necessary for the configuration and execution of computations by the
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`computational unit” is found, for example, in the ’867 Patent’s descriptions of its
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`preferred embodiments. Specifically, the ’867 Patent teaches that a “reconfigurable
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`processor is a computing device that contains reconfigurable components such as
`
`FPGAs and can, through reconfiguration, instantiate an algorithm as hardware.”
`
`’867 Patent at 5:26-29. The Patent so teaches that the reconfigurable hardware must
`
`be configured by instantiating an algorithm. This is confirmed throughout the ’867
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`Patent, by teaching, for example, that “the data prefetch unit is configured by a
`11
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`program executed on the system.” ’867 Patent at 17-18. Common sense and the
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`’867 Patent confirm that configuration is required before computations can be
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`executed on the now-configured reconfigurable hardware. See, e.g., id. at Abstract;
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`3:64-4:26; 5:19-25; 5:26-29; 5:30-33; 5:34-37; 5:51-54; 5:59-6:4; 6:5-31, 6:47-58;
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`6:58-7:4; 7:23-32; 7:49-62; 7:63-8:41; Figs. 1-7 and related descriptions
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`(reconfigurable processor); Figs. 3, 8-14 (prefetch and memory configurations).
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`Revised proposed amended claim 32 narrows the scope of original claim 13
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`for the reasons set forth in the RMTA. Additional limitations narrow claim scope.
`
`Revised proposed amended claim 32 is responsive to a ground for institution
`
`for the reasons set forth in the Revised Motion to Amend. Adding new claim
`
`limitations, by definition, is responsive to a finding of obviousness or anticipation.
`
`The cited prior art in the Petition and Petitioner’s Response to Patent Owners
`
`Motion to Amend does not teach or suggest the proposed amended limitation and
`
`does not render obvious proposed amended claim 21 for the reasons set forth
`
`regarding revised proposed amended claim 20 above. See Section IV.A.
`
`V. CONCLUSION
`For the reasons set forth herein, the proposed amended claims are patentable.
`
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`Date: December 8, 2021
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`Respectfully submitted,
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`/s/ Jay P. Kesan
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`DiMuroGinsberg, PC-
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`DGKeyIP Group
`Jay P. Kesan
`Reg. No. 37,488
`Cecil E. Key (admission pro hac vice
`pending)
`1750 Tysons Blvd., Suite 1500
`Tysons Corner, VA 22102
`Phone: 703-289-5118
`jkesan@dimuro.com
`ckey@dimuro.com
`
`Michael W. Shore
`mshore@shorechan.com
`Alfonso G. Chan
`achan@shorechan.com
`Ari B. Rafilson
`arafilson@shorechan.com
`SHORE CHAN DEPUMPO LLP
`901 Main Street, Suite 3300
`Dallas, Texas 75202
`Telephone: 214-593-9110
`Facsimile: 214-593-9111
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`CERTIFICATE OF SERVICE
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`Pursuant to 37 C.F.R. §§ 42.6(e)(4) and 42.25(b), the undersigned certifies that
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`on December 8, 2021 a complete copy of PATENT OWNER FG SRC LLC’S REPLY
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`IN SUPPORT OF REVISED MOTION TO AMEND was filed electronically through
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`the Patent Trial and Appeal Board’s PTABE2E System and provided, via electronic
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`service, to the Petitioner by serving the correspondence address of record as follows:
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`Dated: December 8, 2021
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`/s/ Jay P. Kesan
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`CERTIFICATE OF COMPLIANCE
`I hereby certify that the foregoing PATENT OWNER FG SRC LLC’S REPLY
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`IN SUPPORT OF REVISED MOTION TO AMEND complies with the page
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`limitation of 37 C.F.R. § 42.24(c)(3) because it is no more than twelve pages. I
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`further certify that the foregoing Response complies with the general format
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`requirements of 37 C.F.R. § 42.6(a) and has been prepared using Microsoft Word in
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`14-point Times New Roma proportional font.
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`Dated: December 8, 2021
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`/s/ Jay P. Kesan
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`APPENDIX A – COMPARISON OF CLAIMS 20 AND 21
`Comparison of proposed amended claims 20 and 21.
`
`Amended Claim 20
`20. A reconfigurable processor that
`instantiates an algorithm as hardware
`comprising:
`a first memory having a first
`characteristic memory bandwidth
`and/or memory utilization; and
`a data prefetch unit coupled to the
`memory, wherein the data prefetch
`unit retrieves only computational
`data required by the algorithm from a
`second memory
`of
`second
`characteristic memory bandwidth
`and/or memory utilization and places
`the retrieved computational data in
`the first memory wherein the data
`prefetch unit operates independent of
`and in parallel with logic blocks
`using the computational data, and
`wherein at least the first memory and
`data prefetch unit are configured to
`conform to needs of the algorithm,
`and
`the data prefetch unit
`is
`configured to match format and
`location of data
`in
`the second
`memory,
`
`reconfigurable
`the
`wherein
`is neither
`integrated
`processor
`nor
`comprises
`a
`within
`conventional microprocessor, and
`wherein
`the
`reconfigurable
`processor operates independent of
`and in parallel with a conventional
`microprocessor.
`
`Amended Claim 21
`20. A reconfigurable processor that
`instantiates an algorithm as hardware
`comprising:
`a first memory having a first
`characteristic memory bandwidth
`and/or memory utilization; and
`a data prefetch unit coupled to the
`memory, wherein the data prefetch
`unit is configured to retrieve[s] only
`computational data required by the
`algorithm from a second memory of
`second
`characteristic memory
`bandwidth and/or memory utilization
`and
`places
`the
`retrieved
`computational data
`in
`the
`first
`memory wherein the data prefetch
`unit operates independent of and in
`parallel with logic blocks using the
`computational data, and wherein at
`least the first memory and data
`prefetch unit are configured
`to
`conform to needs of the algorithm,
`and
`the data prefetch unit
`is
`configured to match format and
`location of data
`in
`the second
`memory,
`reconfigurable
`the
`wherein
`is neither
`integrated
`processor
`nor
`comprises
`a
`within
`conventional microprocessor, and
`wherein
`the
`reconfigurable
`processor operates independent of
`and in parallel with a conventional
`microprocessor.
`
`
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`APPENDIX B – PROPOSED AMENDED CLAIM 20
`Proposed Amended Claim 20 is set forth below. There are no deletions, and
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`underlining is used to indicate additions.
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`Proposed Amended Claim 20. A reconfigurable processor that instantiates
`an algorithm as hardware comprising:
`a first memory having a first characteristic memory bandwidth and/or
`memory utilization; and
`a data prefetch unit coupled to the memory, wherein the data prefetch unit
`retrieves only computational data required by the algorithm from a
`second memory of second characteristic memory bandwidth and/or
`memory utilization and places the retrieved computational data in the
`first memory wherein the data prefetch unit operates independent of
`and in parallel with logic blocks using the computational data, and
`wherein at least the first memory and data prefetch unit are configured
`to conform to needs of the algorithm, and the data prefetch unit is
`configured to match format and location of data in the second memory,
`wherein the reconfigurable processor is neither integrated within nor
`comprises a conventional microprocessor, and
`wherein the reconfigurable processor operates independent of and in
`parallel with a conventional microprocessor.
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`
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`APPENDIX C – PROPOSED AMENDED CLAIM 21
`Proposed Amended Claim 21 is set forth below. [Brackets] are used to indicate
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`deletions, and underlining is used to indicate additions.
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`Proposed Amended Claim 21. A reconfigurable processor that instantiates
`an algorithm as hardware comprising:
`a first memory having a first characteristic memory bandwidth and/or
`memory utilization; and
`a data prefetch unit coupled to the memory, wherein the data prefetch unit is
`configured to retrieve[s] only computational data required by the
`algorithm from a second memory of second characteristic memory
`bandwidth and/or memory utilization and places the retrieved
`computational data in the first memory wherein the data prefetch unit
`operates independent of and in parallel with logic blocks using the
`computational data, and wherein at least the first memory and data
`prefetch unit are configured to conform to needs of the algorithm, and
`the data prefetch unit is configured to match format and location of
`data in the second memory,
`wherein the reconfigurable processor is neither integrated within nor
`comprises a conventional microprocessor, an