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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`FG SRC LLC,
`Patent Owner.
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`
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`
`
`IPR2020-01449
`Patent No. 7,149,867
`
`
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`PATENT OWNER FG SRC LLC’S PRELIMINARY RESPONSE TO
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 7,149,867
`
`
`
`TABLE OF CONTENTS
`
`I.
`
`INTRODUCTION ........................................................................................... 1
`
`II.
`
`RELATED PROCEEDINGS .......................................................................... 1
`
`III.
`
`SRC BACKGROUND .................................................................................... 1
`
`IV. THE BOARD SHOULD DENY INSTITUTION UNDER § 314(a). ............ 2
`
`A. All of the Fintiv Factors Favor Denial of Institution. ........................... 3
`
`B.
`
`Efficiency and Integrity of the System Are Best Served by
`Denying Institution. .............................................................................. 7
`
`V.
`
`TECHNOLOGY BACKGROUND ................................................................ 9
`
`A.
`
`Reconfigurable Processors and FPGAs ................................................ 9
`
`B. Memory Hierarchies ........................................................................... 10
`
`C.
`
`Prefetching .......................................................................................... 11
`
`VI. THE ’867 PATENT ....................................................................................... 12
`
`A.
`
`The Invention Of The ’867 Patent. ..................................................... 13
`
`B.
`
`C.
`
`Prefetching .......................................................................................... 16
`
`The ’867 Patent Discloses The Exact Technology Of Chien,
`Zhang, And Gupta In Its “Relevant Background” Discussion. .......... 17
`
`VII. THE ASSERTED PRIOR ART REFERENCES .......................................... 19
`
`A.
`
`Chien (Ex. 1005) ................................................................................. 20
`
`B.
`
`C.
`
`Zhang (Ex. 1003) ................................................................................ 22
`
`Gupta (Ex. 1004) ................................................................................. 24
`
`VIII. PETITIONER HAS FAILED TO MEET ITS BURDEN IN
`ESTABLISHING ZHANG, GUPTA, AND CHIEN AS PRINTED
`PUBLICATIONS. ......................................................................................... 26
`
`A.
`
`Legal Standards for Establishing Printed Publication. ....................... 26
`
`ii
`
`
`
`B.
`
`Petitioner Has Not Met The Standards For Establishing Zhang,
`Gupta and Chien as Printed Publications. .......................................... 27
`
`1.
`2.
`3.
`4.
`
`Petitioner’s Conference Distribution Theory ........................... 28
`Petitioner’s IEEE Xplore Website Theory. .............................. 30
`Petitioner’s Online Library Records Theory. ........................... 32
`Each of Petitioner’s Grounds Therefore Fails. ......................... 35
`
`IX. PATENT OWNER’S CLAIM CONSTRUCTIONS .................................... 36
`
`A. Agreed Terms ...................................................................................... 36
`
`B.
`
`Terms to be construed. ........................................................................ 37
`
`1.
`
`2.
`
`“retrieves only computational data required by the
`algorithm from a second memory… and places the
`retrieved computational data in the first memory” ................... 37
`“read and write only data required for computations by
`the algorithm between the data prefetch unit and the
`common memory” .................................................................... 38
`
`X.
`
`PETITIONER HAS FAILED TO DEMONSTRATE A
`REASONABLE LIKELIHOOD OF PREVAILING AS TO ANY
`CHALLENGED CLAIM. ............................................................................. 38
`
`A. Ground 1: Claims 1-2, 4-8 And 13-19 Are Not Obvious Over
`Zhang And Gupta. ............................................................................... 38
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`The combination does not render obvious a
`“reconfigurable processor that instantiates an algorithm
`as hardware.” ............................................................................ 39
`The combination does not render obvious a “data prefetch
`unit.” ......................................................................................... 42
`The combination does not render obvious a data prefetch
`unit “wherein the data prefetch unit retrieves only
`computational data required by the algorithm.” ....................... 43
`The combination does not render obvious a first memory
`and a data prefetch unit “wherein at least the first memory
`and data prefetch unit are configured to conform to needs
`of the algorithm.” ...................................................................... 46
`The combination does not render obvious a data prefetch
`unit “configured to match format and location of data in
`the second memory.” ................................................................ 51
`
`iii
`
`
`
`6.
`
`7.
`
`8.
`
`The combination does not render obvious a memory
`controller that “transmits only portions of data desired by
`the data prefetch unit and discards other portions of data
`prior to transmission of the data to the data prefetch unit.” ..... 51
`The combination does not render obvious a
`“reconfigurable processor” as required by claim 13. ............... 52
`The combination does not render obvious a
`reconfigurable processor “wherein the computational unit
`and the data access unit, and the data prefetch unit are
`configured to conform to needs of an algorithm
`implemented on the computational unit and transfer only
`data necessary for computations by the computational
`unit” as required by claim 13. ................................................... 53
`
`B.
`
`Ground 2: Claims 3 And 9-12 Are Not Obvious Over Zhang,
`Gupta, And Chien. .............................................................................. 54
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`The combination does not render obvious a
`“reconfigurable processor[] that can instantiate an
`algorithm as hardware.” ............................................................ 54
`The combination does not render obvious a “data prefetch
`unit.” ......................................................................................... 55
`The combination does not render obvious “a data prefetch
`unit to read and write only data required for computations
`by the algorithm.” ..................................................................... 56
`The combination does not render obvious a data prefetch
`unit configured to “match format and location of data in
`the common memory.” ............................................................. 57
`The combination does not render obvious a memory
`controller that “transmits to the prefetch unit only data
`desired by the data prefetch unit as required by the
`algorithm.” ................................................................................ 57
`The combination does not render obvious a
`“reconfigurable processor [that] also includes a
`computational unit” as required by claim 11. ........................... 58
`
`XI. SECONDARY CONSIDERATIONS OF NON-OBVIOUSNESS .............. 58
`
`XII. CONCLUSION ............................................................................................. 61
`
`
`
`
`
`
`iv
`
`
`
`CASES:
`
`TABLE OF AUTHORITIES
`
`Acceleration Bay, LLC v. Activision Blizzard, Inc.,
`908 F.3d 765 (Fed. Cir. 2018) ..................................................................... 27, 28, 31
`
`Acme Scale Co. v. LTS Scale Co., LLC,
`615 F. App’x 673 (Fed. Cir. 2015) .......................................................................... 21
`
`Continental Intermodal Group - Trucking LLC v. Sand Revolution LLC,
`No. 7-18-cv-00147-ADA (W.D. Tex.) ....................................................................... 3
`
`Cuozzo Speed Techs. v. Lee,
`136 S. Ct. 2131 ............................................................................................................. 2
`
`Elan Pharm., Inc. v. Mayo Found. For Med. Educ. & Research,
`346 F.3d 1051 (Fed. Cir. 2003) ................................................................................ 21
`
`Intelligent Bio-Systems, Inc. v. Illumina Cambridge Ltd.,
`821 F.3d 1359 (Fed. Cir. 2016) ................................................................................ 35
`
`Jazz Pharm., Inc. v. Amneal Pharm., LLC,
`895 F.3d 1347 (Fed. Cir. 2018) ................................................................................ 26
`
`Kerr Machine Co. d/b/a Kerr Pumps v. Vulcan Industrial Holdings, LLC,
`6-20-cv-00200-ADA (W.D. Tex.) ....................................................................... 3, 4, 5
`
`MultiMedia Content Mgmt LLC v. Dish Network L.L.C.,
`6-18-cv-00207-ADA (W.D. Tex.) ............................................................................... 3
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) (en banc) ............................................................. 36
`
`Samsung Elec. Co. v. Infobridge Pte. Ltd.,
`929 F.3d 1363 (Fed. Cir. 2019) ......................................................................... passim
`
`SRI Int’l, Inc. v. Internet Sec. Sys., Inc.,
`511 F.3d 1186 (Fed. Cir. 2008) ............................................................................... 26
`
`Solas OLED v. Dell Techs. Inc.,
`6-19-cv-00514-ADA, Text Order dated Jun. 23, 2020 (W.D. Tex.) ....................... 3
`
`Solas OLED v. Dell Techs. Inc.,
`6-19-cv-00515-ADA, Text Order dated Jun. 23, 2020 (W.D. Tex.) ....................... 3
`
`v
`
`
`
`Voter Verified, Inc. v. Premier Election Solutions, Inc.,
`698 F.3d 1374 (Fed. Cir. 2012) ................................................................................ 31
`
`ADMINISTRATIVE ORDERS:
`
`Apple Inc. v. Fintiv, Inc.,
`Case IPR2020-00019, Paper 11 (PTAB Mar. 20, 2020) ............................... passim
`
`Apple Inc. v. Parus Holdings, Inc.,
`Case IPR2020-00686, Paper 9 (PTAB Sept. 23, 2020) ......................................... 5
`
`General Plastic Indus. Co., Ltd. v. Canon Kabushiki Kaisha,
`Case IPR2016–01357, Paper 19 (PTAB Sept. 6, 2017) ......................................... 8
`
`Hulu, LLC v. Sound View Innovations, LLC,
`Case IPR2018-01039, Paper 29 (PTAB POP Dec. 20, 2019) ................. 26, 34, 35
`
`Mylan Pharms., Inc. v. Bayer Intellectual Property GMBH,
`Case IPR2018-01143, Paper 13 (PTAB Dec. 3, 2018) .............................................. 8
`
`NetApp, Inc. v. Realtime Data LLC,
`Case IPR2017-01195, Paper 9 (PTAB Oct. 12, 2017) ........................................... 8
`
`NHK Spring Co., Ltd v. Intri-Plex Techs., Inc.,
`Case IPR2018-00752, Paper 8 (PTAB Sept. 12, 2018) ............................................. 8
`
`Philip Morris Prod., S.A. v. RAI Strategic Holdings, Inc.,
`Case IPR2020-00921, Paper 9 (PTAB Nov. 16, 2020) ......................................... 3
`
`STATUTES:
`
`35 U.S.C. § 103 ........................................................................................................... 1, 35
`
`35 U.S.C. § 314 ........................................................................................................ 2, 9, 61
`
`35 U.S.C. § 316 .................................................................................................................. 5
`
`REGULATIONS:
`
`37 C.F.R. § 42.100(b) ....................................................................................................... 6
`
`vi
`
`
`
`
`
`I.
`
`INTRODUCTION
`
`Patent Owner FG SRC LLC (hereinafter “SRC” or “Patent Owner”)
`
`respectfully submits this Patent Owner Preliminary Response to the Petition for Inter
`
`Partes Review dated August 10, 2020 (“Petition”) of U.S. Patent No. 7,149,867 (Ex.
`
`1001, “’867 patent”) filed by Intel Corporation (“Intel” or “Petitioner”). Petitioner
`
`asserts that claims 1-19 of the ’867 patent are unpatentable on two grounds based
`
`solely on 35 U.S.C. § 103:
`
`Ground 1 – Claims 1-2, 4-8, 13-19 are unpatentable as obvious over
`
`Zhang in view of Gupta as understood by one of ordinary skill in the art.
`
`Ground 2 – Claims 3 and 9-12 are unpatentable as obvious over Zhang in
`
`view of Gupta and Chien as understood by one of ordinary skill in the art.
`
`This Preliminary Response is timely filed based on the Board’s November 10,
`
`2020 Order. See Paper 8.
`
`II. RELATED PROCEEDINGS
`
`Related Proceedings are listed in Paper 1, at 2.
`
`III. SRC BACKGROUND
`
`Patent Owner’s predecessor, SRC Computers was founded in 1996 by Jon
`
`Huppenthal, Jim Guzy, and Seymore Robert Cray (hence SRC). Ex. 2005, ¶¶ 36-
`
`37; Ex. 2002. Mr. Cray—widely considered to be the father of supercomputing—
`
`designed a series of computers that for decades were the fastest in the world. Ex.
`
`2002; Ex. 2005, ¶ 40. SRC’s patent portfolio is a direct result of this work.
`
`1
`
`
`
`IV. THE BOARD SHOULD DENY INSTITUTION UNDER § 314(a).
`
`The Board should exercise its discretion under 35 U.S.C. § 314(a) to deny
`
`Intel’s Petition. Petitioner concedes that all the claims that are at issue in the WDTX
`
`Action are also at issue here. Paper 1, at 7; Exs. 2004, 2005. Accordingly, this
`
`proceeding would be duplicative of the related district court case involving the same
`
`parties and the same patent, and that case will outpace a final written decision in this
`
`proceeding.
`
`Section 314(a) provides the Director with discretion to deny a petition. See
`
`35 U.S.C. § 314(a); Cuozzo Speed Techs. v. Lee, 136 S. Ct. 2131, 2140 (“[T]he
`
`agency’s decision to deny a petition is a matter committed to the Patent Office’s
`
`discretion.”). When considering whether to exercise its discretion not to institute,
`
`the circumstances surrounding proceedings “related to the same patent, either at the
`
`Office, in the district courts, or the ITC” are considered. See Consolidated Trial
`
`Practice Guide (November 2019) at 58. Several factors inform that consideration:
`
`1. whether the court granted a stay or evidence exists that one may be granted
`if a proceeding is instituted;
`2. proximity of the court’s trial date to the Board’s projected statutory
`deadline for a final written decision;
`3. investment in the parallel proceeding by the court and the parties;
`4. overlap between issues raised in the petition and in the parallel
`proceeding;
`5. whether the petitioner and the defendant in the parallel proceeding are the
`same party; and
`6. other circumstances that impact the Board’s exercise of discretion,
`including the merits.
`
`2
`
`
`
`Apple Inc. v. Fintiv, Inc., IPR2020-00019, Paper 11, at 5-6 (PTAB Mar. 20, 2020)
`
`(precedential); Philip Morris Prod., S.A. v. RAI Strategic Holdings, Inc., IPR2020-
`
`00921, Paper 9, at 14-15 (PTAB Nov. 16, 2020). The Board must then take “a
`
`holistic view of whether efficiency and integrity of the system are best served by
`
`denying or instituting review.” Fintiv, IPR2020-0019, Paper 11, at 6.
`
`Applying the Fintiv analysis to the facts in this instance, Intel’s Petition must
`
`be denied.
`
`A. All of the Fintiv Factors Favor Denial of Institution.
`
`Regarding Fintiv Factor 1, Intel has not yet requested a stay and failed to
`
`provide any evidence demonstrating that the WDTX Action would be stayed if this
`
`IPR is instituted. Paper 1, at 7. Instead, all available evidence indicates that Judge
`
`Albright would deny such a stay even if trial were instituted. Judge Albright
`
`routinely and consistently denies such stays and has stated his belief in the Seventh
`
`Amendment right to a jury trial as a strong reason for doing so. Ex. 2024,
`
`Continental Intermodal Group - Trucking LLC v. Sand Revolution LLC (denying
`
`motion to stay pending instituted IPR because “[t]he Court strongly believes [in] the
`
`Seventh Amendment.”); Ex. 2016, Kerr Machine Co. d/b/a Kerr Pumps v. Vulcan
`
`Industrial Holdings, LLC (denying motion to stay pending post-grant review); Ex.
`
`2017, MultiMedia Content Mgmt LLC v. Dish Network L.L.C. (denying motion to
`
`stay pending IPR); Ex. 2018 and 2025, Solas OLED v. Dell Techs. Inc. (same).
`
`3
`
`
`
`The instant matter is factually the same as Kerr Machine. There, plaintiff Kerr
`
`filed a single patent infringement suit on March 19, 2020. Ex. 2019, at 4. Defendant
`
`Vulcan filed its petition for PGR challenging all asserted claims on May 20, 2020,
`
`about two months later. Id., at 6. On July 31, 2020, Vulcan moved to stay the
`
`litigation pending the PGR petition, which has a statutory final written decision date
`
`of December 11, 2021. Id., at 12, 14. Trial was set for August 2, 2021, about four
`
`months before the final written decision would issue. Ex. 2020. Within three days
`
`of the filing of the motion, Judge Albright denied it without a hearing or any
`
`opposition briefing, holding:
`
`The PTAB has not instituted the PGR. … Even if the PTAB institutes,
`the Court anticipates that the trial date will occur before the PGR's
`final written decision. ... Allowing this case to proceed to completion
`will provide a more complete resolution of the issues including
`infringement, all potential grounds of invalidity, and damages. … The
`Court believes in the Seventh Amendment. … Plaintiff opposes the
`stay.
`
`Ex. 2016 (emphasis added).
`
`As in Kerr, trial in the underlying litigation is set several months before a final
`
`written decision would issue. As in Kerr, allowing the case to proceed to completion
`
`will “provide a more complete resolution of the issues including infringement, all
`
`potential grounds of invalidity, and damages.” Id. Thus, the Court’s order in Kerr,
`
`a case factually indistinguishable from the instant case, is substantive evidence that
`
`the Court will not grant a stay even if the Board were to institute.
`
`4
`
`
`
`Because this matter is factually identical to that of Kerr, it is wholly
`
`distinguishable from Apple Inc. v. Parus Holdings, Inc., IPR2020-00686, Paper 9
`
`(PTAB Sept. 23, 2020), a case in which the Board held:
`
`Patent Owner contends that it presents “specific evidence” of how the
`Texas court would rule…. However, all Patent Owner offers is
`conjecture based on how the Texas court has ruled in different cases
`based on different facts.
`
`Id. at 10 (emphasis added). The present matter is “not based on different facts” than
`
`Kerr.
`
`Thus, this factor weighs against institution. Intel has been unable to show that
`
`evidence exists that a stay may be granted if a proceeding is instituted. The fact that
`
`discovery is stayed pending claim construction is irrelevant as the same was true in
`
`Kerr. Ex. 2021, at 2.
`
`Regarding Fintiv Factor 2, Intel’s Petition misleadingly states that “no trial
`
`date has been set.” A week before Intel filed its petition Judge Albright’s clerk
`
`emailed the parties, stating “the Court will set the trial date for November 8, 2021.”
`
`Ex. 2022. Based on the Notice According Filing Date, the Final Written Decision
`
`would not be due until at least February 17, 2022. 35 U.S.C. § 316(a). The Court
`
`would thus resolve the relevant validity issues first. Therefore, this factor favors
`
`denying institution. Philip Morris, IPR2020-00921, Paper 9, at 16; see also Fintiv,
`
`IPR2020-00019, Paper 15, 12-13 (PTAB May 13, 2020) (this factor ““weighs
`
`somewhat in favor of discretionary denial” because trial was set two months before
`
`the final written decision).
`
`5
`
`
`
`Regarding Fintiv Factor 3, Intel has already answered the complaint, the
`
`parties have already exchanged infringement and invalidity contentions, technical
`
`and financial documents have been produced, claim construction proceedings are
`
`underway and a Markman hearing is scheduled for March 5, 2021. Ex. 2023. The
`
`claim construction standard is the same. Consolidated Trial Practice Guide at 70;
`
`37 C.F.R. § 42.100(b). Thus, the Board will be duplicating the same claim
`
`construction efforts. Moreover, like the petitioner in Fintiv, Intel filed its petition
`
`between the initial case management proceedings, and the Markman hearing.
`
`IPR2020-00019, Paper 15, at 9. Thus, this factor favors denial. See id., at 13-14.
`
`Regarding Fintiv Factor 4, Petitioner’s narrow stipulation does not eliminate
`
`the possibility that substantially similar art and arguments will be raised by Petitioner
`
`in the WDTX Action. See Philip Morris, IPR2020-00921, Paper 9, at 19
`
`(considering Petitioner stipulation that “it will not pursue any IPR grounds in the
`
`EDVA case if the Board institutes”). Petitioner and its expert argue that the three
`
`references are related to the “same project,” and it has not committed to drop its
`
`reliance on that project. See, e.g. Ex. 1006, ¶ 122. This factor therefore favors
`
`denying institution. Fintiv, IPR2020-00019, Paper 15, at 15.
`
`Regarding Fintiv Factor 5, Petitioner concedes that it is the sole defendant in
`
`the WDTX Action. Paper 1, at 2. This factor therefore favors denying institution.
`
`Fintiv, IPR2020-00019, Paper 15, at 15; Philip Morris, IPR2020-00921, Paper 9, at
`
`20.
`
`6
`
`
`
`Regarding Fintiv Factor 6, the merits of Intel’s petition are too weak to
`
`overcome the remaining factors. For example, Petitioner has failed to establish with
`
`particularity that any of the asserted non-patent references are printed publications
`
`that were publicly available as to the critical date. See Section VIII., infra. Because
`
`these are the only references cited, their failure to qualify as prior art dooms the
`
`petition. This factor therefore favors denial. Fintiv, IPR2020-00019, Paper 15, at
`
`15-17.
`
`Finally, all arguments Intel presents have recently been rejected by the Board.
`
`In Philip Morris, the petitioner argued that the Board should not exercise its
`
`discretion not to institute because a stay might be requested and granted, the trial
`
`date was not set with certainty, the district court proceedings were at an early stage
`
`with little activity apart from filing of claim construction briefs, the petitioner
`
`provided a narrow stipulation as to the issues that it would not pursue in the district
`
`court if the IPR was instituted, and the Board found the merits of the petition to be
`
`strong. Id. These are the same arguments that Petitioner is presenting here. See
`
`Paper 1, at 6-7.
`
`Thus, all of the Fintiv factors favor discretionary denial in this case.
`
`B.
`
`Efficiency and Integrity of the System Are Best Served by
`Denying Institution.
`
`“In general, an anticipated district court trial date substantially in advance of a
`
`projected statutory deadline for the Board to issue a final decision increases the likelihood
`
`7
`
`
`
`that the district court will reach a determination of the parties’ dispute as to the validity of
`
`the challenged claims before the Board will. Under such circumstances, the application
`
`of Office policy has often resulted in the denial of institution.” Philip Morris, IPR2020-
`
`00921, Paper 9, at 28 (citations omitted).
`
`Here, there are no factors that favor institution. Even if the merits of the asserted
`
`grounds were to favor institution, “the efficiency and integrity of the system … taking into
`
`account the consistent application of Office policy” requires that institution be denied. Id.,
`
`at 28-29; see also NHK Spring Co., Ltd v. Intri-Plex Techs., Inc., Case IPR2018-00752,
`
`Paper 8, at 19-20 (PTAB Sept. 12, 2018); NetApp, Inc. v. Realtime Data LLC, Case
`
`IPR2017-01195, Paper 9, at 12-13 (PTAB Oct. 12, 2017).
`
`Finally, the AIA was designed to “limit unnecessary and counterproductive
`
`litigation costs.” H.R. Rep. No. 112-98, pt. 1, at 40 (2011), 2011 U.S.C.C.A.N. 69,
`
`69; Consolidated Trial Practice Guide at 56. Given the substantial overlap between
`
`the district court action and this IPR, this proceeding is not an effective and
`
`appropriate use of the Board’s resources and is contrary to the AIA’s overall goal to
`
`“make the patent system more efficient by the use of post-grant review proceedings.”
`
`See General Plastic Industrial Co., Ltd. v. Canon Kabushiki Kaisha, Case IPR2016-
`
`01357, Paper 19, at 16-17 (PTAB Sept. 6, 2017) (precedential). IPRs are not a tool
`
`to delay prosecution for infringement. Thus, institution is not justified. NHK Spring,
`
`Paper 8, at 19-20; NetApp, Paper 8, at 12-13; see also Mylan Pharms., Inc. v. Bayer
`
`8
`
`
`
`Intellectual Property GMBH, Case IPR2018-01143, Paper 13, at 12-14 (PTAB Dec.
`
`3, 2018).
`
`Accordingly, the Board should deny institution under § 314(a).
`
`V. TECHNOLOGY BACKGROUND
`
`A. Reconfigurable Processors and FPGAs.
`
`The ’867 patent relates to the use of reconfigurable processors, such as those
`
`made using FPGAs. Ex. 1001, 1:16-24, 5:26-29. An FPGA is a reprogrammable
`
`integrated circuit that contains an array of programmable logic blocks and memory
`
`elements connected via programmable interconnect. Ex. 2001, ¶ 54, Ex. 2010, ¶ 14.
`
`A user can program an FPGA to perform a specific function by configuring the logic
`
`blocks and interconnect. This enables the user to create a hardware accelerated
`
`implementation of an algorithm by programming the FPGA in a manner that
`
`efficiently executes the algorithm. Id. In other words, with a reconfigurable
`
`processor such as an FPGA, the hardware can adapt to the algorithm. An FPGA is
`
`configured by loading a file called a bitstream into the FPGA. Id. Reconfigurable
`
`processors instantiate hardware to directly perform the required task, and do not rely
`
`on “instructions” the way a general-purpose CPU does. For this reason, the term
`
`“instruction” does not have a plain and ordinary meaning with respect to
`
`reconfigurable processors. Id.
`
`In contrast, a CPU executes an algorithm by performing a sequence of
`
`instructions that implement the algorithm. Ex. 2001, ¶ 55, Ex. 2010, ¶ 15. A
`
`9
`
`
`
`different algorithm can be implemented on the CPU by changing the instruction
`
`sequence. Id. The CPU is flexible; it can implement almost any algorithm. Id. But
`
`because the CPU hardware is fixed, it cannot be customized towards the needs of
`
`any particular algorithm like an FPGA. Id. These customizations allow FPGA
`
`implementations to be orders of magnitude more efficient than implementing that
`
`algorithm as software on a CPU. Id.
`
`B. Memory Hierarchies
`
`Computing systems including CPUs and FPGAs typically employ a memory
`
`hierarchy, which combines different types of memories in an attempt to ensure that
`
`data required for computation is available as needed. Ex. 2001, ¶ 125, Ex. 2010, ¶
`
`18. There is a general trade-off between memory size and bandwidth. Id. In general,
`
`larger memories have lower bandwidth, i.e., they can store a lot of data but the rate
`
`at which they can transfer this data (bits/second) is low. Id. Smaller memories have
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`much higher bandwidth. Id. Thus, memory systems commonly use hierarchies of
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`progressively faster (higher bandwidth) but smaller size. Id.
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`The ’867 patent discusses memory throughout the claims and specification.
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`For example, Claim 1 recites moving data from a “second memory” to a “first
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`memory” within a memory hierarchy. This is akin to the concepts described above,
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`in which data can be moved from slower, larger memory (e.g., a second memory) to
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`quicker, smaller memory (e.g., a first memory). Ex. 2001, ¶ 127, Ex. 2010, ¶¶ 20-
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`21.
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`10
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`
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`The invention of the ’867 patent specifically “relates to implementing explicit
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`memory hierarchies in reconfigurable processors that make efficient use of off-
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`board, on-board, on-chip storage and available algorithm locality. These explicit
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`memory hierarchies avoid many of the tradeoffs and complexities found in the
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`traditional [implicit] memory hierarchies of microprocessors.” Ex. 1001, 1:18-24.
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`Implicit memory devices encompass a family of processing elements that are
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`all implicitly controlled and typically are made up of fixed logic that is not altered
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`by the user. These devices execute software-directed instructions on a step-by-step
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`basis in fixed logic having predetermined interconnections and functionality. Ex.
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`2001, ¶ 121.
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`Explicit memory devices, on the other hand, are Direct Execution Logic
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`(DEL) and comprise a family of components that is explicitly controlled and is
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`typically reconfigurable. This set of elements enables a program to establish an
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`optimized interconnection among the selected functional units in order to implement
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`a desired computational, pre-fetch and/or data access functionality for maximizing
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`the parallelism inherent in the particular code. Id., ¶ 29.
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`C.
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`Prefetching
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`A simple (unoptimized) memory system would have a processor that requests
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`data when it is required for computation. Ex. 2001, ¶ 56, Ex. 2010, ¶ 22. This can
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`be problematic especially if the data resides in off-chip memory, which has a large
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`latency or large number of cycles (e.g., hundreds or more) to retrieve the data. Id.
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`11
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`
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`This requires the computational unit to stall or wait while the data is being loaded.
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`Id. This problem is addressed by a “prefetch unit”, which fetches needed data before
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`it is needed by the processor.
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`Prefetching initiates a request for data before that data is required. In an ideal
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`case, the prefetch data arrives no later than when it is required. Ex. 2001, ¶ 56, Ex.
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`2010, ¶ 26. Generally speaking, there are two ways of prefetching data: 1)
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`dynamically and 2) statically. Id. Dynamic prefetching attempts to guess what
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`future data is required by looking at past data access requests. Id. For example, a
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`dynamic prefetch unit may see a request for some data and prefetch the next N data
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`elements located spatially nearby to the initial data (with the hopes that the algorithm
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`will request this data in the future). Id. Static prefetching techniques insert explicit
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`prefetch instructions into the computer system, e.g., a compiler will analyze the
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`algorithm and insert prefetch data fetches before the data is computed upon. Id.
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`There are many types of prefetching techniques, and customizing the prefetching
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`technique to the algorithm can provide significant overall performance benefits. Id.
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`VI. THE ’867 PATENT
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`The field of the invention of the ’867 patent is reconfigurable hardware. Ex.
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`1001, 1:16-18. “More specifically, the invention relates to implementing explicit
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`memory hierarchies in reconfigurable processors that make efficient use of off-
`
`board, on-board, on-chip storage and available algorithm locality. These explicit
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`12
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`
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`memory hierarchies avoid many of the tradeoffs and complexities found in the
`
`traditional [implicit] memory hierarchies of microprocessors.”
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`A. The Invention Of The ’867 Patent.
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`To improve upon the limitations of the prior art, the ’867 patent discloses a
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`flexible yet efficient fully reconfigurable hardware system consisting of
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`computational units, data prefetch units, data access units, and memory. Ex. 1001,
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`Abstract. The parts are fully reconfigurable, meaning they can be configured as
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`needed for a particular algorithm. Id. Once properly configured, the data prefetch
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`unit retrieves data from a memory and supplies the data through a data access unit
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`to the computational units in a way optimally adapted to the needs of the particular
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`algorithm. Id.
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`Computer programs are a collection of algorithms that interact to implement
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`desired functionality. Ex. 1001, 6:32-34. In the prior art, use of static computing
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`hardware resources (e.g., a conventional microprocessor), required the computer
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`program to be adapted to run on the particular hardware platform. Ex. 1001, 6:40-
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`42. “In this manner, the computer program is adapted to conform to the limitations
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`of the static hardware platform.” Id., 6:42-43.
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`The ’867 patent effectively flips the paradigm and allows software written in
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`a human readable high-level language to be compiled into direct execution logic
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`(DEL). The reconfigurable processor is then configured with the DEL. Ex. 1001,
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`6:52-54. “In this manner, the hardware resources are essentially adapted to conform
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`13
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`
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`to the program rather than the program being adapted to conform to the hardware
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`resources.” Ex. 1001, 6:54-57.
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`Figure 1 represents a reconfigurable processor (RP):
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`
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`Ex. 1001, Fig. 1.
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`The ’867 patent further recognized that “[h]igh memory bandwidth efficiency
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`is achieved when only data required for computation is moved within the memory
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`hierarchy.”