UNITED STATES PATENT AND TRADEMARK OFFICE
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`Paper No. 44
`Filed: October 22, 2021
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`
`
`INTEL CORPORATION and XILINX, INC.1,
`Petitioners,
`v.
`FG SRC LLC,
`Patent Owner.
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`
`
`IPR2020-01449
`Patent No. 7,149,867
`
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`
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`
`
`PATENT OWNER’S SUR-REPLY TO
`PETITIONERS’ REPLY TO PATENT OWNER RESPONSE
`
`
`1 Xilinx, Inc. filed a petition and motion for joinder in IPR2021-00633 which were
`granted and, therefore, has been joined as a petitioner in this proceeding.
`1
`
`
`
`
`
`
`
`
`
`
`Paper No. 44
`Filed: October 22, 2021
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`
`
`INTEL CORPORATION and XILINX, INC.1,
`Petitioners,
`v.
`FG SRC LLC,
`Patent Owner.
`
`
`
`
`
`
`
`
`
`
`
`IPR2020-01449
`Patent No. 7,149,867
`
`
`
`
`
`
`
`
`
`PATENT OWNER’S SUR-REPLY TO
`PETITIONERS’ REPLY TO PATENT OWNER RESPONSE
`
`
`1 Xilinx, Inc. filed a petition and motion for joinder in IPR2021-00633 which were
`granted and, therefore, has been joined as a petitioner in this proceeding.
`1
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`
`
`Exhibit No.
`2001
`2002
`2003
`
`2004
`
`2005
`
`2006
`
`2007
`2008
`
`2009
`2009-1
`
`2009-2
`
`2010
`
`2011
`
`2012
`
`2013
`
`LIST OF EXHIBITS
`Descriptions
`Declaration of Dr. Vojin Oklobdzija
`Cray, Britannica Online Encyclopedia
`Declaration of Brandon Freeman dated 10/25/18
`SRC Labs LLC and Saint Regis Mohawk Tribe v. Microsoft
`Corporation, No. 2:18-cv-00321-JLR, Dkt. 125 (W.D. Wash. Oct.
`25, 2018)
`Plaintiff’s Original Complaint For Patent Infringement in FG SRC
`LLC v. Intel Corp., No. 6:20-cv-00315-ADA (W.D. Texas), filed
`April 24, 2020
`Plaintiff’s First Amended Complaint For Patent Infringement in
`FG SRC LLC v. Intel Corp., No. 6:20-cv-00315-ADA (W.D.
`Texas), filed April 24, 2020
`Declaration of Mark Wollgast dated 09/10/18
`Xilinx, Inc. v. Saint Regis Mohawk Tribe, IPR2018-0195
`COTS Journal, UAVs Lead Push for Embedded Supercomputing
`Press Release: SRC Computers Chosen by Lockheed Martin for
`U.S. Army Program
`Declaration of Henning Schmidt
`Declaration of Henning Schmidt, Exhibit A, IEEE Xplore:
`Advanced Search
`Declaration of Henning Schmidt, Exhibit B, IEEE Xplore:
`Advanced Search Results
`Declaration Of Ryan Kastner, Ph.D. In Support Of FG SRC
`LLC’s Opening Claim Construction Brief in FG SRC LLC v. Intel
`Corp., No. 6:20-cv-00315-ADA (W.D. Texas), filed April 24,
`2020
`Peter McMahon, High Performance Reconfigurable Computing for
`Science and Engineering Applications (Thesis Oct. 2006).
`Caliga, Delivering Acceleration: The Potential for Increased HPC
`Application Performance Using Reconfigurable Logic
`D. A. Buell, D. Caliga, J. P. Davis, G. Quan, “The DARPA
`boolean equation benchmark on a reconfigurable computer,”
`Proceedings of the Military and Aerospace Programmable Logic
`Devices (MAPLD) Conference, Washington, DC, 8-10 September
`2004
`
`ii
`
`
`
`
`
`
`Exhibit No.
`2014
`
`2015
`
`2016
`
`2017
`
`2018
`
`2019
`
`2020
`
`2021
`
`2022
`2023
`
`2024
`
`2025
`
`2026
`2027
`
`2028
`
`2029
`2030
`
`Descriptions
`El-Araby, The Promise of High-Performance Reconfigurable
`Computing
`FG SRC LLC’s Opening Claim Construction Brief in FG SRC
`LLC v. Intel Corp., No. 6:20-cv-00315-ADA (W.D. Texas),
`filed April 24, 2020
`Kerr Machine Co. d/b/a Kerr Pumps v. Vulcan Industrial
`Holdings, LLC, No. 6:20-cv-00200, Text Order dated Aug. 2, 2020
`(W.D. Tex.)
`MultiMedia Content Mgmt LLC v. Dish Network L.L.C., No. 6:18-
`cv-00207, Dkt. 73 (W.D. Tex.)
`Solas OLED v. Dell Techs. Inc., No. 6:19-cv-00514, Text Order
`dated June 23, 2020
`Kerr Machine Co. v. Vulcan Indus. Holdings, LLC, No. 6:20-cv-
`200, Dkt. 28 (W.D. Tex. July 31, 2020)
`Kerr Machine Co. v. Vulcan Indus. Holdings, LLC, No. 6:20-cv-
`200, Dkt. 24 (W.D. Tex. June 14, 2020)
`Kerr Machine Co. v. Vulcan Indus. Holdings, LLC, No. 6:20-cv-
`200, Dkt. 12 (W.D. Tex., June 14, 2020)
`Email from J. Yi to Counsel (Aug. 3, 2020)
`FG SRC LLC v. Intel Corp., No. 1:20-cv-00834, Dkt. 48 (W.D.
`Tex. Nov. 23, 2020) (Amended Schedule)
`Continental Intermodal Group - Trucking LLC v. Sand Revolution
`LLC, No. 7:18-cv-00147, Text Order dated July 22, 2020 (W.D.
`Tex.)
`Solas OLED v. Dell Techs. Inc., No. 6:19-cv-00515, Text Order
`dated Jun. 23, 2020
`2019-07-11 - DirectStream MSFT - Huppenthal Declaration
`Declaration of William Mangione-Smith, Ph.D., In Support of FG
`SRC LLC’s Motion to Amend
`Declaration of Dr. William Mangione-Smith in support of Patent
`Owner Response
`Deposition Transcript of Dr. Stanley Shanfield
`Declaration of William Mangione-Smith, Ph.D., In Support of FG
`SRC LLC’s Revised Motion to Amend
`
`iii
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`
`
`I.
`II.
`
`B.
`
`E.
`
`F.
`
`TABLE OF CONTENTS
`INTRODUCTION ........................................................................................... 1
`THE INSTITUTED COMBINATION OF ZHANG, GUPTA, AND
`CHIEN DOES NOT RENDER THE CHALLENGED CLAIMS
`OBVIOUS. ...................................................................................................... 1
`A.
`The instituted combination of Zhang, Gupta, and Chien teaches
`away from the ’867 Patent. ................................................................... 1
`The combination does not render obvious a “reconfigurable
`processor that instantiates an algorithm as hardware.” ......................... 2
`The combination does not render obvious a “data prefetch unit.” ....... 5
`The combination does not render obvious a data prefetch unit
`“wherein the data prefetch unit retrieves only computational
`data required by the algorithm.” ........................................................... 7
`The combination does not render obvious a first memory and a
`data prefetch unit “wherein at least the first memory and data
`prefetch unit are configured to conform to needs of the
`algorithm.” ............................................................................................ 9
`The combination does not render obvious a data prefetch unit
`“configured to match format and location of data in the second
`memory.” ............................................................................................. 10
`III. CONCLUSION ............................................................................................. 12
`
`
`C.
`D.
`
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`
`iv
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`
`
`CASES
`
`TABLE OF AUTHORITIES
`
`In re Oelrich,
`666 F.2d 578 (C.C.P.A. 1981) ....................................................................... 11
`In re Rijckaert,
`9 F.3d 1531 (Fed.Cir.1993) ........................................................................... 11
`PAR Pharm., Inc. v. TWI Pharms., Inc.,
`773 F.3d 1186 (Fed. Cir. 2014) ..................................................................... 11
`
`
`
`v
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`
`
`I.
`
`INTRODUCTION
`Patent Owner FG SRC LLC (hereinafter “SRC” or “Patent Owner”)
`
`respectfully submits this Sur-Reply to Petitioners’ Reply (Paper 40, “Reply”) to
`
`Patent Owner’s Response (Paper 34, “Response”) to the Petition for Inter Partes
`
`Review dated August 10, 2020 (Paper 1, “Petition”) of U.S. Patent No. 7,149,867
`
`(Ex. 1001, “’867 Patent”) filed by Intel Corporation (“Intel” or “Petitioner”).
`
`Petitioners’ Reply focuses much on aspects in which Patent Owner’s response
`
`is similar to its preliminary response, but little on what has been added to address
`
`the questions raised by the institution decision. Patent Owner reiterates and clarifies
`
`these points here.
`
`II. THE INSTITUTED COMBINATION OF ZHANG, GUPTA, AND
`CHIEN DOES NOT RENDER THE CHALLENGED CLAIMS OBVIOUS.
`The instituted combination of Zhang, Gupta, and Chien does not properly
`
`disclose or suggest the claimed inventions of the ’867 Patent.
`
`A. The instituted combination of Zhang, Gupta, and Chien teaches
`away from the ’867 Patent.
`The institution decision argues that the instituted combination (Zhang, Gupta,
`
`and Chien) may merely fail to disclose the invention, as opposed to teach away from
`
`it. Paper 13 at 45. The institution decision further disagrees with Patent Owner’s
`
`argument that “Zhang’s statement that ‘the entire application remains in software’
`
`evidences that Zhang’s architecture does not instantiate an algorithm as hardware,”
`
`because Zhang does not explicitly state that “all algorithms that comprise the
`1
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`
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`
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`application” also remain in software. Paper 13 at 49. Patent Owner directly
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`addressed the Board’s concerns in its Response. Paper 34 at 34, 35. Petitioners do
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`not respond to this supplemental information. Compare id. with Paper 40, 8-9.
`
`Specifically, Dr. Mangione-Smith confirms that Zhang is not merely silent on
`
`the technology of the ’867 Patent, but actually teaches away from implementing any
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`part of the application itself or any of the algorithms that comprise the application
`
`in hardware. EX. 2028, ¶70. “Zhang specifically indicates that [all of] the
`
`algorithms that comprise the application discussed in Zhang also ‘remain in
`
`software’ and are executed by the conventional CPU disclosed in Zhang.” It is
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`counterintuitive and indeed nonsensical to assume—without supporting disclosure
`
`in Zhang—that any algorithm that is part of the application would be “instantiated
`
`as hardware” while “the entire application remains in software” as Zhang explicitly
`
`discloses. Id. The hardware adaptations taught in Zhang are transparent to the
`
`application and its algorithms because they are intended to “preserv[e] machine
`
`usability through software.” Id. Notably, Petitioners’ Reply does not address this
`
`fact. Paper 40, 8-9.
`
`The combination does not render obvious a “reconfigurable
`B.
`processor that instantiates an algorithm as hardware.”
`Petitioners rely solely on Zhang for this limitation which, as explained in the
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`prior section, teaches away from implementing any part of the application in
`
`hardware. There is a stark difference between including some reconfigurable
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`2
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`
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`components in a conventional CPU as compared to using reconfigurable hardware
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`to actually “instantiate an algorithm as hardware” as claimed.
`
`In Zhang, the processor running the main application is a conventional CPU,
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`not a reconfigurable processor. Zhang uses programmable logic (FPGA) only to
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`deliver data for use by that conventional CPU. The strongest support in Zhang for
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`Petitioners’ argument that Zhang indeed discloses a reconfigurable processor as per
`
`the ’867 Patent is Zhang’s statement that it proposes “an architecture that integrates
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`small blocks of programmable logic into key elements of a baseline architecture,
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`including processing elements.” Ex. 1003 at 2:43-46. However, the conclusion
`
`drawn by the Petitioners that Zhang’s processing element itself is a reconfigurable
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`processor capable of instantiating an algorithm as hardware is belied by Zhang’s
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`disclosure that the entire application remains in software discussed in the preceding
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`section, which is further supported by Zhang’s diagram indicating that the
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`reconfigurable logic is only used at the periphery of the conventional CPU, as shown
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`in Fig. 2:
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`
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`3
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`
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`Id., Fig. 2 excerpt (emphasis added). Fig. 2 leaves no doubts that the programmable
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`logic is next to—not contained in—the CPU. Zhang thus flatly contradicts the
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`agreed construction of “reconfigurable processor” which requires “a computing
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`device that contains reconfigurable components.” See EX1001 5:26-26. As
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`described, programmable logic is only implemented in small blocks for specific
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`intermediate purposes between components, such as the interface between CPU and
`
`cache, the network interface, or the memory interface. Id. Further, per Dr.
`
`Mangione-Smith, “Zhang specifically indicates that [all of] the algorithms that
`
`comprise the application discussed in Zhang also ‘remain in software’ and are
`
`executed by the conventional CPU disclosed in Zhang.” EX. 2028, ¶70. This
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`architecture is, by definition, incapable of “instantiating an algorithm as hardware.”
`
`Ex. 2028, ¶ 42. In short, Zhang does not disclose a reconfigurable processor because
`
`its CPU hardware is static and cannot instantiate a specific algorithm or application
`
`as claimed by the ’867 Patent.
`
`Even in going so far as to identify the entirety of Zhang’s system as a single
`
`reconfigurable processor, as Petitioners do (Response at 12), fails to solve
`
`Petitioners’ shortcoming because the conventional static CPU at the heart of
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`Petitioners’ “reconfigurable processor” remains capable only of executing its
`
`instruction set and is—by definition of being “static”—incapable of instantiating an
`
`algorithm as hardware.
`
`4
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`
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`Petitioners further blatantly misquotes and misrepresents Zhang as stating
`
`only that the “application remains in software,” and that “nothing about that
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`statement precludes compiling one (or more) of an application’s algorithms and
`
`instantiating it as hardware.” Response at 14. However, Petitioners intentionally
`
`omit that Zhang explicitly requires that “the entire application remains in software.”
`
`Ex. 1003, at 14, col. 1:32-34. It is simply nonsensical to require that the entire
`
`application remain in software—as Zhang does—while also instantiating parts of it
`
`in hardware. Notably, loading software for execution by a conventional processor
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`is not tantamount to instantiating it in reconfigurable hardware, even when certain
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`components of that system are configured to optimize that particular application.
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`Finally, even Petitioners’ statement that this scenario would not be precluded by
`
`Zhang’s disclosure does not equate to a positive teaching of this hypothetical
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`eventuality to a POSITA. Zhang’s definitive disclosure that “the entire application
`
`remains in software” leaves no room for Petitioners’ supposition that “well, maybe
`
`it doesn’t.” Response at 14-15.
`
`C. The combination does not render obvious a “data prefetch unit.”
`The basic idea of prefetching data is to obtain data before it is needed by the
`
`application. Ex. 2028, ¶47. The fact that the data prefetch unit of the ’867 Patent
`
`can operate “prior to, in parallel with, or after” the computational logic does not
`
`support that the computational logic must wait for data to be fetched by the pre-fetch
`
`unit. The statement relates only to the operation of the prefetch unit, not to the data
`
`5
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`
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`
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`that is fetched at a given time, which—per the ’867 Patent—must always be fetched
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`before it is needed in order to accomplish the goal that “bandwidth utilization is
`
`increased due to the ability of the data prefetch units 501 to initiate a data transfer in
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`advance of the requirement for data by computational logic.” Ex. 1001 at 7:66-8:2
`
`(emphasis added).
`
`Finally, Petitioners’ argument that Zhang discloses that some of the data
`
`fetched by Zhang may be used later does not teach a POSITA that Zhang’s “prefetch
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`unit” intentionally moves data before it is needed. Response at 17. This is directly
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`related to the teaching of the ’867 Patent that it transfers “only data required by the
`
`algorithm” and no other computational data, per Patent Owner’s proposed
`
`construction. Zhang’s second case study does not change this paradigm and
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`discloses only speculative fetching triggered by a read-miss. In Zhang’s second case
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`study, each matrix element requires 40 bytes of storage, but the centralized L1 cache
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`is only configurable to either 32 or 64 bytes. Zhang second case study thus also
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`retrieves superfluous data—at a minimum in the last cache row that is highly
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`unlikely to align perfectly on a cache boundary. Ex. 2028, ¶ 74. The ’867 Patent,
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`on the other hand, teaches reconfiguring the first memory (L1 cache in Zhang) as
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`multiple FIFO streams of the required width and depth in close proximity to multiple
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`computational units performing matrix multiplication calculations in parallel, one
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`whole row/column at a time. Id., ¶¶ 88, 121.
`
`6
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`
`
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`D. The combination does not render obvious a data prefetch unit
`“wherein the data prefetch unit retrieves only computational data
`required by the algorithm.”
`As explained previously (Paper 34 at 40-44), Zhang presents two case studies.
`
`First, both case studies use a specific library that contains only non-zero matrix
`
`elements meaning that the data needed for the computation is already optimized. Ex.
`
`2028, ¶¶ 74. Therefore, it is not a hardware adaptation which ensures that only data
`
`needed for computation is retrieved. Id. Second, Dr. Mangione-Smith explains that
`
`even Zhang’s optimized storage scheme does not disclose loading “only data
`
`required for the algorithm.” EX2028, ¶ 74. “It is highly unlikely that even in the
`
`efficient data storage scheme disclosed in Zhang, the last data elements of the matrix
`
`would completely fill up the last cache line perfectly. A POSITA would understand
`
`from Zhang’s disclosure that the entire last cache line is loaded, regardless of
`
`whether it is full or not.” Id. Petitioners’ argument regarding the likelihood of
`
`whether or not the data may or may not line up perfectly on a cache line boundary
`
`misses the point. Since the reference does not teach that the data does or at least
`
`should line up perfectly on a cache boundary means that it does not teach a POSITA
`
`to transfer only data that is actually used as required by the claims. Even considering
`
`the rare instance that it may line up perfectly does not mean that a POSITA would
`
`glean that this is desirable from Zhang’s disclosure. Zhang is simply agnostic as to
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`whether the last cache line is full of data required by the algorithm—the last cache
`
`line is loaded one way or the other. Dr. Shanfield confirmed this. Ex. 2029 at
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`7
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`
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`
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`218:20-219:7. Petitioners’ hail-Mary argument that Dr. Shanfield further stated that
`
`the cache is configurable does not cure this shortcoming because (1) the simulated
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`L1 and L2 caches have line sizes of only 32 or 64 bytes (Ex. 1003, at 15, Table 1)
`
`and no other options are disclosed; and (2) even though Dr. Shanfield stated that
`
`“because Zhang is ‘doing a simulation, he can vary that, or make that decision
`
`different than the entire row or column’” does not counter the point that—in fact—
`
`Zhang didn’t do so, and didn’t disclose any other cache line sizes. Most importantly,
`
`the problem is the same for any cache line size—because the likelihood that the
`
`given data at that moment matches the chosen cache line size is equally small for all
`
`possible choices. Unlike Zhang, the ’867 Patent addresses that exact problem by
`
`teaching that the cache size is specifically adapted to always match the data
`
`requirements. Zhang does not disclose this improvement.
`
`Finally, Petitioners argue that “the combinations’ prefetcher does not always
`
`transfer a complete cache line.” Response at 19 (citing EX1006 ¶203 (citing Ex.
`
`1004 at 9, 2:1-5)). However, the cited portion of the underlying reference does not
`
`support this argument:
`
`This prefetch hardware is combined, for some applications, with
`address translation and compaction hardware in the memory
`controller that works well with data structures that do not quite fit into
`a single cache line.
`Ex. 1004 at 9, 2:1-5. This excerpt, at best, supports that certain address
`
`translation and compaction hardware works well with data structures that do not
`
`quite fit into a single cache line, but says nothing about whether or not the entire
`8
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`
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`cache line is read at once or not. To the contrary, Gupta implements the prefetcher
`
`described in Zhang, and Zhang in turn teaches that “when the processor accesses the
`
`start of a row or column linked list, a prefetch for the entire row or column is
`
`initiated” and the main idea of “prefetching of whole rows or columns using pointer
`
`chasing in the memory module.” Ex. 1003 at 16, 1:36-37; 2:38-40.
`
`The combination does not render obvious a first memory and a
`E.
`data prefetch unit “wherein at least the first memory and data prefetch
`unit are configured to conform to needs of the algorithm.”
`Neither Zhang nor Gupta discloses reconfiguring the cache memory (first
`
`memory) or data prefetch unit to be matched to the exact needs of the algorithm.
`
`First, the memory disclosed in Zhang and Gupta is not configurable at all. Zhang
`
`specifically discloses reconfigurable components separate from the conventional
`
`memory it uses.
`
`
`
`Ex. 1003., Fig. 2 excerpt (emphasis added). All citations within Zhang and Gupta
`
`confirm that the reconfigurable logic resides only in the peripheral components
`
`“integrated with” as opposed to “contained within” the memory and cache: “using
`
`programmable logic integrated with the L1 cache.” EX1003 at 15, 2:4-5, Gupta
`
`“supports configurability of the cache memory via an on-board FPGA-based
`9
`
`
`
`
`
`memory controller.” EX1004 at 9, 1:8-9 and 2:35-37. The fact that Gupta’s cache
`
`can be configured to use cache lines of either 32 or 64 bytes does not disclose a cache
`
`that actually comprises reconfigurable hardware within the meaning of the invention
`
`of the ’867 Patent. Indeed, Gupta’s figure 1 confirms that only the cache controllers
`
`are in the programmable logic. Ex. 1004, Fig. 1. Gupta’s text explicitly confirms
`
`that “the FPGAs on the board contain controllers for the SRAM, DRAM, and L1
`
`cache.” Id., at 10, col. 1:43-45 (emphasis added). No indication is given that the
`
`memories themselves are implemented in programmable logic. Ex. 2028, ¶¶ 68, 97.
`
`Finally, Dr. Shanfield’s obvious statement that, since Zhang is a simulation, it could
`
`have simulated other cache line sizes still only discloses that a conventional cache is
`
`configured, not that a cache is actually implemented in reconfigurable hardware and
`
`adapted to the current algorithm as needed.
`
`The combination does not render obvious a data prefetch unit
`F.
`“configured to match format and location of data in the second
`memory.”
`Zhang does not disclose reconfiguring the memory unit to match the needs of
`
`the algorithm. Petitioners did not address the logic of the institution decision which
`
`noted that Zhang discloses this claim element based on Zhang’s aim “to send only
`
`used fields of matrix elements during a given computation,” and because
`
`“transferring all data (e.g., non-zero matrix elements) because all data is needed or
`
`required effectively retrieves only computational data required by the algorithm.”
`
`Paper 13 at 56, 57. This logic is faulty as it does not support that a POSITA would
`
`10
`
`
`
`
`
`glean from Zhang and Gupta to mind what data is or is not transferred. Instead, it
`
`supports—at best—that
`
`the claimed
`
`invention happens necessarily albeit
`
`inadvertently. In other words, Petitioners argue that the limitation is inherently
`
`present in the Zhang/Gupta/Chien combination. However, Dr. Mangione-Smith
`
`confirms that the mechanism of the claimed invention actually does not happen as
`
`of necessity. Ex. 2028 ¶ 74. While it could possibly happen, it is highly unlikely.
`
`Id. Case law supports that such a scenario is not a sufficient teaching by the prior
`
`art to render an invention obvious. Instead, the Federal Circuit requires that “the use
`
`of inherency, a doctrine originally rooted in anticipation, must be carefully
`
`circumscribed in the context of obviousness.” PAR Pharm., Inc. v. TWI Pharms.,
`
`Inc., 773 F.3d 1186, 1195 (Fed. Cir. 2014). “The mere fact that a certain thing may
`
`result from a given set of circumstances is not sufficient [to establish inherency].”
`
`In re Rijckaert, 9 F.3d 1531, 1533–34 (Fed.Cir.1993) (emphasis added). That is the
`
`exact situation here. Only in the unlikely event that the last data line matches up
`
`perfectly with the last cache line, would no extraneous data be fetched in Zhang.
`
`“[Only if] the disclosure is sufficient to show that the natural result flowing from the
`
`operation as taught would result in the [claim limitation], it seems to be well settled
`
`that the disclosure should be regarded as sufficient.” In re Oelrich, 666 F.2d 578,
`
`581 (C.C.P.A. 1981). That is simply not the case here. Instead, Zhang discloses
`
`only transfer of whole cache lines (Ex. 1003 at 16, 1:36-37; 2:38-40), which are
`
`highly unlikely to align with the data. Ex. 2028, ¶ 74.
`11
`
`
`
`
`
`III. CONCLUSION
`For the reasons reiterated here, the instituted combination of Zhang, Gupta,
`
`and Chien does not disclose or suggest the claimed inventions of the ’867 Patent.
`
`
`
`Date: October 22, 2021
`
`Respectfully submitted,
`
`
`
`/s/ Jay P. Kesan
`Jay P. Kesan
`Reg. No. 37,488
`Cecil E. Key
`Henning Schmidt
`DIMURO GINSBURG P.C.-
`DGKEYIP GROUP
`1750 Tyson’s Blvd., Suite 1500
`Tysons Corner, VA 22102
`(703) 289-5118
`jkesan@dimuro.com
`ckey@dimuro.com
`hschmidt@dimuro.com
`
`Ari Rafilson
`Reg no. 58,693
`SHORE CHAN LLP
`901 Main Street, Suite 3300
`Dallas, TX 75202
`(214) 593-9110
`arafilson@shorechan.com
`
`Attorneys for Patent
`Owner FG SRC LLC
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`12
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`CERTIFICATE OF SERVICE
`Pursuant to 37 C.F.R. §§ 42.6(e)(4) and 42.25(b), the undersigned certifies that
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`on October 22, 2021 a complete copy of Patent Owner’s Sur-Reply to Petitioners’
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`Reply to Patent Owner’s Response was filed electronically through the Patent Trial
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`and Appeal Board’s PTABE2E System and provided, via electronic service, to the
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`Petitioners by serving the correspondence address of record as follows:
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`Brian C. Nash
`PILLSBURY WINTHROP
` SHAW PITTMAN LLP
`401 Congress Avenue, Suite 1700
`Austin, TX 78701
`brian.nash@pillsburylaw.com
`
`Evan Finkel, Reg. No. 49,059
`PILLSBURY WINTHROP
` SHAW PITTMAN LLP
`725 S. Figueroa Street, Suite 2800
`Los Angeles, CA 90017-5406
`evan.finkel@pillsburylaw.com
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`Matthew Hindman, Reg. No. 57,396
`PILLSBURY WINTHROP
` SHAW PITTMAN LLP
`2550 Handover Street
`Palo Alto, CA 94304
`matthew.hindman@pillsburylaw.com
`
`Kenneth Darby Jr., Reg No. 65,068
`David Hoffman, Reg. No. 54,174
`FISH & RICHARDSON P.C.
`3200 RBC Plaza60 South Sixth Street
`Minneapolis, MN 55402
`hoffman@fr.com
`darby@fr.com
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`Dated: October 22, 2021
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`/s/ Jay P. Kesan
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`13
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`CERTIFICATE OF WORD COUNT
`Pursuant to 37 C.F.R. § 42.24(d), the undersigned certifies that the foregoing
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`Sur-Reply to Petitioners Reply to Patent Owner’s Response contains less than 5600
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`words, excluding the table of contents, table of authorities, certificate of service,
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`certificate of word count, and appendix of exhibits. Patent Owner has relied on the
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`word count feature of the word processing software used to create this paper in
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`making this certification.
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`Dated: October 22, 2021
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`/s/ Jay P. Kesan
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`14
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