UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INTEL CORPORATION,
`Petitioner,
`V.
`FG SRC LLC,
`Patent Owner.
`
`IPR2020-01449
`Patent No. 7,149,867
`
`DECLARATION OF WILLIAM MANGIONE-SMITH, PH.D., IN
`SUPPORT OF FG SRC LLC'S REVISED MOTION TO AMEND
`
`I, Dr. William Mangione-Smith, under the penalty of perjury under the laws
`
`of the United States, declare that the following is true and correct based on the best
`
`of my ability.
`
`Date: September 29, 2021
`
`Signedy
`WILLIAM MANGIONE-SMITH, PH.D.
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INTEL CORPORATION,
`Petitioner,
`V.
`FG SRC LLC,
`Patent Owner.
`
`IPR2020-01449
`Patent No. 7,149,867
`
`DECLARATION OF WILLIAM MANGIONE-SMITH, PH.D., IN
`SUPPORT OF FG SRC LLC'S REVISED MOTION TO AMEND
`
`I, Dr. William Mangione-Smith, under the penalty of perjury under the laws
`
`of the United States, declare that the following is true and correct based on the best
`
`of my ability.
`
`Date: September 29, 2021
`
`Signedy
`WILLIAM MANGIONE-SMITH, PH.D.
`
`
`
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`
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`1.
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`I have been retained by DiMuro Ginsberg, P.C., as an independent
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`technical expert in the Inter Partes Review dispute between FG SRC, and Intel
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`Corporation, No. IPR2020-01449 which involves U.S. Patent No. 7,149,867 (“’867
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`Patent”).
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`2.
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`I have been paid for my work as a technical expert at my customary
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`hourly rate. My compensation does not in any way depend on the outcome of this
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`matter, and I have no personal interest in the outcome of this matter.
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`I.
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`Qualifications
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`3. My technical background and experience cover most aspects of
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`computer system design, including low level circuitry, computer architecture,
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`computer networking, digital rights management, cryptography, digital media,
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`communications, information technology, application software, client-server
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`application, Web technology, and system software (e.g., operating systems and
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`compilers). I am a member of the Institute of Electrical and Electronics Engineers
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`and the Association for Computing Machinery, which are the two most significant
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`professional organizations in my profession. I have been employed as a design
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`engineer, research engineer, professor, and technical expert. Over my professional
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`career, I have been an active inventor with 121 issued U.S. patents, 200 published
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`and pending U.S. patent applications and many unpublished U.S. patent
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`applications.
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`2
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`4.
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`From 1984 until 1991, I attended the University of Michigan in Ann
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`Arbor, Michigan, where I was awarded the degrees of Bachelor of Science and
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`Engineering, Master of Science and Engineering, and Doctor of Philosophy. My
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`doctoral research focused on high performance computing systems including
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`computer architecture, applications and operating system software, and compiler
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`technology. One of my responsibilities during my graduate studies included
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`teaching senior undergraduate students who were about to enter the profession.
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`5.
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`After graduating from the University of Michigan, I was employed by
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`Motorola in Schaumburg, Illinois. While at Motorola, I was part of a team
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`designing and manufacturing the first commercial battery-powered product capable
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`of delivering Internet email over a wireless (i.e., radio frequency) link and one of
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`the first personal digital assistants. I also served as the lead architect on the
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`second-generation of this device with control over the entire system design
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`including the memory subsystem architecture, embedded processor, ASIC, power
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`system, and analog circuitry. Part of my responsibilities at Motorola involved the
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`specification, design, and testing of system control Application-Specific Integrated
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`Circuits (“ASICs”). I conducted the initial research and advanced design that
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`resulted in the Motorola M*Core embedded microprocessor. M*Core was
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`designed to provide the high performance of desktop microprocessors with the low
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`power of contemporaneous embedded processors. The M*Core received
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`3
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`widespread use in many communications products including various cellular
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`handsets, advanced pagers, and embedded infrastructure.
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`6.
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`From 1995 until 2005, I was employed by the University of California
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`at Los Angeles (“UCLA”) as a professor of Electrical Engineering. I was the
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`director of the laboratory for Compiler and Architecture Research in Embedded
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`Systems (“CARES”) and served as the field chair for Embedded Computing
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`Systems. The CARES research team focused on research, engineering, and design
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`challenges in the context of battery-powered and multi-media mobile computing
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`devices. One of the key developments of my lab was the Mediabench software
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`tool, which is widely used to design and evaluate multi-media embedded devices.
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`Key elements of Mediabench include software that is essential for modern digital
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`wireless communications. My primary responsibility, in addition to classroom
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`teaching, involved directing the research and training of graduate students. I was a
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`tenured member of the faculty and had responsibilities for teaching as well as
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`scholarly research. My colleagues at UCLA were some of the leading scientists
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`and engineers in the world with a long list of innovations from computer network
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`security devices to the nicotine patch. The graduate student researchers in my
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`laboratory came from a diverse set of backgrounds, all with undergraduate degrees
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`in computer engineering, electrical engineering, or computer science, many with
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`multiple years of experience working as professional engineers in areas such as
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`4
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`digital rights management, cryptography, and some combination of digital media,
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`communications, information technology, software development, computer system
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`design, or computer science and ASIC circuit design.
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`7.
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`From 2005 until 2009, I was employed at Intellectual Ventures in
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`Bellevue, Washington. My responsibilities at Intellectual Ventures included
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`business development, technology assessment, market forecasting, university
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`outreach, collaborative inventing, intellectual property licensing support, and
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`intellectual property asset pricing. My colleagues and co-inventors at Intellectual
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`Ventures included the former lead intellectual property strategist at Intel, Intel’s
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`former lead IP counsel, Microsoft’s former chief software architect, the founder of
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`Microsoft research, the designer of the Mach operating system, the architect of the
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`U.S. Defense Department’s Strategic Defense Initiative, the founder of Thinking
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`Machines (a seminal parallel processing computer system), and Bill Gates. I had
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`responsibility for hiring and managing over 15 staff members including multiple
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`Ph.Ds. with degrees in electrical engineering or computer science, and decades of
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`experience in product design and engineering.
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`8.
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`A summary of some of my qualifications for forming the opinions in
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`this declaration are as follows: I have more than 30 years of experience as a
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`computer architect, computer system designer, communication system designer,
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`educator, and as an executive in the PC and electronics business. I am also a
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`5
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`member of several professional associations, such as the ACM and IEEE, and have
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`
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`been intimately involved in professional research through the International
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`Symposium on Microarchitecture (Program Chair for 26th and General Chair for
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`36th), IEEE Transactions on Computers (Associate Editor), ACM Transactions on
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`Embedded Computing Systems (Associate Editor), and IEEE Computer (Associate
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`Editor). I also have been on the program committees for ISCA, MICRO, ISLPED,
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`Network Processors Workshop, FPL, Complexity-Effective Design, RAW,
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`Workshop on Mediaprocessors, and DSP, FPT, and INTERACT.
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`9.
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`I also have extensive experience and expertise with FPGA technology
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`in general and reconfigurable computing in particular. My research was funded by
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`the US Defense Advanced Research Projects Agency (DARPA), published in
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`leading journals in my field, and appeared on the cover of Scientific American
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`(June 1997). Specific research areas included cryptography, network security,
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`fault-tolerance, and intellectual property protection.
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`10. For further details regarding my employment and academic history,
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`please refer to my curriculum vitae provided in Appendix A.
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`II. Bases Of Opinions
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`11. The basis and reasoning of my opinions include my education,
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`training, and experience as an engineer, including my 35 years of experience
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`
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`6
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`
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`designing microprocessors. In the course of conducting my analysis and forming
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`
`
`my opinions, I have considered the materials listed below:
`
`a. U.S. Patent No. 7,149,867 to Daniel Poznanovic, et al., filed June16,
`2004, and issued on December12, 2006 (“’867 patent”) and its file
`history;
`b. X. Zhang et al., Architectural Adaptation of Application-Specific
`Locality Optimizations, IEEE (1997) (“Zhang”);
`c. R. Gupta, Architectural Adaptation in AMRM Machines, IEEE (2000)
`(“Gupta”);
`d. A. Chien and R. Gupta, MORPH: A System Architecture for Robust
`Higher Performance Using Customization,” IEEE (1996) (“Chien”);
`e. Chien et al., Safe and Protected Execution for the Morph/AMRM
`Reconfigurable Processor, IEEE (1999);
`f. Declaration of Stanley Shanfield, Ph.D.;
`g. Declaration of Rajesh K. Gupta;
`h. Declaration of J. Munford;
`i. Provisional Application No. 60/479,339;
`j. U.S. Patent 8,713,518;
`k. Book: John L. Hennessy and David A. Patterson, “Computer
`Architecture: A Quantitative Approach” (The Morgan Kaufmann Series
`in Computer Architecture and Design); and
`l. Book: David Culler, “Parallel Computer Architecture: A
`Hardware/Software Approach” (The Morgan Kaufmann Series in
`Computer Architecture and Design);
`m. Intel’s IPR petition in this matter and its exhibits;
`n. Declaration of Ryan Kastner, Ph.D. In Support Of FG SRC LLC’s
`Opening Claim Construction Brief in FG SRC LLC v. Intel Corp., No.
`6:20-cv-00315-ADA (W.D. Texas), filed April 24, 2020;
`
`
`
`7
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`
`
`
`
`
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`o. FG’SRC’s Preliminary Response in this proceeding (Paper 9);
`p. Declaration of Vojin G. Oklobdzija, Ph.D., In Support of FG SRC
`LLC’s Preliminary Response (EX2001);
`q. Institution Decision in this proceeding (Paper 13);
`r. Intel Corporation’s Opposition to the Motion to Amend (Paper 36);
`s. The Board’s Preliminary Guidance – Patent Owner’s Motion To Amend
`issued on Sep. 15, 2021 (Paper 38);
`t. U.S. Patent No. 5,737,631 to Trimberger, filed April 5, 1995, and issued
`on April 7, 1998 (“Trimberger”), and the materials cited therein;
`u. Any other materials referenced herein.
`12. My opinions in this declaration are based on the understanding of a
`
`person of ordinary skill in the art at the time of the invention of the claims in the
`
`’867 Patent.
`
`13.
`
`In assessing the level of skill of a person of ordinary skill in the art I
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`have considered the type of problems encountered in the field, the prior solutions
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`to those problems found in the prior art references, the pace with which
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`innovations are made, the sophistication of the technology, the level of education
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`of active workers in the field, and my own experience working with those of skill
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`in the art at the time of the invention.
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`14. A person of ordinary skill in the art (“POSITA”) at the time of the
`
`filing of the ’867 patent would typically have at least an M.S. Degree in Computer
`
`Engineering, Computer Science, or Electrical Engineering, or equivalent work
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`experience, along with at least three years of experience related specifically to
`8
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`
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`computer architecture, hardware design, and reconfigurable processors. In
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`
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`addition, a POSITA would be familiar with hardware description languages and
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`design tools and methodologies used to program a reconfigurable processor.
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`15.
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`I am very familiar with this level of skill. In the course of my 35
`
`years of processor design and research, I have supervised and worked with
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`engineers in this field having the level of skill identified above.
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`16.
`
`I understand that the words of a claim are generally given their
`
`ordinary and customary meaning, that is, the meaning that the term would have to
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`a person of ordinary skill in the art in question at the time of the invention
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`17.
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`I understand that a claim term that does not use the word “means” is
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`presumed not to be a means-plus-function term. I understand that a term that does
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`not use the word “means” would be construed as a means-plus-function term if it
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`does not describe structure to a POSITA. Conversely, I understand that if a term
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`describes structure to a POSITA, it is not a means-plus-function term.
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`III. ANALYSIS OF PROPOSED CLAIM AMENDMENTS
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`18.
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`I have been asked to provide my expert opinion regarding proposed
`
`amended claims 20 (amending original claim 1), 21 (amending original claim 1),
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`28 (replacing claim 9), and 32 (replacing claim 13), and specifically, whether the
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`proposed amendments to the proposed amended claims are (1) responsive to a
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`ground for unpatentability at issue in this IPR per the institution decision; (2)
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`
`
`9
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`
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`enlarging the claim scope; or (3) introducing new subject matter; and (4) whether
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`
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`the proposed amended claims, as a whole, are (a) supported by the patent
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`specification; and (b) supported by the provisional application to which they claim
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`priority.
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`A.
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`Proposed Amended Claim 20 (Amending Claim 1)
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`19. Proposed Amended Claim 20 appears below. I have been provided
`
`these amended claims along with editing that uses underlining to indicate
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`additions.
`
`Proposed Amended Claim 20. A reconfigurable processor that
`instantiates an algorithm as hardware comprising:
`a first memory having a first characteristic memory bandwidth and/or
`memory utilization; and
`a data prefetch unit coupled to the memory, wherein the data prefetch
`unit retrieves only computational data required by the algorithm
`from a second memory of second characteristic memory
`bandwidth and/or memory utilization and places the retrieved
`computational data in the first memory wherein the data prefetch
`unit operates independent of and in parallel with logic blocks
`using the computational data, and wherein at least the first
`memory and data prefetch unit are configured to conform to
`needs of the algorithm, and the data prefetch unit is configured to
`match format and location of data in the second memory,
`wherein the reconfigurable processor is neither integrated within nor
`comprises a conventional microprocessor, and
`wherein the reconfigurable processor operates independent of and in
`parallel with a conventional microprocessor.
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`
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`10
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`20.
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`I understand that the Board in its institution decision found that
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`“Petitioner has shown sufficiently that Zhang in combination with Gupta would
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`have rendered claims 1, 2, 4–8, 13–19 obvious.” Paper 13, at 71. Based on my
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`understanding of the requirements of patentability and obviousness, the addition of
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`substantive limitations supported by the patent specification that are not obvious is
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`one approach for responding to such a ground for institution. The proposed
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`amendments shown here thus directly address the grounds for institution.
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`21.
`
`In my expert opinion, proposed amended claim 20 does not broaden
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`claim scope. To the contrary, as a result of the addition of the limiting elements
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`requiring that “wherein the reconfigurable processor is neither integrated within
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`nor comprises a conventional microprocessor” and “wherein the reconfigurable
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`processor operates independent of and in parallel with a conventional
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`microprocessor,” the claim scope is narrowed. By requiring that the reconfigurable
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`processor is neither integrated within nor comprises a conventional
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`microprocessor, the amendment excludes from the claim scope the use of a
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`conventional CPU together with only limited reprogrammable peripheral
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`components as well as “reconfigurable system” which has a CPU integrated in it.
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`In other words, the reconfigurable processor that instantiates an algorithm as
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`hardware does not utilize a conventional microprocessor in any way for the
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`purposes of said algorithm.
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`11
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`22. Further, the amendment explicitly excludes from the claim scope the
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`use of a conventional CPU as the computational unit of the claimed reconfigurable
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`processor together with only limited reprogrammable peripheral components. This
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`narrowing of the claim is directly responsive to the Zhang, Gupta, and Chien prior
`
`art, which relies on the use of a CPU together with only “small pockets of
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`reprogrammable logic.” Ex. 1003, at 13, col. 2:44-49. Therefore, this is a scope
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`limiting amendment.
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`23.
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`In Zhang, the processor running the main application is a conventional
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`CPU, not a reconfigurable processor. This is shown in Fig. 2 of Zhang.
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`Ex. 1003, Fig. 2. Zhang uses programmable logic (FPGA) only as means to
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`deliver data for use by that conventional CPU. Zhang specifically states that it
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`12
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`
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`includes only “small blocks of programmable logic implemented into key elements
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`
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`of a baseline architecture” to enable “the customization of architectural
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`mechanisms and policies to match an application.” Ex. 1003, at 13, col. 2:44-49.
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`Zhang’s small blocks of programmable hardware facilitate movement of data
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`between memory hierarchies to reduce latency at the point of data consumption.
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`Id. Unlike the ’867 patent however, the final consumer is a conventional CPU, not
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`a reconfigurable processor. Gupta builds on Zhang and thus also uses a
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`conventional CPU, as I explained in more detail in my prior declaration.
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`24. Similarly, the amendment that “the reconfigurable processor operates
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`independent of and in parallel with a conventional microprocessor” limits claim
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`scope by excluding the use of a reconfigurable processor that does not operate
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`independent of and in parallel with a conventional microprocessor, as that
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`purportedly disclosed by Trimberger.
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`25. Regarding the newly cited Trimberger reference, a POSITA would
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`understand that Trimberger teaches a tightly integrated conventional microprocessor
`
`that is augmented with a reconfigurable component for implementing special purpose
`
`instructions. Thus, Trimberger is intended to extend the instruction set of a
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`conventional microprocessor.
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`26. The figure below is labeled Figure 5.1 in the 1998 edition of Computer
`
`Organization & Design, the Hardware/Software Interface by Patterson and
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`
`
`13
`
`
`
`
`Hennessy. This textbook is considered the gold standard for computer architecture
`
`
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`classes. The figure discloses a simple model for a processor that has an instruction
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`memory, a set of registers that hold local data, and an arithmetic logic unit (ALU).
`
`
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`27. This figure is structurally the same as Fig. 1 of Trimberger which
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`discloses the Trimberger invention. In Trimberger, the FIXED E-UNIT 24 serves the
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`role of the ALU above. Trimberger has added a second function unit, the PRGM E-
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`UNIT 30, which is implemented as programmable hardware. The use of multiple
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`execution units, for example the presence of multiple ALUs in the figure above, was
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`well known in the art at the time of Trimberger’s filing. His novelty revolved around
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`having a programmable execution unit where the hardware functions could be
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`changed.
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`
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`14
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`
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`28.
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` Trimberger discloses that the processor's register file and bus are
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`directly accessible to the programmable hardware execution unit (Fig. 1, 4:11-28, Fig.
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`2, 7:57-8:4).
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`29.
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`Trimberger does not talk about fetching data of any sort at all, let alone
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`prefetching data. While the entire purpose of the ’867 patent is to improve the
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`usefulness of memory access, Trimberger only ever refers to instruction fetching, and
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`not even instruction prefetching. A POSITA would recognize that instructions and
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`data are two separate and distinct things.
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`30.
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` Additionally, while the ’867 patent claims implementing entire
`
`algorithms in programmable logic, Trimberger discloses implementing instructions in
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`programmable logic (Title, Abstract, 2:62-3:9). Examples of the types of instructions
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`that Trimberger envisioned implementing include bit manipulation, bit counting,
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`polynomial evaluation, arithmetic sequences, search, spell-check, procedure
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`invocation, and context switching (3:10-27). None of these operations would be
`
`characterized as algorithms. Thus, a POSITA would understand that Trimberger
`
`neither disclosed nor taught implementing an algorithm in a reconfigurable processor,
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`as required by the claims of the ’867 Patent.
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`31.
`
`In contrast, the ’867 Patent discloses a reconfigurable processor with no
`
`linkages to a conventional microprocessor. Figures 1 and 3 of the ’867 Patent
`
`disclose an embodiment of the ’867 patented invention and no general-purpose
`
`processor or microprocessor is present. Nowhere in the written description of the
`
`
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`15
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`
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`’867 Patent is a linkage between the reconfigurable processor and a conventional
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`
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`processor disclosed or taught. Rather, all the teaching in the ’867 Patent is directed to
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`a reconfigurable processor that executes algorithms in the absence of any
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`conventional processor, and certainly without any tight linkages or coordination.
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`B.
`
`Proposed Amended Claim 28 (Replacing Claim 9)
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`32. Proposed Amended Claim 28 is set forth below. Underlining is used
`
`to indicate additions.
`
`Proposed Amended Claim 28. A reconfigurable hardware system,
`comprising:
`a common memory; and
`one or more reconfigurable processors that can instantiate an algorithm
`as hardware coupled to the common memory, wherein at least
`one of the reconfigurable processors includes a data prefetch unit
`to read and write only data required for computations by the
`algorithm between the data prefetch unit and the common
`memory wherein the data prefetch unit operates independent of
`and in parallel with logic blocks using the computational data,
`and wherein the data prefetch unit is configured to conform to
`needs of the algorithm and match format and location of data in
`the common memory,
`wherein data required for computations by the algorithm comprises
`only data required for the instantiation and execution of the
`algorithm,
`wherein the at least one of the reconfigurable processors is neither
`integrated within nor comprises a conventional microprocessor,
`and
`wherein the at least one of the reconfigurable processors operates
`independent of and in parallel with a conventional
`microprocessor.
`
`
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`16
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`33.
`
`I understand that the Board in its institution decision found that
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`“Petitioner has adequately shown that Zhang, Gupta, and Chien teach the
`
`limitations in claim 9 for purposes of institution.” Paper 13, at 73. Based on my
`
`understanding of the requirements of patentability and obviousness, the addition of
`
`substantive limitations supported by the patent specification that are not obvious is
`
`responsive to a ground for institution. The proposed amendments shown here
`
`directly address the grounds for institution.
`
`34.
`
`In my expert opinion, proposed amended claim 28 does not broaden
`
`claim scope. To the contrary, the addition of the limiting elements narrows claim
`
`scope. First, by requiring that “the at least one of the reconfigurable processors is
`
`neither integrated within nor comprises a conventional microprocessor,” the claim
`
`scope is narrowed for the reasons explained above in reference to proposed
`
`amended claim 20. The amendment explicitly excludes the use of a conventional
`
`CPU as the computational unit of the claimed reconfigurable processor, which is
`
`directly responsive to the Zhang, Gupta, and Chien prior art, which relies on the
`
`use of a CPU together with only “small pockets of reprogrammable logic.” Ex.
`
`1003, at 13, col. 2:44-49; see also id. at Fig. 2.
`
`35. Second, the addition of the claim element “the at least one of the
`
`reconfigurable processors operates independent of and in parallel with a
`
`conventional microprocessor” limits claim scope for the reasons explained above
`
`
`
`17
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`
`
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`in reference to proposed amended claim 20. This amendment explicitly excludes
`
`
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`the use of a reconfigurable processor that does not operate independent of and in
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`parallel with a conventional microprocessor, as that purportedly disclosed by
`
`Trimberger.
`
`36. Third, the claim element “wherein data required for computations by
`
`the algorithm comprises only data required for the instantiation and execution of
`
`the algorithm” further limits claim scope by excluding all information from the
`
`term “data required for computations” that is not used for either instantiation or
`
`execution of the algorithm. This amendment excludes any other kind of
`
`information being read or written that is not directly required for computing the
`
`algorithm.
`
`C.
`
`Proposed Amended Claim 32 (Replacing Claim 13)
`
`37. Proposed Amended Claim 32 is set forth below. Underlining is used
`
`to indicate additions.
`
`Proposed Amended Claim 32. A method of transferring data
`comprising:
`transferring data between a memory and a data prefetch unit in a
`reconfigurable processor, and
`transferring the data between a computational unit and the data access
`unit, wherein the computational unit and the data access unit, and
`the data prefetch unit are configured to conform to needs of an
`algorithm implemented on the computational unit and transfer
`only data necessary for computations by the computational unit,
`and wherein the prefetch unit operates independent of and in
`
`
`
`18
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`
`
`
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`parallel with the computational unit,
`wherein data necessary for computations by the computational unit
`comprises only data necessary for the configuration and
`execution of computations by the computational unit, and
`wherein the computational unit is neither integrated within nor
`comprises a conventional microprocessor, and
`wherein the reconfigurable processor operates independent of and in
`parallel with a conventional microprocessor.
`I understand that the Board in its institution decision found that
`
`38.
`
`“Petitioner has shown sufficiently that Zhang in combination with Gupta would
`
`have rendered claims 1, 2, 4–8, 13–19 obvious.” Based on my understanding of
`
`the requirements of patentability and obviousness, by adding substantive
`
`limitations supported by the patent specification that are not obvious a patent
`
`owner is responding to a ground for institution. The proposed amendments shown
`
`here directly address the grounds for institution.
`
`39.
`
`In my expert opinion, proposed amended claim 32 does not broaden
`
`claim scope. To the contrary, the addition of the limiting elements narrows claim
`
`scope. By requiring that “wherein the computational unit is neither integrated
`
`within nor comprises a conventional microprocessor,” the claim scope is narrowed
`
`for the reasons explained above in reference to proposed amended claim 20. The
`
`amendment explicitly excludes the use of a conventional CPU as the computational
`
`unit of the claimed reconfigurable processor, which is directly responsive to the
`
`Zhang, Gupta, and Chien prior art, which relies on the use of a CPU together with
`
`
`
`19
`
`
`
`
`only “small pockets of reprogrammable logic.” Ex. 1003, at 13, col. 2:44-49; see
`
`
`
`also id. at Fig. 2.
`
`40. Second, the addition of the claim element “wherein the reconfigurable
`
`processor operates independent of and in parallel with a conventional
`
`microprocessor” limits claim scope for the reasons explained above in reference to
`
`proposed amended claim 20. This amendment explicitly excludes the use of a
`
`reconfigurable processor that does not operate independent of and in parallel with a
`
`conventional microprocessor, as that purportedly disclosed by Trimberger.
`
`IV. REVISION OR SUPPLEMENTATION
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`41. My opinions are subject to change or revision. I may acquire
`
`additional opinions that Petitioner or its expert may present or information I may
`
`receive in the future or additional work I may perform. With this in mind, based
`
`on the analysis I have conducted and for the reasons set forth, I have preliminarily
`
`reached the conclusions and opinions in this Report.
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`V. EXHIBITS
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`42.
`
`In the event of a hearing or trial in this matter, I may create and/or use
`
`various exhibits relevant to this case for the purposes of demonstrating my
`
`testimony as discussed in this Report. I have not yet selected the particular
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`exhibits or created or assisted in the creation of demonstrative exhibits to assist me
`
`in testifying.
`
`
`
`20
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`
`
`
`VI. CONCLUSION
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`
`
`43. For at least the reasons stated above, and others, it is my expert
`
`opinion that Petitioner’s references do not disclose all elements of any of the
`
`amended claims of the ’867 Patent.
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`
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`21
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`
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