`
`
`
`Paper No. 40
`Filed: September 24, 2021
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________
`
`INTEL CORPORATION and XILINX, INC.,1
`
`Petitioners,
`
`v.
`
`FG SRC LLC,
`
`Patent Owner
`
`____________________
`
`CASE NO.: IPR2020-01449
`PATENT NO. 7,149,867
`____________________
`
`PETITIONERS’ REPLY TO PATENT OWNER’S RESPONSE TO
`PETITION
`
`
`
`
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`1 Xilinx, Inc. filed a motion for joinder and petition in IPR2021-00633, which was
`granted, and, therefore has been joined as petitioner in this proceeding.
`
`
`
`
`
`
`
`TABLE OF CONTENTS
`
`Page
`
`I.
`
`Introduction .......................................................................................................... 1
`
`II. PO’s constructions should not be adopted ........................................................... 2
`
`III. Zhang, Gupta, and Chien are prior art ................................................................. 4
`
`IV. The instituted combinations render the claims obvious ...................................... 8
`
`A. PO’s “teaching away” and “enabling disclosure” arguments fail ................. 8
`
`B. The combination teaches the claimed “reconfigurable
`processor” .................................................................................................... 10
`
`C. The combination teaches the claimed “data prefetch unit” ......................... 16
`
`D. The combination teaches the “only” limitations ......................................... 18
`
`E. The combination teaches the “configured to conform”
`limitations .................................................................................................... 21
`
`F. PO repeats the above arguments for other limitations and claims .............. 24
`
`V. PO fails its burden on secondary considerations ............................................... 24
`
`VI. Conclusion ......................................................................................................... 26
`
`CERTIFICATE OF COMPLIANCE ....................................................................... 28
`
`CERTIFICATE OF SERVICE ................................................................................ 29
`
`
`
`
`
`i
`
`
`
`
`
`TABLE OF AUTHORITIES
`
`Page(s)
`
`Cases
`
`Amgen Inc. v. Hoechst Marion Roussel, Inc.
`314 F.3d 1313 (Fed. Cir. 2003) ............................................................................ 9
`
`FG SRC, LLC v. Intel Corp.,
`6:20-cv-00315, ECF No. 1 (W.D. Tex. Apr. 24, 2020) ...................................... 26
`
`Fox Factory, Inc. v. SRAM, LLC,
`944 F.3d 1366 (Fed. Cir. 2019) .......................................................................... 24
`
`Hulu, LLC v. Sound View Innovations, LLC,
`IPR2018-01039, Paper 29 17-18 (Dec. 20, 2019) ................................................ 5
`
`In re Lister,
`583 F.3d 1307 (Fed. Cir. 2009) ............................................................................ 8
`
`Ormco Corp. v. Align Tech., Inc.,
`463 F.3d 1299 (Fed. Cir. 2006) .......................................................................... 25
`
`VidStream LLC v. Twitter, Inc.,
`981 F.3d 1060 (Fed. Cir. 2020) ............................................................................ 5
`
`Voter Verified, Inc. v. Premier Election Sols. Inc.,
`698 F.3d 1374 (Fed. Cir. 2012) ............................................................................ 7
`
`Wyers v. Master Lock Co.,
`616 F.3d 1231 (Fed. Cir. 2010) .......................................................................... 26
`
`
`
`
`
`ii
`
`
`
`
`
`TABLE OF EXHIBITS
`
`Exhibit No.
`
`Description
`
`Exhibit 1001 U.S. Patent No. 7,149,867 to Daniel Poznanovic, et al., filed June
`16, 2004, and issued on December 12, 2006 (the “’867 patent”).
`
`Exhibit 1002 Prosecution history of the ’867 patent.
`
`Exhibit 1003 X. Zhang et al., Architectural Adaptation of Application-Specific
`Locality Optimizations, IEEE (1997) (“Zhang”).2
`
`Exhibit 1004 R. Gupta, Architectural Adaptation in AMRM Machines, IEEE
`(2000) (“Gupta”).
`
`Exhibit 1005 A. Chien and R. Gupta, MORPH: A System Architecture for
`Robust Higher Performance Using Customization,” IEEE (1996)
`(“Chien”).
`
`Exhibit 1006 Declaration of Stanley Shanfield, Ph.D.
`
`Exhibit 1007 RESERVED
`
`Exhibit 1008 RESERVED
`
`Exhibit 1009 RESERVED
`
`Exhibit 1010 Declaration of Rajesh K. Gupta
`
`Exhibit 1011 Chien et al., Safe and Protected Execution for the Morph/AMRM
`Reconfigurable Processor, IEEE (1999).
`
`Exhibit 1012 Declaration of Jacob Munford
`
`Exhibit 1013 RESERVED
`
`Exhibit 1014 Order Governing Proceedings - Patent Case by Judge Alan D
`Albright, filed on June 30, 2020 in FG SRC LLC v. Intel
`Corporation, No. 6:20-cv-00315-ADA (W.D. Tex.)
`
`Exhibit 1015 Scheduling Order by Judge Alan D Albright, filed on August 1,
`2020 in FG SRC LLC v. Intel Corporation, No. 6:20-cv-00315-
`ADA (W.D. Tex.)
`
`
`2 For ease of reference and citation, Petitioner has added line numbers to Exhibits
`1003, 1004, 1005 and 1011. For example, the citation “EX1003-15 C2:4-16” refers
`to Exhibit 1003, Page 15, Column 2, Lines 4-16, and the subsequent citation “id.-
`12 C1:12-C2:5” refers to Exhibit 1003, Page 12, Column 1, Line 12 through
`Column 2, Line 5.
`
`iii
`
`
`
`
`
`Exhibit No.
`
`Description
`
`Exhibit 1016 Plaintiffs SRC Labs, LLC & Saint Regis Mohawk Tribe’s
`Opening Claim Construction Brief, filed on November 5, 2018 in
`SRC Labs, LLC et al. v. Amazon Web Services, Inc. et al., No.
`2:18-cv-00317-JLP (W.D. Was.)
`
`Exhibit 1017 Provisional Patent Application No. 60/479,339
`
`Exhibit 1018 Plaintiff's Preliminary Infringement Contentions, submitted on
`July 23, 2020 in FG SRC LLC v. Intel Corporation, No. 6:20-cv-
`00315-ADA (W.D. Tex.)
`
`Exhibit 1019 Amended Scheduling Order by Judge Alan D Albright, filed on
`December 18, 2020 in UNM Rainforest Innovations v. Dell
`Technologies et al., No. 6:20-cv-00468-ADA (W.D. Tex.)
`
`Exhibit 1020 Docket Sheet from UNM Rainforest Innovations v. Dell
`Technologies et al., No. 6:20-cv-00468-ADA (W.D. Tex.)
`
`Exhibit 1021 Scheduling Order by Judge Alan D Albright, filed on November
`19, 2020 in Theta IP, LLC v. Samsung Electronics Co., Ltd. et al.,
`No. 6:20-cv-00160-ADA (W.D. Tex.)
`
`Exhibit 1022 Agreed Post-Markman Scheduling Order by Judge Alan D
`Albright, filed on December 3, 2020 in Videoshare, LLC v.
`Google LLC and YouTube, LLC, No. 6:19-cv-00663-ADA (W.D.
`Tex.)
`
`Exhibit 1023 Docket Sheet from H-E-B, LP v. Wadley Holdings, LLC, dba
`nICE Coolers et al., No. 6:20-cv-00081-ADA (W.D. Tex.)
`
`Exhibit 1024 Western District of Texas Order by Chief Judge Orlando L.
`Garcia
`regarding Court Operations Under
`the Exigent
`Circumstances Created by the COVID-19 Pandemic, filed on
`March 13, 2020 in all cases.
`
`Exhibit 1025 Western District of Texas Eleventh Supplemental Order by Chief
`Judge Orlando L. Garcia Regarding Court Operations Under the
`Exigent Circumstances Created by the COVID-19 Pandemic,
`filed on December 10, 2020 in all cases.
`
`Exhibit 1026 December 23, 2020 email from H. Santasawatkul to Counsel
`
`Exhibit 1027 Declaration of Gordon MacPherson
`
`Exhibit 1028 Declaration of Eileen D. McCarrier
`
`Exhibit 1029 Declaration of Austin M. Schnell
`
`iv
`
`
`
`
`
`
`
`Exhibit No.
`
`Description
`
`Exhibit 1030 Supplemental Declaration of Rajesh K. Gupta, Ph.D.
`
`Exhibit 1031 Supplemental Declaration of Jacob Robert Munford
`
`Exhibit 1032 RESERVED
`
`Exhibit 1033 District Court Claim Construction Order
`
`Exhibit 1034 Declaration of Stanley Shanfield, Ph.D.
`
`Exhibit 1035 March 12, 2021 email from M. Shore to B. Nash
`
`Exhibit 1036 March 31, 2021 email from M. Shore to Court and Counsel
`
`Exhibit 1037 U.S. Patent No. 5,737,631 to Trimberger, filed April 5, 1995, and
`issued on April 7, 1998 (“Trimberger”).
`
`Exhibit 1038 Plaintiff FG SRC’s Opening Claim Construction Brief, filed on
`November 17, 2020 in FG SRC LLC v. Intel Corporation, No.
`6:20-cv-00315-ADA (W.D. Tex.)
`
`Exhibit 1039 Deposition transcript of Rajesh K. Gupta, Ph.D.
`
`Exhibit 1040 Deposition transcript of Gordon MacPherson (IEEE)
`
`Exhibit 1041 Assignment to FG SRC, LLC
`
`Exhibit 1042 Chapter 7 Case Schedules, In re DirectStream LLC, Case No. 20-
`10534, 2020 WL 3483549, ECF No. 3 (Bankr. D. Del. 2020)
`(Walrath, J.)
`
`Exhibit 1043 Deposition transcript of Stanley Shanfield, Ph.D.
`
`Exhibit 1044 Deposition transcript of William Mangione-Smith
`
`
`
`
`
`v
`
`
`
`
`
`
`
`LIST OF ABBREVIATIONS
`
`Abbreviation
`
`Description
`
`Pet.
`
`POPR
`
`PRPR
`
`Intel Corp. v. FG SRC LLC, IPR2020-01449, Paper 1, Petition
`for Inter Partes Review of U.S. Patent No. 7,149,867
`
`Intel Corp. v. FG SRC LLC, IPR2020-01449, Paper 9, Patent
`Owner’s Preliminary Response
`
`Intel Corp. v. FG SRC LLC, IPR2020-01449, Paper 11,
`Petitioner’s Reply to Preliminary Response
`
`Institution
`
`Intel Corp. v. FG SRC LLC, IPR2020-01449, Paper 13, Granting
`Institution of Inter Partes Review
`
`MTA
`
`Resp.
`
`Opp.
`
`Intel Corp. v. FG SRC LLC, IPR2020-01449, Paper 26, Patent
`Owner’s Motion to Amend
`
`Intel Corp. v. FG SRC LLC, IPR2020-01449, Paper 34, Patent
`Owner’s Response to Petition
`
`Intel Corp. v. FG SRC LLC, IPR2020-01449, Paper 36,
`Petitioner’s Opposition to Patent Owner’s Motion to Amend
`
`Guidance
`
`Intel Corp. v. FG SRC LLC, IPR2020-01449, Paper 38,
`Preliminary Guidance on Patent Owner’s Motion to Amend.
`
`NOTE ON EMPHASIS: All emphasis in the brief is added unless otherwise
`indicated.
`
`vi
`
`
`
`
`
`I.
`
`Introduction
`
`Patent Owner (PO) largely repeats—word-for-word—its POPR.
`
`PO’s threshold argument against the printed publication status of Zhang,
`
`Gupta, and Chien is identical to its POPR and thus fails to address the Institution
`
`Decision’s detailed analysis, Petitioner’s supplemental information, or the
`
`witnesses’ testimony. Evidence amassed from multiple libraries and witnesses
`
`(including author and publisher) establishes that each was publicly available
`
`through conference attendance, libraries, and IEEE Xplore before the critical date.
`
`PO’s disputes on the combinations’ disclosures reduce to the same four
`
`issues. First, PO again argues Zhang teaches a static CPU and away from a
`
`“reconfigurable processor” because applications remain in software. But Zhang
`
`teaches integrating programmable logic into its “processing elements” to adapt
`
`hardware to match an application, and that is not precluded by maintaining
`
`applications in software. Second, PO again contends Zhang’s expressly named
`
`“prefetch unit” does not prefetch, rather it fetches after a read miss. But Zhang’s
`
`teachings show its prefetcher meets the agreed construction of “data prefetch unit”
`
`and obtains data before it is needed. Third, PO again contends Zhang’s prefetcher
`
`does not meet the “only” limitations because the retrieved data is already
`
`optimized and speculative, and newly argues that Zhang’s last cache line includes
`
`extraneous data. But Zhang teaches retrieving “only used fields of matrix elements
`
`1
`
`
`
`
`
`during a given computation,” and PO’s new “last line” argument is contradicted by
`
`Zhang’s second case study and the expert testimony that PO cites. Fourth, PO
`
`again argues the combination’s first memory is fixed and not configurable. But
`
`Zhang and Gupta teach integrating programmable logic into the memory
`
`components (including L1 cache) to achieve reconfigurability, and cache line size
`
`is not limited to the examples in Zhang’s Table 1, as PO contends.
`
`Finally, PO’s secondary considerations arguments are identical to those in
`
`its POPR and do not address the Institution’s analysis. As before, PO fails its
`
`burden by not showing a nexus with the claimed systems and method.
`
`Accordingly, for the reasons below and stated in the Petition, claims 1-19 of
`
`the ’867 patent should be cancelled as obvious under the instituted grounds.
`
`II.
`
`PO’s constructions should not be adopted
`
`PO gives no persuasive reason for the Board to revisit the same two
`
`constructions that the Board and district court both declined to adopt. Resp. 31-33;
`
`Institution 25-26; POPR 37-38. First, PO does not rely on those constructions to
`
`overcome prior art. PO recites its construction in each section, but its analyses of
`
`the claims and instituted combinations are based on the claim language itself and
`
`do not hinge on the construction. See Resp. 40-44 (contending Zhang “does not
`
`disclose loading ‘only data required for the algorithm’”), 54-55 (same). PO’s
`
`expert does not rely on (or even recite) PO’s constructions either. E.g., EX1044
`
`2
`
`
`
`
`
`28:18-29:5, 32:10-14, 107:19-108:7. Thus, a construction is not necessary to
`
`resolve the parties’ dispute as to the instituted proceeding. Institution 26.
`
`Second, PO proposes these constructions, much like its proposed
`
`amendments, for the improper purpose of fixing its failed infringement theory. See
`
`Opp. 2-6, 18-20. PO proposed the same constructions in district court, arguing that
`
`despite these “only” limitations, the data prefetch unit may retrieve or read other
`
`data or instructions in addition to computational data required by the algorithm.
`
`See EX1033; EX1038 8-15. The court rejected those arguments with constructions
`
`that afford “only” its ordinary meaning and preclude the data prefetch unit from
`
`retrieving or reading other data or instructions from the claimed memory. EX1033.
`
`PO thereafter confirmed to the district court that “[PO] (and [Petitioner]) believe
`
`the Court’s construction precludes a finding of infringement, so there is no basis to
`
`move forward unless either the claims construction is changed or the claims are
`
`amended.” EX1036; see also EX1035. Both the Board and the district court
`
`correctly declined to rewrite claim language in a manner that PO has since revealed
`
`was designed to overcome non-infringement.
`
`Finally, PO’s constructions are unsupported by intrinsic evidence.
`
`Institution 25-26. PO quotes specification language that refers to “delivering only
`
`requested data,” Resp. 32, which is consistent with other examples. E.g., EX1001
`
`7:23-25, 8:3-8, 8:22-28. But contrary to PO’s suggestion, these examples do not
`
`3
`
`
`
`
`
`use “only” to merely distinguish from retrieving other computational data. Rather,
`
`they use “only” to distinguish from moving any other data or instruction besides
`
`the data required for computation. E.g., id. 9:27-40 (efficiency gains achieved by
`
`“delivering only requested data” and “eliminating the need to transfer an index
`
`array”); see also EX1017 4-5 (overhead reduced because “no instruction traffic”).
`
`Indeed, PO added these limitations during prosecution to overcome a rejection
`
`based on art that retrieved a configuration vector. E.g., EX1002-185 (rejection
`
`based on Paulraj’s “reconfiguration unit 106,” which retrieves a configuration
`
`vector), 197-99 (amending to add “only” limitations), 231 (relying on “only”
`
`limitations in Notice of Allowance). Thus, to the extent constructions are adopted
`
`on these terms, they should be consistent with the intrinsic record as reflected by
`
`the district court’s constructions. See EX1033.
`
`III. Zhang, Gupta, and Chien are prior art
`
`PO’s argument against Zhang, Gupta, and Chien as prior art is word-for-
`
`word identical to its POPR argument despite the Institution Decision’s thorough
`
`analysis, Petitioner’s supplemental information after institution, and PO’s cross
`
`examination of the witnesses. Compare Resp. 19-29 with POPR 26-35; see also
`
`Institution 34-44; Paper 21; Paper 27; EX1027-EX1031; Papers 28-30. As
`
`established in the Petition, analyzed at institution, and further confirmed by
`
`supplemental information, each was publicly accessible before June 18, 2003.
`
`4
`
`
`
`
`
`First, each reference bears “multiple conventional indicia of publication and
`
`public accessibility prior to the critical date, such as copyright date, ISBN number
`
`and IEEE order plan catalog number, price, indicia of publication by an established
`
`publisher, IEEE, and instructions for ordering additional copies.” Institution 41;
`
`e.g., EX1003-12; EX1004-8; EX1005-7. Those indicia support public accessibility.
`
`VidStream LLC v. Twitter, Inc., 981 F.3d 1060, 1065 (Fed. Cir. 2020); Hulu, LLC
`
`v. Sound View Innovations, LLC, IPR2018-01039, Paper 29 17-18 (Dec. 20, 2019)
`
`(precedential).
`
`Second, evidence establishes each was publicly available to conference
`
`attendees years before the critical date. Dr. Gupta, who authored or co-authored the
`
`references, confirms that each was distributed by the last day of its respective
`
`conference. EX1030 ¶¶4-5, 7-8, 10-11. That is consistent with IEEE’s standard
`
`practices at the time, which IEEE confirms were followed at these conferences.
`
`EX1027 ¶¶11-13; EX1040 21:11-19; see also EX1030 ¶3; EX1039 12:18-13:9.
`
`PO’s recycled argument that Dr. Gupta lacks personal knowledge ignores both his
`
`subsequent testimony confirming, based on personal knowledge, each article’s
`
`distribution, see EX1030 ¶¶4-5, 7-8, 10-11; EX1039 at 11:7-23, 23:6-18, as well as
`
`IEEE’s corroboration, EX1027 ¶¶11-13.
`
`Third, evidence establishes each was publicly available in libraries before
`
`the critical date. Mr. Munford, an expert in library sciences, analyzed and
`
`5
`
`
`
`
`
`compared physical copies and MARC records from numerous libraries and
`
`concludes each reference’s public availability. EX1031 ¶¶21-35 (Zhang available
`
`shortly after November 18, 1997), ¶¶37-51 (Gupta available shortly after May 15,
`
`2000), ¶¶54-69 (Chien available shortly after November 18, 1996).
`
`PO argues first that the MARC records identify only the conference’s name
`
`or subject, not the referenced paper. Resp. 27-28. But as the Board noted, it is
`
`reasonable to expect that catalogued proceedings include the entire document (i.e.,
`
`all conference papers, including each of Petitioner’s references), particularly in
`
`view of MARC code 300 and the referenced pagination. Institution 42-43; see also
`
`EX1012 ¶¶23, 28, 30, 32, 36, 38, 42, 46 (761-page proceeding including Zhang,
`
`161-page proceeding including Gupta, 372-page proceeding including Chien);
`
`EX1031 ¶¶28, 46; EX1003-11 (“Author Index” at 758); EX1004-7 (“Author
`
`Index” at 161); EX1005-6 (“Author Index” at 371). Moreover, Mr. Munford
`
`retrieved physical copies corresponding to the MARC records and confirmed that
`
`each reference is included. EX1031 ¶¶22, 32, 38, 46, 49, 54, 55, 66, 67.
`
`PO also argues that a MARC record’s catalogue date is insufficient because
`
`shelving could occur later, manufacturing a purported 5-6 year “margin of error”
`
`using Chien’s upload date to IEEE Xplore. Resp. 28. But Mr. Munford testifies
`
`that, in his experience and expert opinion, these materials are generally available
`
`for distribution between one and ten weeks after MARC record creation. See
`
`6
`
`
`
`
`
`EX1031 ¶14; EX1012 ¶13. And evidence supports that determination here, such as
`
`a physical Zhang copy with a handwritten date one week after its MARC record,
`
`EX1031 ¶35, and a library that catalogued Chien’s journal as a periodical,
`
`indicating the library would have received and made available each new journal
`
`edition soon after release, id. ¶69. PO’s “margin of error” also fails because (i) the
`
`upload process to Xplore is unrelated to an individual library’s shelving practices;
`
`and (ii) Xplore did not exist until after the first two conferences. See EX1040
`
`22:19-21, 30:4-6 (IEEE Xplore live around 1999); EX1039 at 25:14-20 (same); see
`
`also EX1040 29:7-12 (all three references likely received and processed together,
`
`explaining common upload date). Moreover, Mr. Munford’s expert testimony on
`
`shelving practices is unrebutted and not overcome by PO’s attorney-speculation
`
`that every referenced library took 3-5 years to shelve the proceedings.
`
`Finally, evidence establishes that each was publicly available through IEEE
`
`Xplore by August 6, 2002. E.g., EX1027 ¶10; id. 6, 16, 24; see also EX1040
`
`20:18-21:10, 23:9-19, 25:2-22, 26:15-27:6. As the Board noted, PO “does not
`
`appear to dispute that [each was] available on the IEEE website as of August 6,
`
`2002.” Institution 43 (quoting POPR 28, 31); see Resp. 21, 25 (same statements).
`
`Although PO contends the references were not meaningfully indexed, Resp. 20,
`
`24-25, “indexing is not ‘a necessary condition for a reference to be publicly
`
`accessible.’” Voter Verified, Inc. v. Premier Election Sols. Inc., 698 F.3d 1374,
`
`7
`
`
`
`
`
`1380 (Fed. Cir. 2012) (citation omitted); Institution 43. Moreover, PO ignores
`
`evidence demonstrating Xplore’s accessibility, indexing, and search functionality
`
`before the critical date. EX1031 ¶¶16, 78, 178 (June 5, 2001 Federal Register
`
`notice listing Patent Examiner resources), 207-11 (news articles from 2002
`
`confirming that IEEE Xplore included links, index terms, and search capability).
`
`The failure of PO’s purported “reasonable search ... using key concepts” is
`
`irrelevant because that is not the test. Institution 41-42 (quoting In re Lister, 583
`
`F.3d 1307, 1315 (Fed. Cir. 2009). The question is whether a diligent researcher
`
`could have located the references using Xplore’s searchable and indexed database,
`
`see id., and that is established with unrebutted evidence.
`
`IV. The instituted combinations render the claims obvious
`
`A.
`
`PO’s “teaching away” and “enabling disclosure” arguments fail
`
`PO raises the same general “teaching away” and lacking “enabling
`
`disclosures” arguments that the Board found unpersuasive at institution. Resp. 13-
`
`19, 33-35, 54; Institution 44-45, 49, 72; POPR 20-25, 38-39.
`
`PO’s “teaching away” arguments remain unavailing. As the Board
`
`recognized, PO’s arguments relate to purported non-disclosure, not criticism
`
`against modifying references to arrive at the claimed invention as the law requires.
`
`Institution 45. As explained in Part IV.B, infra, the asserted combinations teach a
`
`“MultiprocessOr with Reconfigurable Parallel Hardware” (MORPH) architecture
`
`8
`
`
`
`
`
`that uses a processor with reconfigurable components, including for its “processing
`
`elements,” to adapt hardware to match an application, and thus instantiates an
`
`application’s algorithm as hardware. Zhang’s “remains in software” statement is
`
`consistent with (and does not preclude) those teachings. Institution 44-45, 49.
`
`PO’s “enablement” argument also fails. First, as the Board recognized,
`
`under § 103, “a reference need not be enabled; it qualifies as prior art, regardless,
`
`for whatever is disclosed therein.” Institution 45 (quoting Amgen Inc. v. Hoechst
`
`Marion Roussel, Inc. 314 F.3d 1313, 1357 (Fed. Cir. 2003). Second, PO argues
`
`against Chen’s and Zhang’s self-enablement but ignores Gupta. Resp. 33, 54
`
`(citing EX2028 ¶¶65, 98). As PO and its expert concede, Gupta discloses a
`
`prototype of Zhang’s teaching, Resp. 12, 18; EX2028 ¶99, which is evidence of the
`
`combinations’ enablement. Third, each reference was refereed and accepted for
`
`presentation and publication in association with industry recognized conferences.
`
`See, e.g., EX1039 12:18-13:3; EX1030 48, 53; EX1031 69, 71-72, 222-23. Fourth,
`
`PO contends the technology disclosed by each was well-known at the time of the
`
`patent. Resp. 10-12. Fifth, each reference’s disclosure is commensurate in scope
`
`with the ’867 patent’s degree of disclosure. See EX1001. Finally, as demonstrated,
`
`the instituted combinations, taken as a whole, teach each limitation and enables a
`
`POSITA to practice the claimed inventions. Pet. 16-87.
`
`9
`
`
`
`
`
`B.
`
`The combination teaches the claimed “reconfigurable processor”
`
`PO again contends Zhang teaches a conventional “static” CPU rather than
`
`the “reconfigurable processor” of each challenged independent claim by using the
`
`same arguments the Board found unpersuasive at institution. Resp. 33-37; 51-54;
`
`see also id. 57; Institution 46-50, 63, 72-73; POPR 39-42, 52-54, 58. PO’s only
`
`addition is to now quote its expert’s opinion that Zhang teaches away from
`
`implementing any part of an application’s algorithm as hardware because its
`
`application remains in software. Resp. 35.
`
`PO’s arguments against Zhang’s reconfigurable processor remain
`
`unavailing. First, as the Board recognized, PO introduces requirements that are not
`
`commensurate with the claim scope or the agreed construction. E.g., Resp. 6, 12,
`
`16-17, 34-37 (requiring “fully” reconfigurable processor, to “replace” a
`
`microprocessor, “physical adaptation of the entire reconfigurable processor,”
`
`instantiating an “entire” algorithm); Institution 48. The agreed construction
`
`requires only “a computing device that contains reconfigurable components,” see
`
`EX1001 5:26-26, and the claim language recites a reconfigurable processor that
`
`instantiates an algorithm and some configurable components, id. claim 1 (“first
`
`memory and data prefetch unit” are “configured to conform”), claim 9 (“data
`
`prefetch unit” is “configured to conform”), claim 13 (“computational unit and the
`
`data access unit and the data prefetch unit” are “configured to conform”).
`
`10
`
`
`
`
`
`Consistent with these requirements, Petitioner has shown that the instituted
`
`combinations’ reconfigurable processor contains reconfigurable components,
`
`including each of these claimed components, e.g., Pet. 17-21, 24-25, 46-49, 67-68,
`
`85, and that the reconfigurable processor instantiates an algorithm (e.g., matrix
`
`multiplication algorithms and prefetching algorithms) as hardware, id. 28-31, 42-
`
`43, 46-49, 51-53, 58-59, 64, 67-69, 84-85.
`
`Second, PO’s additional requirements conflict with intrinsic evidence. For
`
`example, PO argues the patent’s invention “replace[s]” a microprocessor to suggest
`
`it precludes use with conventional CPUs. Resp. 17, 19, 34. But the patent teaches
`
`using its reconfigurable processors (RPs) with a conventional system. EX1001
`
`6:19-25; see also id. claim 7. And both experts agree the patent’s disclosure
`
`contemplates using the invention with a conventional CPU. E.g., EX1044 41:22-
`
`44:9; EX1043 35:2-37:3. In addition, the applicants tried similar arguments during
`
`prosecution, asserting that Paulraj’s “reconfigurable cache” was not a
`
`reconfigurable processor, nor did Paulraj suggest “replac[ing] the CPU with a
`
`reconfigurable processor that can instantiate an algorithm as hardware.” EX1002-
`
`131 (emphasis original). But the Examiner maintained the rejection, stating that
`
`Paulraj’s processor contained memory components that were reconfigured based
`
`on the application that is to execute on the processor. Id.-146; see also id.-105
`
`(prior rejection noting reconfigurable system was within Paulraj’s CPU). The
`
`11
`
`
`
`
`
`applicants subsequently argued against Paulraj on other limitations. Id. 165-71,
`
`197-201.
`
`Third, PO mischaracterizes Zhang as disclosing a “static” “conventional”
`
`CPU incapable of instantiating an algorithm as hardware, arguing as before that
`
`Zhang teaches only “application specific hardware instantiations for the cache,
`
`network, and memory interfaces” and not processing elements. Resp. 44-48. PO is
`
`first wrong to focus its analysis only on Zhang’s CPU-labeled block alone rather
`
`than the reconfigurable processor that Petitioner and Dr. Shanfield identified with a
`
`pink box like in the example below:
`
`
`
`E.g., Pet. 17-18, 25-26, 28-30 (describing and illustrating Zhang’s reconfigurable
`
`processor in various figures with a pink box including first memory, second
`
`memory, and prefetcher in addition to blocks labeled “CPU” or “processor”);
`
`EX1006 ¶¶125, 128-31. As PO’s expert agreed, that box includes reconfigurable
`
`12
`
`
`
`
`
`components. EX1044 83:16-85:24. It therefore meets the agreed construction of a
`
`reconfigurable processor. See Pet. 17-18, 25-26, 28-30.
`
`PO is also wrong to contend that Zhang’s processing elements are not
`
`reconfigurable. Resp. 15-17, 34-37. Zhang expressly discloses integrating
`
`programmable logic into the processing elements, which Zhang identifies
`
`separately from the memory hierarchy, scalable interconnect, and network
`
`interface:
`
`We propose an architecture that integrates small blocks of
`
`programmable logic into key elements of a baseline architecture,
`
`including processing elements, components of the memory
`
`hierarchy, and the scalable interconnect, to provide architectural
`
`adaptation—the customization of architectural mechanisms and
`
`policies to match an application.
`
`EX1003-13 C2:44-49 (italic in original); id. Fig. 2 (illustrating programmable logic
`
`within the CPU, cache, network interface, and memory); Pet. 28-30. As PO’s
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`expert conceded, Zhang’s disclosure of integrating programmable logic into the
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`processing elements includes taking “portions of the actual conventional CPU and
`
`making that implemented with programmable logic.” EX1044 80:14-82:16. Dr.
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`Shanfield agrees. EX1043 25:16-26:22. Thus, Zhang’s processing elements—
`
`whether labeled “processor” or “CPU”—are indeed reconfigurable.
`
`13
`
`
`
`
`
`Finally, Zhang teaches optimizing matrix multiplication computations using
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`the customization provided by its programmable logic to improve computational
`
`processing. Pet. 17-19, 42-43, 46, 64, 67-68; e.g., EX1003-12 C1:28-31, C2:39-45.
`
`Zhang’s reconfigurable processor therefore contains reconfigurable components
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`and can instantiate an algorithm as hardware. Institution 49-50. Thus, Zhang’s
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`reconfigurable processor is not a static, conventional CPU as PO contends.
`
`Fourth, as the Board recognized, PO’s argument that Zhang teaches away
`
`from implementing an application’s algorithms as hardware because the
`
`“application remains in software” is unpersuasive. Resp. 16, 19, 34-36, 52;
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`Institution 49. Nothing about that statement precludes compiling one (or more) of
`
`an application’s algorithms and instantiating it as hardware. Indeed, that is entirely
`
`consistent with the ’867 patent, which teaches taking an application’s software
`
`(e.g., in C or Fortran) and compiling “carve-outs” into direct execution logic
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`(DEL) that gets loaded into the reconfigurable processor. EX1001 6:47-57;
`
`EX1044 53:4-9, 54:11-22; EX1043 64:23-66:24, 68:12-70:17. But as PO’s expert
`
`agrees, that software is not removed or deleted after compilation; it will still exist
`
`in memory. EX1044 57:24-58:19, 60:25-61:9; see also EX1043 64:23-66:24,
`
`68:12-70:17. Thus, a POSITA reads the ’867 patent to also allow the application to
`
`remain in software.
`
`14
`
`
`
`
`
`Zhang’s statement merely distinguishes its approach from conventional co-
`
`processing architectures that must repartition hardware and software functionality
`
`and reimplement the co-processing hardware every time a new application is run.
`
`See EX1003-12 C1:23-33, C1:47-C2:36. Zhang maintains the application in
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`software to use “architectural adaptation … in the bindings, mechanisms, and
`
`policies on the interaction of processing, memory, and communication resources
`
`while keeping the macro-level organization the same and thus preserving the
`
`programming model for developing applications.” EX1003-13 C2:50-53, -14 C1:2.
`
`But Zhang also teaches reconfiguring key elements of its architecture using
`
`reprogrammable logic to match an application. Pet. 28-30; EX1003-13 C2:44-49.
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`Thus, Zhang both maintains its application in software and reconfigures its
`
`hardware to match an application using programmable logic.
`
`Moreover, PO’s contention that Zhang’s statement somehow precludes
`
`implementing any part of an application’s algorithms in hardware is belied by its
`
`own argument, which concedes that Zhang (and Chien and Gupta) teach the “use
`
`of reconfigurable logic … to implement reconfigurable logic in ‘support’
`
`algorithms.” Resp. 13. Thus, Zhang does not preclude or teach away from
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`instantiating an algorithm as hardware.
`
`Fifth, as the Board recognized, PO’s renewed contention that Zhang teaches
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`only application-class-specific adaptations is unpersuasive. Institution 49-50; Resp.
`
`15
`
`
`
`
`
`37. Zhang repeatedly emphasizes that its adaptations “match an application,” are
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`“application-specific” and achieve performance improvements “on a per
`
`application basis.” EX1003-12 to -14; Pet. 28-30. Thus, Zhang teaches application-
`
`specific adaptations.
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`C. The combination teaches the claimed “data prefetch unit”
`
`PO argues again that, despite its name, Zhang’s prefetch unit cannot satisfy
`
`the “data prefetch unit” of each independent claim because it purportedly only
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`post-fetches data after a cache read miss; the Board found this unpersuas
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