505881821
`
`01/24/2020
`
`PATENT ASSIGNMENT COVER SHEET
`
`Electronic Version v1.1
`Stylesheet Version v1.2
`
`EPAS ID: PAT5928646
`
`SUBMISSION TYPE:
`
`NEW ASSIGNMENT
`
`NATURE OF CONVEYANCE:
`
`ASSIGNMENT
`
`CONVEYING PARTY DATA
`
`DIRECTSTREAM LLC
`
`RECEIVING PARTY DATA
`
`Execution Date
`
`01/22/2020
`
`
`
`Property Type amber
`
`NomeCPGSROUSOOS
`
`PROPERTY NUMBERS Total: 42
`
`505881821
`
`tel Exhibit 1044 «4
`
`PATENT
`REEL: 051615 FRAME: 0344
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`Intel Exhibit 1041 - 1
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`

`

`[PropertyType[Number
`
`CORRESPONDENCE DATA
`
`AddressLine 2:
`
`AddressLine 4:
`
`SUITE 1000
`
`MINNEAPOLIS, MINNESOTA 55437
`
`source=Patent Assignment DS to FG SRC#paget.tif
`
`(952)896-3333
`Fax Number:
`Correspondencewill be sent to the e-mail addressfirst; if that is unsuccessful, it will be sent
`using a fax number,if provided; if that is unsuccessful, it will be sent via US Mail.
`Phone:
`952-896-3295
`Email:
`ipgroup@larkinhoffman.com
`Correspondent Name:
`TODD R. FRONEK
`AddressLine1:
`8300 NORMAN CENTER DRIVE
`
`NAME OF SUBMITTER
`
`TODD R. FRONEK
`
`SIGNATURE:
`
`DATE SIGNED:
`
`Total Attachments: 7
`
`/Todd R. Fronek/
`
`01/24/2020
`
`PATENT
`REEL: 051615 FRAME: 0345
`
`Intel Exhibit 1041 - 2
`
`

`

`source=Patent Assignment DS to FG SRC#pagez.tif
`source=Patent Assignment DS to FG SRC#page3.tif
`source=Patent Assignment DS to FG SRC#page4.tif
`source=Patent Assignment DS to FG SRC#page5d.tif
`source=Patent Assignment DS to FG SRC#page6.tif
`
`source=Patent Assignment DS to FG SRC#page7.tif
`
`Intel Exhibit 1041 - 3
`
`PATENT
`REEL: 051615 FRAME: 0346
`
`Intel Exhibit 1041 - 3
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`

`

`Patent Assignment Agreement
`
`THIS PATENT ASSIGNMENT AGREEMENTisenteredinto on January 22, 2020 by and
`between DirectStream LLC, a Delawarelimitedliability company (Assignor) and FG SRC LLC,
`a Delaware limited liability company (Assignee).
`
`WHEREAS,Assignoris the sole and exclusive ownerofthe U.S. Patents and pendingpatent
`applications identified in Schedule A (the “Patents”); and
`
`WHEREAS,Assignee desires to acquire all rights, title and interest in and to the Patents;
`
`NOW, THEREFORE,the parties agree as follows:
`
`1. Assignment. Be it knownthat for good and valuable consideration, the receipt and
`sufficiency of which is hereby acknowledged, Assignor hereby irrevocably conveys,
`transfers, and assigns to Assignee, and Assignee hereby accepts, all of Assignor’s right,
`title, and interest in and to the following
`
`(a) the patents and patent applications set forth in Schedule A
`hereto andall issuances, divisions, continuations,
`continuations-in-part, reissues, extensions, reexaminations,
`and renewals thereof(the “Patents”);
`
`(bNee
`
`(c)
`
`(d~~
`
`all rights of any kind whatsoever of Assignor accruing
`under any of the foregoing provided by applicable law of
`any jurisdiction, by international treaties and conventions,
`and otherwise throughoutthe world;
`
`any andall royalties, fees, income, payments, and other
`proceeds now orhereafter due or payable with respect to
`any andall of the foregoing, past, present and future; and
`
`any and all claims and causesof action with respect to any
`of the foregoing, whether accruing before, on,or after the
`date hereof, includingall rights to and claims for damages,
`restitution, and injunctive and otherlegal and equitable
`relief for past, present, and future infringement,
`misappropriation, violation, misuse, breach, or default,
`with the right but no obligation to sue for such legal and
`equitable relief and to collect, or otherwise recover, any
`such damages.
`
`2. Covenants. Assignor covenants and agrees and warrants that it has a full and
`unencumberedtitle to the invention hereby assigned, and further covenants and agrees
`that it has the right to grant such rights to said Patents andthat it will, at any time upon
`request without cost or further compensation, execute and deliver any andall papers or
`instruments that, in the opinion of the Assignee, may be necessary or desirable to secure
`
`4835-8327-4159 v.4
`
`Intel Exhibit 1041 - 4
`
`PATENT
`REEL: 051615 FRAME: 0347
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`Intel Exhibit 1041 - 4
`
`

`

`said Assignee the full enjoyment ofthe rights and properties herein conveyedor intended
`to be conveyed bythis instrument.
`
`3. Recordation and Further Actions. Assignor hereby authorizes the Commissioner for
`Patents in the United States Patent and Trademark Office to record andregister this
`Patent Assignment upon request by Assignee. Following the date hereof, Assignorshall
`take such steps and actions, and provide such cooperation and assistance to Assignee and
`its successors, assigns, and legal representatives, including the execution anddelivery of
`any affidavits, declarations, oaths, exhibits, assignments, powers ofattorney, or other
`documents, as may be necessary to effect, evidence, or perfect the assignment ofthe
`Assigned Patents to Assignee, or any assignee or successorthereto.
`
`4. Counterparts. This Patent Assignment Agreement maybe executed in counterparts,
`each of which shall be deemedan original, but all of which together shall be deemed one
`and the same agreement. A signed copy of this Patent Assignment Agreement delivered
`by facsimile, e-mail, or other meansofelectronic transmission shall be deemed to have
`the same legal effect as delivery of an original signed copy of this Patent Assignment
`Agreement.
`
`5. Successors and Assigns. This Patent Assignmentshall be binding upon andshall inure to
`the benefit of the parties hereto and their respective successors and assigns.
`
`6. Governing Law. This Patent Assignmentand any claim, controversy, dispute, or cause
`of action (whether in contract, tort, or otherwise) based upon,arising out of, or relating to
`this Patent Assignment Agreementandthe transactions contemplated herebyshall be
`governedby, and construed in accordance with, the laws of the United States and the
`State of Delaware, without giving effect to any choiceor conflict of law provision or rule
`(whether of the Delaware or any other jurisdiction).
`
`4835-8327-4159 v.4
`
`Intel Exhibit 1041 - 5
`
`PATENT
`REEL: 051615 FRAME: 0348
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`Intel Exhibit 1041 - 5
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`

`

`IN WITNESS WHEREOF,Assignorhas duly executed and delivered this Patent Assignment as
`of the date first above written.
`
`AGREED TO AND ACCEPTED:
`
`
`DirectStream,L
`
`Signature:
`
`:
`Todd Rooke¥ CEO
`
`/
`
`
`
`
`
`Date: January 22, 2020
`
`AGREED TO AND ACCEPTED:
`
`FG SRC, LLC
`
`Signature:
`
`Brandon Freeman, Manager
`
`Date: January 22, 2020
`
`4835-8327-4159 v.4
`
`Intel Exhibit 1041 - 6
`
`PATENT
`REEL: 051615 FRAME: 0349
`
`Intel Exhibit 1041 - 6
`
`

`

`IN WITNESS WHEREOF,Assignorhas duly executed and delivered this Patent Assignment as
`of the date first above written.
`
`AGREED TO AND ACCEPTED:
`
`DirectStream, LLC
`
`Signature:
`
`Todd Rooke, CEO
`
`Date: January 22, 2020
`
`AGREED TO AND ACCEPTED:
`
`FG SRC, LLC
`
`Signature:__“FS.ggseux'
`‘
`
`Brandon Freemafi, Manager
`
`Date: January 22, 2020
`
`4835-8327-4159 v.4
`
`Intel Exhibit 1041 - 7
`
`PATENT
`REEL: 051615 FRAME: 0350
`
`Intel Exhibit 1041 - 7
`
`

`

`
`
`
`
`6,247,110
`
`6/12/2001
`
`Issued
`
`6,339,819
`
`1/15/2002
`
`6,594,736
`
`6,836,823
`
`6,941 539
`
`Issued
`
`8/13/2002
`
`7/15/2003
`
`12/28/2004
`9/6/2005
`
`Issued
`
`6,961,841
`
`11/1/2005
`
`Issued
`
`6,964,029
`
`11/8/2005
`
`Process for converting programsin high-level
`programming languagesto a unified executable for
`hybrid computing platforms
`System and method for providing an arbitrated
`memory bus in a hybrid computing system
`
`
`
`Issued
`
`6,983,456
`
`1/3/2006
`
`Issued
`
`6,996,656
`
`2/7/2006
`
`US.
`
`US.
`
`US.
`
`US.
`
`US.
`
`US.
`
`US.
`
`US.
`
`US.
`
`US.
`
`Schedule A
`
`
`
`
`eqs
`Patent
`
`Title NoJ/Serial|!ssued/Filing
`
`Jurisdiction
`Date
`
`No.
`
`
`
`System and method for dynamicpriority conflict
`
`resolution in a multi-processor computer system
`
`
`US. Issued having shared memory resources
`
`6,026,459
`2/15/2000
`
`
`
`
`Multiprocessor computer architecture incorporating a
`plurality of memory algorithm processors in the
`
`memory subsystem
`6,076,152
`6/13/2000
`
`
`
`
`Multiprocessor computer architecture incorporating a
`
`plurality of memory algorithm processorsin the
`
`memory subsystem
`Issued
`
`
`Split directory-based cache coherency technique for a
`
`
`Issued
`multi-processor computer system
`6,295,598
`9/25/2001
`
`
`
`Multiprocessor with each processor element
`accessing operandsin loaded input buffer and
`
`forwarding results to FIFO output buffer
`
`
`
`
`System and method for accelerating web site access
`and processing utilizing a computer system
`
`
`incorporating reconfigurable processors operating
`
`under a single operating system image
`Issued
`6,434,687
`
`System and method for semaphore and atomic
`operation managementin a multiprocessor
` Bandwidth enhancementfor uncached devices
`
`
`Efficiency of reconfigurable hardware
`
`
`Multiprocessor computerarchitecture incorporating a
`plurality of memory algorithm processors in the
`memory subsystem
`System and methodfor partitioning control-dataflow
`graph representations
`
`
`
`Computer system architecture and memory controller
`for close-coupling within a hybrid processing system
`utilizing an adaptive processorinterface port
`
`
`
`7,003,593
`
`2/21/2006
`
`
`
`
`
`System and method for explicit communication of
`messages between processes running on different
`
`US.
`nodes in a clustered multiprocessor system
`Issued
`7,124,211
`10/17/2006
`
`
`
`|_US._|Map compiler pipelined loop structure
`US.
`System and methodof enhancing efficiency and
`utilization of memory bandwidth in reconfigurable
`U.S.
`hardware
`Issued
`7,149,867
`
`12/12/2006
`
`4835-8327-4159 v.4
`
`Intel Exhibit 1041 - 8
`
`PATENT
`REEL: 051615 FRAME: 0351
`
`Intel Exhibit 1041 - 8
`
`

`

`
`ers
`Patent
`Status
`No./Serial
`Issued/Filing
`
`
`Title
`Date
`
`No.
`
`
`Interface for integrating reconfigurable processors
`into a general purpose computing system
`
`Debugging and performanceprofiling using control-
`dataflow graph representations with reconfigurable
`hardware emulation
`Interface for integrating reconfigurable processors
`into a general purpose computing system
`Switch/network adapter port coupling a
`reconfigurable processing element to one or more
`microprocessors for use with interleaved memory
`controllers
`
`
`
`
`Issued
`
`7,155,602
`
`12/26/2006
`
`Issued
`
`7,155,708
`
`12/26/2006
`
`Issued
`
`7,167,976
`
`1/23/2007
`
`
`
`7,197,575
`
`3/27/2007
`
`6/26/2007
`
`
`
`
`
`
`
`Jurisdiction
`
`q n
`
`U.S
`
`S
`
`wn
`
`~
`
`n
`
`q a
`
`q
`
`cq w”
`
`4835-8327-4159 v.4
`
`
`
`
` te
`
`
`
`Multiprocessor computer architecture incorporating a
`plurality of memory algorithm processorsin the
`
`memory subsystem
`Issued
`
`System and method for converting control flow graph
`representations to control-dataflow graph
`representations
`
`Switch/network adapter port for clustered computers
`employing a chain of multi-adaptive processors in a
`dual in-line memory module format
`
`Multi-adaptive processing systems and techniques for
`enhancing parallelism and performance of
`computational functions
`
`
`Issued
`
`
`7,225,324
`
`3/29/2007
`
`7,237,091
`
`7,299,458
`
`11/20/2007
`
`
`
`
`
`
`
`Reconfigurable processor elementutilizing both
`coarse and fine grained reconfigurable elements
`
`Issued
`
`7,406,573
`
`7/29/2008
`
`Issued
`
`7,373,440
`
`5/13/2008
`
`Switch/network adapter port for clustered computers
`
`
`employing a chain of multi-adaptive processors in a
`
`dual in-line memory module format
`
`
`Switch/network adapter port incorporating shared
`memory resourcesselectively accessible by a direct
`
`
`execution logic element and one or more denselogic
`
`devices
`
`
`Switch/network adapter port coupling a
`reconfigurable processing element to one or more
`
`
`microprocessors for use with interleaved memory
`
`
`G
`controllers
`Multi-adaptive processing systems and techniques for
`enhancing parallelism and performance of
`
`
`
`q
`computational functions
`
`Switch/network adapter port incorporating shared
`memory resourcesselectively accessible by a direct
`
`execution logic element and one or more denselogic
`
`
`devices in a fully buffered dual in-line memory
`
`module format (FB-DIMM)
`
`
`
`
`Process for converting programs in high-level
`programming languages to a unified executable for
`
` q ~
`
`hybrid computing platforms
`
`
`
`7,421,524
`
`9/2/2008
`
`7,424,552
`
`9/9/2008
`
`7,565,461
`
`7/21/2009
`
`7,620,800
`
`11/17/2009
`
`7,680,968
`
`3/16/2010
`
`7,703,085
`
`4/20/2010
`
`Intel Exhibit 1041 - 9
`
`PATENT
`REEL: 051615 FRAME: 0352
`
`Intel Exhibit 1041 - 9
`
`

`

`U.S.
`
`processor computer system having shared resources
`
`Issued
`
`effects
`System and method for computational unification of
`
`Issued
`
`8,589,666
`
`11/19/2013
`
`
`
`USS.
`
`Issued
`
`8,713,518
`
`4/29/2014
`
`1/6/2015
`
`3/27/2014
`
`
`
`
`Patent
`
`
`Issued/Filing
`
`No./Serial
`Date
`Title
`
`
`
`
`No.
`
`
`us Dynamicpriorityconflictresolutioninamulti-
`
`
`
`
`7,890,686
`2/15/2011
`Lous|Elimination ofstream consumerloop overshoot|sssued|US.
`
`
`So heterogeneousimplicitandexplicitprocessing
`
`
`
`
`elements
`
`
`System and method for computational unification of
`
`heterogeneous implicit and explicit processing
`
`
`
`
`elements
`
`
`
`8,930,892
`
`
`System and method for retaining DRAM data when
`
`reprogramming reconfigurable devices with DRAM
`
`
`memory controllers
`9,153,311
`
`
`
`System and method for retaining dram data when
`
`
`reprogramming reconfigurable devices with DRAM
`
`
`
`
`
`
`memory controllers incorporating a data maintenance
`
`
`
`12/27/2016
`block colocated with a memory module or subsystem
`
`
`
`
`
`System and method for retaining DRAM data when
`
`
`reprogramming reconfigurable devices with DRAM
`
`memory controllers incorporating a data maintenance
`
`block colocated with a memory module or subsystem
`
`
`Issued
`
`9,530,483
`
`9,727,269
`
`
`
`
`
`8/8/2017
`
`
`
`System and method for thermally coupling memory
`devices to a memory controller in a computer
` 12/19/2017
`
`
`memory board
`
`
`
`
`Mobile electronic devices utilizing reconfigurable
`processing techniques to enable higher speed
`
` 2/2/2012
`applications with lowered power consumption
`Ss.
`
`
`
`Multi-processor computer architecture incorporating
`5/28/2013
`
`US. Pending|13/903,720distributed multi-ported common memory modules
`
`
`
`
`Pending
`
`13/365,090
`
`4835-8327-4159 v.4
`
`RECORDED: 01/24/2020
`
`Intel Exhibit 1041 - 10
`
`PATENT
`REEL: 051615 FRAME: 0353
`
`Intel Exhibit 1041 - 10
`
`