505881821
`
`01/24/2020
`
`PATENT ASSIGNMENT COVER SHEET
`
`Electronic Version v1.1
`Stylesheet Version v1.2
`
`SUBMISSION TYPE:
`
`NEW ASSIGNMENT
`
`NATURE OF CONVEYANCE:
`
`ASSIGNMENT
`
`CONVEYING PARTY DATA
`
`DIRECTSTREAM LLC
`
`RECEIVING PARTY DATA
`
`EPAS ID: PAT5928646
`
`Execution Date
`
`01/22/2020
`
`Nome
`
`OOS
`
`PROPERTY NUMBERS Total: 42
`
`Property Type amber
`
`REEL: 051615 FRAME: 0344
`
`505881821
`
`tel Exhibit 1044 «4
`
`PATENT
`
`Intel Exhibit 1041 - 1
`
`

`

`[PropertyType[Number
`
`CORRESPONDENCE DATA
`
`Email:
`Correspondent Name:
`AddressLine1:
`
`AddressLine 2:
`
`AddressLine 4:
`
`ipgroup@larkinhoffman.com
`TODD R. FRONEK
`
`8300 NORMAN CENTER DRIVE
`
`SUITE 1000
`
`MINNEAPOLIS, MINNESOTA 55437
`
`Fax Number:
`(952)896-3333
`Correspondencewill be sent to the e-mail addressfirst; if that is unsuccessful, it will be sent
`a fax number,if provided;
`if that is unsuccessful, it will be sent via US Mail.
`using
`Phone:
`952-896-3295
`
`source=Patent Assignment DS to FG SRC#paget.tif PATENT
`
`NAME OF SUBMITTER
`
`TODD R. FRONEK
`
`SIGNATURE:
`
`DATE SIGNED:
`
`Total Attachments: 7
`
`/Todd R. Fronek/
`
`01/24/2020
`
`REEL: 051615 FRAME: 0345
`
`Intel Exhibit 1041 - 2
`
`

`

`source=Patent Assignment DS to FG SRC#pagez.tif
`source=Patent Assignment DS to FG SRC#page3.tif
`source=Patent Assignment DS to FG SRC#page4.tif
`source=Patent Assignment DS to FG SRC#page5d.tif
`source=Patent Assignment DS to FG SRC#page6.tif
`
`source=Patent Assignment DS to FG SRC#page7.tif
`
`Intel Exhibit 1041
`
`3
`
`-
`
`PATENT
`
`REEL: 051615 FRAME: 0346
`
`Intel Exhibit 1041 - 3
`
`

`

`Patent
`
`Assignment Agreement
`
`THIS PATENT ASSIGNMENT AGREEMENTisenteredinto on
`January 22, 2020 by and
`a Delawarelimited
`between DirectStream LLC,
`liability company (Assignor) and FG SRC LLC,
`a Delaware limited
`liability company (Assignee).
`WHEREAS, Assignoris the sole and exclusive ownerofthe U.S. Patents and pendingpatent
`applications identified in Schedule A (the “Patents”); and
`
`WHEREAS,Assignee desires to
`
`acquire all rights, title and interest in and to the Patents;
`NOW, THEREFORE,the parties agree as follows:
`1.
`Be it knownthat for good and valuable consideration, the receipt and
`Assignment.
`sufficiency of which is hereby acknowledged, Assignor hereby irrevocably conveys,
`to
`transfers, and assigns
`Assignee, and Assignee hereby accepts, all of Assignor’s right,
`title, and interest in and to the
`following
`
`set forth in Schedule A
`(a) the patents and patent applications
`hereto andall issuances, divisions, continuations,
`continuations-in-part, reissues, extensions, reexaminations,
`and renewals thereof(the “Patents”);
`
`(bNee
`
`(c)
`
`(d~~
`
`all rights of any kind whatsoever of Assignor accruing
`under any of the foregoing provided by applicable law of
`any jurisdiction, by international treaties and conventions,
`and otherwise throughoutthe world;
`any andall royalties, fees, income, payments, and other
`now orhereafter due or
`payable with respect to
`proceeds
`any andall of the foregoing, past, present and future; and
`any and all claims and causesof action with respect to any
`on, or after the
`of the foregoing, whether accruing before,
`to and claims for damages,
`date hereof, includingall rights
`restitution, and injunctive and otherlegal and
`equitable
`relief for past, present, and future infringement,
`or
`misappropriation, violation, misuse, breach,
`default,
`to sue for such legal and
`with the right but no
`obligation
`or otherwise recover, any
`equitable relief and to collect,
`such damages.
`
`covenants and agrees and warrants that it has a full and
`2. Covenants.
`Assignor
`unencumberedtitle to the invention hereby assigned, and further covenants and agrees
`to said Patents andthat it will, at any time upon
`to grant such rights
`that it has the right
`request without cost or further compensation,
`execute and deliver any andall papers or
`Assignee, may be necessary or desirable to secure
`instruments that, in the
`opinion of the
`
`4835-8327-4159 v.4
`
`Intel Exhibit 1041
`
`4
`
`-
`
`PATENT
`
`REEL: 051615 FRAME: 0347
`
`Intel Exhibit 1041 - 4
`
`

`

`ofthe rights and properties herein conveyedor intended
`said Assignee the full enjoyment
`to be conveyed bythis instrument.
`
`3. Recordation and Further Actions. Assignor hereby authorizes the Commissioner for
`Patents in the United States Patent and Trademark Office to record and
`register this
`Patent Assignment upon request by Assignee. Following the date hereof, Assignorshall
`take such steps and actions, and provide such cooperation and assistance to
`Assignee and
`its successors, assigns, and legal representatives, including the execution and
`delivery of
`any affidavits, declarations, oaths, exhibits, assignments, powers of
`or other
`attorney,
`as may be necessary to effect, evidence,
`or
`ofthe
`perfect the assignment
`documents,
`or any assignee
`or successorthereto.
`Assigned Patents to
`Assignee,
`may
`4. Counterparts. This Patent Assignment Agreement
`be executed in counterparts,
`each of which shall be deemedan original, but all of which together shall be deemed one
`and the same
`agreement. A signed copy of this Patent Assignment Agreement delivered
`or other meansofelectronic transmission shall be deemed to have
`by facsimile, e-mail,
`the same
`legal effect as
`delivery of an
`original signed copy of this Patent
`Assignment
`Agreement.
`
`Assignmentshall be binding upon andshall inure to
`5. Successors and Assigns. This Patent
`successors and assigns.
`the benefit of the parties hereto and their respective
`6. Governing Law. This Patent Assignmentand any claim, controversy, dispute,
`of action (whether in contract, tort, or
`or
`out of,
`otherwise) based upon,arising
`relating
`andthe transactions contemplated herebyshall be
`this Patent Assignment Agreement
`governed by, and construed in accordance with, the laws of the United States and the
`State of Delaware, without giving effect to any choiceor conflict of law provision
`or rule
`(whether of the Delaware or
`any other
`jurisdiction).
`
`or cause
`
`to
`
`4835-8327-4159 v.4
`
`Intel Exhibit 1041
`
`5
`
`-
`
`PATENT
`
`REEL: 051615 FRAME: 0348
`
`Intel Exhibit 1041 - 5
`
`

`

`IN WITNESS WHEREOF,Assignorhas duly executed and delivered this Patent Assignment
`of the date first above written.
`
`as
`
`AGREED TO AND ACCEPTED:
`
`DirectStream,L
`
`
`Signature:
`
`
`
`/
`
`:
`
`Todd Rooke¥ CEO
`
`
`
`Date: January 22, 2020
`
`AGREED TO AND ACCEPTED:
`
`FG SRC, LLC
`
`Signature:
`
`Brandon Freeman, Manager
`
`Date:
`
`January 22, 2020
`
`4835-8327-4159 v.4
`
`Intel Exhibit 1041
`
`6
`
`-
`
`PATENT
`
`REEL: 051615 FRAME: 0349
`
`Intel Exhibit 1041 - 6
`
`

`

`IN WITNESS WHEREOF,Assignorhas duly executed and delivered this Patent Assignment
`of the date first above written.
`
`as
`
`AGREED TO AND ACCEPTED:
`
`DirectStream, LLC
`
`Signature:
`
`Todd Rooke, CEO
`
`Date:
`
`January 22, 2020
`
`AGREED TO AND ACCEPTED:
`
`FG SRC, LLC
`
`‘
`
`Signature:__“FS.ggseux'
`Brandon Freemafi, Manager
`
`Date:
`
`January 22, 2020
`
`4835-8327-4159 v.4
`
`Intel Exhibit 1041
`
`7
`
`-
`
`PATENT
`
`REEL: 051615 FRAME: 0350
`
`Intel Exhibit 1041 - 7
`
`

`

`Jurisdiction
`
`Title
`
`Schedule A
`
`Patent
`NoJ/Serial
`No.
`
`eqs
`!ssued/Filing
`Date
`
`US.
`
`US.
`
`US.
`
`US.
`
`US.
`
`US.
`
`US.
`
`US.
`
`US.
`
`US.
`
`US.
`
`
`
`US.
`US.
`
`8/13/2002
`
`7/15/2003
`
`12/28/2004
`
`9/6/2005
`
`11/1/2005
`
`
`
`Issued
`
`6,961,841
`
`Issued
`
`6,964,029
`
`11/8/2005
`
`Issued
`
`Issued
`
`
`
`
`
`6,983,456
`
`1/3/2006
`
`6,996,656
`
`2/7/2006
`
`7,003,593
`
`2/21/2006
`
`
`
`Issued
`
`7,124,211
`
`10/17/2006
`
`12/12/2006
`
`
`
`
`
`
`System and method for dynamicpriority conflict
`
`resolution in a
`
`multi-processor computer system
`
`having shared memory resources
`US.
`Issued
`2/15/2000
`6,026,459
`
`
`a
`
`Multiprocessor computer architecture incorporating
`
`
`plurality of memory algorithm processors in the
`
`
`memory subsystem
`6/13/2000
`6,076,152
`
`
`Multiprocessor computer architecture incorporating
`
`
`plurality of memory algorithm processorsin the
`
`Issued
`memory subsystem
`6/12/2001
`6,247,110
`
`
`Split directory-based cache coherency technique for a
`
`
`Issued
`9/25/2001
`multi-processor computer system
`6,295,598
`
`
`
`
`Multiprocessor with each processor element
`accessing operandsin loaded input buffer and
`
`forwarding results to FIFO output buffer
`Issued
`1/15/2002
`6,339,819
`
`
`System and method for accelerating web site access
`
`a
`and processing utilizing
`
`computer system
`
`incorporating reconfigurable processors operating
`under a
`
`Issued
`single operating system image
`6,434,687
`
`
`
`System and method for semaphore and atomic
`operation managementin a
`
`multiprocessor
` Bandwidth enhancementfor uncached devices
`6,836,823
`
`
`Efficiency of reconfigurable hardware
`Issued
`6,941 539
`
`
`a
`Multiprocessor computerarchitecture incorporating
`plurality of memory algorithm processors in the
`memory subsystem
`System and methodfor partitioning control-dataflow
`graph representations
`Process for converting programsin high-level
`to a unified executable for
`programming languages
`hybrid computing platforms
`an arbitrated
`System and method for providing
`memory bus in a
`hybrid computing system
`Computer system architecture and memory controller
`for close-coupling within a
`hybrid processing system
`an
`adaptive processorinterface port
`utilizing
`System and
`for explicit communication of
`method
`on different
`messages between processes running
`nodes in a clustered multiprocessor system
`
`
`Map compiler pipelined loop structure
`
`System and methodof enhancing efficiency and
`utilization of memory bandwidth in reconfigurable
`U.S.
`hardware
`Issued
`7,149,867
`
`
`
`
`
`a
`
`6,594,736
`
`
`
`4835-8327-4159 v.4
`
`Intel Exhibit 1041
`
`8
`
`-
`
`PATENT
`
`REEL: 051615 FRAME: 0351
`
`Intel Exhibit 1041 - 8
`
`

`

`Jurisdiction
`
`q n
`
`U.S
`
`
`
`ers
`Patent
`
`Issued/Filing
`Status
`No./Serial
`Title
`
`
`Date
`
`No.
`
`Interface for integrating reconfigurable processors
`
`into a
`
`general purpose computing system
`Debugging and performanceprofiling using control-
`
`
`dataflow graph representations with reconfigurable
`hardware emulation
`Interface for integrating reconfigurable processors
`into a
`general purpose computing system
`a
`Switch/network adapter port coupling
`reconfigurable processing element to one or more
`microprocessors for use with interleaved memory
`
`controllers
`
`3/27/2007
`7,197,575
`
`Issued
`
`7,155,602
`
`12/26/2006
`
`Issued
`
`Issued
`
`7,155,708
`
`12/26/2006
`
`7,167,976
`
`1/23/2007
`
`
`
`
`
`
`
`
`
`
`
`
`
`S
`
`wn
`
`~
`
`n
`
`q a
`
`q
`
`G
`
`q
`
`cq w”
`
`7,373,440
`
`5/13/2008
`
`7,406,573
`
`7/29/2008
`
`Issued
`
`Issued
`
`
`
`7,421,524
`
`9/2/2008
`
`7,424,552
`
`9/9/2008
`
`7,565,461
`
`7/21/2009
`
`7,620,800
`
`11/17/2009
`
`
`
`7,680,968
`
`3/16/2010
`
`7,703,085
`
`4/20/2010
`
`4835-8327-4159 v.4
`
`Intel Exhibit 1041
`
`9
`
`-
`
`PATENT
`
`REEL: 051615 FRAME: 0352
`
`6/26/2007
`
`a
`
`te
`
`7,237,091
`
`7,299,458
`
`11/20/2007
`
`
`
`
`Multi-adaptive processing systems and techniques for
`enhancing parallelism and performance of
`
`
`computational functions
`Issued
`3/29/2007
`7,225,324
`
`
`Multiprocessor computer architecture incorporating
`
`plurality of memory algorithm processorsin the
`
`Issued
`memory subsystem
`
`System and method for converting control flow graph
`
`representations to control-dataflow graph
`representations
`
`Switch/network adapter port for clustered computers
`
`a chain of multi-adaptive processors in a
`
`employing
`dual in-line memory module format
`Reconfigurable processor elementutilizing both
`coarse and fine grained reconfigurable elements
`Switch/network adapter port for clustered computers
`a chain of multi-adaptive processors in a
`employing
`dual in-line memory module format
`
`Switch/network adapter port incorporating shared
`
`
`a direct
`memory resources
`selectively accessible by
`execution logic element and one or more denselogic
`
`
`
`devices
`a
`Switch/network adapter port coupling
`
`
`reconfigurable processing element to one or more
`microprocessors for use with interleaved memory
`
`
`
`controllers
`
`Multi-adaptive processing systems and techniques for
`
`enhancing parallelism and performance of
`
`
`computational functions
`Switch/network adapter port incorporating shared
`
`
`memory resources
`a direct
`selectively accessible by
`
`execution logic element and one or more denselogic
`
`devices in a
`fully buffered dual in-line memory
`
`module format (FB-DIMM)
`
`
`Process for converting programs in high-level
`
`
`to a unified executable for
`programming languages
`
`
` q ~
`hybrid computing platforms
`
`Intel Exhibit 1041 - 9
`
`

`

`Title
`
`
`Patent
`
`
`Issued/Filing
`Dynamic priority conflict resolution in a multi-
`No./Serial
`Date
`
`
`
`
`No.
`
`
`Elimination ofstream consumerloop overshoot
`
`
`processor computer system having shared resources
`Issued
`2/15/2011
`7,890,686
`
`
`heterogeneousimplicitandexplicitprocessing
`
`
`
`effects
`System and method for computational unification of
`
`Issued
`
`sssued
`
`
`
`Issued
`
`8,589,666
`
`11/19/2013
`
`
`
`8,713,518
`
`4/29/2014
`
`U.S.
`
`US.
`
`USS.
`
`
`us
`Lous
`
`So
`elements
`
`
`System and method for computational unification of
`
`
`
`heterogeneous implicit and explicit processing
`
`
`1/6/2015
`elements
`
`
`
`
`8,930,892
`System and method for retaining DRAM data when
`
`
`
`devices with DRAM
`reprogramming reconfigurable
`3/27/2014
`
`memory controllers
`
`9,153,311
`
`
`
`
`System and method for retaining dram data when
`
`
`
`reprogramming reconfigurable devices with DRAM
`
`
`a data maintenance
`
`
`
`memory controllers incorporating
`
`
`
`block colocated with a memory module or
`
`
`subsystem
`
`
`
`System and method for retaining DRAM data when
`
`
`reprogramming reconfigurable devices with DRAM
`a data maintenance
`
`memory controllers incorporating
`block colocated with a memory module or
`
`subsystem
`
`
`System and method for thermally coupling memory
`
`devices to a memory controller in a
`computer
`memory board
`
`Mobile electronic devices utilizing reconfigurable
`
`to enable higher speed
`
`processing techniques
`Ss.
`applications with lowered power consumption
`
`Multi-processor computer architecture incorporating
`
`common memory modules
`US.
`distributed multi-ported
`
`
`Issued
`
`9,530,483
`
`12/27/2016
`
`
`
`
`
` 12/19/2017
`
`
`5/28/2013
`
`
`9,727,269
`
`8/8/2017
`
`
`
`
`
`
`Pending
`
`13/365,090
`
`2/2/2012
`
`Pending
`
`13/903,720
`
`
`
`
`
`
`
`4835-8327-4159 v.4
`
`RECORDED: 01/24/2020
`
`Intel Exhibit 1041
`
`10
`
`-
`
`PATENT
`
`REEL: 051615 FRAME: 0353
`
`Intel Exhibit 1041 - 10
`
`