Case 2:18-cv-00317-JLR Document 114 Filed 11/05/18 Page 1 of 26
`
`THE HONORABLE JAMES L. ROBART
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF WASHINGTON
`AT SEATTLE
`
`SRC LABS, LLC & SAINT REGIS
`MOHAWK TRIBE,
`
` CASE NO. 2:18-cv-00317-JLR
`
` Plaintiffs,
`
` v.
`
`AMAZON WEB SERVICES, INC.,
`AMAZON.COM, INC.,
`& VADATA INC.,
`
` Defendant.
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`PLAINTIFFS’ OPENING CLAIM
`CONSTRUCTION BRIEF
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`ORAL ARGUMENT REQUESTED
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`JURY TRIAL DEMANDED
`
`DUE DATE:
`November 16, 2018
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`PLAINTIFFS’ OPENING
`CLAIM CONSTRUCTION BRIEF
`CASE NO. 2:18-CV-317-JLR
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`BREMER LAW GROUP PLLC
`1700 SEVENTH AVENUE, SUITE 2100
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`Intel Exhibit 1016 - 1
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`Case 2:18-cv-00317-JLR Document 114 Filed 11/05/18 Page 2 of 26
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`TABLE OF CONTENTS
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`TABLE OF AUTHORITIES ........................................................................................... iii 
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`I.  INTRODUCTION ...................................................................................................... 1 
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`II. TECHNICAL BACKGROUND ............................................................................... 1 
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`A. Conventional Computer Architecture. ..................................................................... 1 
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`B. Field Programmable Gate Arrays. ........................................................................... 2 
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`C. The Patents-in-Suit. ................................................................................................. 2 
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`III. LEGAL STANDARD FOR CLAIM CONSTRUCTION ........................................ 3 
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`IV. DISPUTED TERMS FROM THE ’324 AND ’800 PATENTS .................................. 3 
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`A. “systolic”/systolically .............................................................................................. 4 
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`B. “pass computed data seamlessly” ............................................................................. 6 
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`C. “instantiated” / “instantiating”/ “instantiation” ...................................................... 7 
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`V.  DISPUTED TERM FOR THE ’311 PATENT .......................................................... 10 
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`A. “a data maintenance block” – claim 1 .................................................................... 10 
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`VI. DISPUTED TERMS IN THE ’867 PATENT ............................................................ 13 
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`A. “a data prefetch unit” – claims 1, 3, 4 ..................................................................... 13 
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`B. “a data prefetch unit coupled to the memory, wherein the data prefetch unit
`retrieves only computational data required by the algorithm from a second
`memory of second characteristic memory bandwidth and/or memory
`utilization and places the retrieved computational data in the first memory”
`– claim 1 ................................................................................................................ 14 
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`C. “at least the first memory and data prefetch unit are configured to conform to
`needs of the algorithm” – claims 1, 3, 4 ................................................................. 18 
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`VII.  CONCLUSION .................................................................................................... 21
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`PLAINTIFFS’ OPENING
`CLAIM CONSTRUCTION BRIEF
`CASE NO. 2:18-CV-317-JLR
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`BREMER LAW GROUP PLLC
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`Intel Exhibit 1016 - 2
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`Case 2:18-cv-00317-JLR Document 114 Filed 11/05/18 Page 3 of 26
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`
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`CASES
`
`TABLE OF AUTHORITIES
`
`Abbott Labs. v. Sandoz, Inc.,
`566 F.3d 1282 (Fed. Cir. 2009) ............................................................................... 10, 11, 12
`
`
`Amgen Inc. v. Hoechst Marion Rousell, Inc.,
`314 F.3d 1313 (Fed. Cir. 2003) .......................................................................................... 13
`
`
`Ancora Techs., Inc. v. Apple, Inc.,
`744 F.3d 732 (Fed. Cir. 2014) .......................................................................................... 5, 7
`
`
`Apex Inc. v. Raritan Computer, Inc.,
`325 F.3d 1364 (Fed. Cir. 2003) .......................................................................................... 15
`
`
`Comark Commc’ns, Inc. v. Harris Corp.,
`156 F.3d 1182 (Fed. Cir. 1998) ............................................................................................ 3
`
`
`Linear Tech. Corp. v. Impala Linear Corp.,
`379 F.3d 1311 (Fed. Cir. 2004) .......................................................................................... 17
`
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`Massachusetts Inst. of Tech. & Elecs. For Imaging, Inc. v. Abacus Software,
`462 F.3d 1344 (Fed. Cir. 2006) ..................................................................................... 15, 17
`
`
`Nautilus, Inc. v. Biosig Instruments, Inc.,
`572 U.S. 898 (2014) ................................................................................................ 18, 19, 20
`
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`Pacing Techs., LLC v. Garmin Int'l, Inc.,
`778 F.3d 1021 (Fed. Cir. 2015) ..................................................................................... 4, 5, 8
`
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) ........................................................................... 3, 12, 13, 14
`
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`Power Integrations, Inc., v. Fairchild Semiconductor Int'l, Inc.,
`711 F.3d 1348 (Fed. Cir. 2013) ..................................................................................... 16, 17
`
`
`Teva Pharm. USA, Inc. v. Sandoz, Inc.,
`789 F.3d 1335 (Fed. Cir. 2015) .......................................................................................... 18
`
`
`Vitronics Corp. v. Conceptronic, Inc.,
`90 F.3d 1576 (Fed. Cir. 1996) ......................................................................................... 3, 12
`PLAINTIFFS’ OPENING
`BREMER LAW GROUP PLLC
`CLAIM CONSTRUCTION BRIEF
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`Case 2:18-cv-00317-JLR Document 114 Filed 11/05/18 Page 4 of 26
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`Watts v. XL Sys., Inc.,
`232 F.3d 877 (Fed. Cir. 2000) ............................................................................................ 15
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`Williamson v. Citrix Online, LLC,
`792 F.3d 1339 (Fed. Cir. 2015) .......................................................................................... 15
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`Zeroclick, LLC v. Apple Inc.,
`891 F.3d 1003 (Fed. Cir. 2018) .......................................................................................... 14
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`STATUTES:
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`35 U.S.C. § 112 ................................................................................................................ passim
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`PLAINTIFFS’ OPENING
`CLAIM CONSTRUCTION BRIEF
`CASE NO. 2:18-CV-317-JLR
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`BREMER LAW GROUP PLLC
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`Intel Exhibit 1016 - 4
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`Case 2:18-cv-00317-JLR Document 114 Filed 11/05/18 Page 5 of 26
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`I. INTRODUCTION
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`Plaintiffs have proposed claim constructions for the disputed terms of U.S. Patent Nos.
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`7,225,324 (the “’324 Patent”), 7,620,800 (the “’800 Patent”), 9,153,311 (the “’311 Patent”),
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`and 7,149,867 (the “’867 Patent”) and, collectively with the ‘324 Patent, the ‘800 Patent,
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`and the ‘311 Patent, the “patents-in-suit”) that are fully supported by the intrinsic and
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`extrinsic evidence. By contrast, Amazon has proposed constructions that do not comport
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`with either the intrinsic or extrinsic record and are, in some cases, contradicted by positions
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`Amazon has advanced in its petition for inter partes review of the ’867 patent.
`II. TECHNICAL BACKGROUND
`A. Conventional Computer Architecture.
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`Conventional computers utilize general-purpose processors from Intel or AMD and
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`employ a Von Neumann architecture. In a conventional computer, “hardware is fixed and
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`cannot be changed after manufacturing.”1 In Von Neumann machines both the “software
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`program and the data to operate on reside in the main memory and therefore the processor
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`is connected to the main memory through bus lines that include [a] data bus and address
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`bus.”2 To execute a software program, the processor “goes through a fixed routine of
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`steps”:3
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`1. Instruction Fetch - read the instruction whose address is
`specified by the program counter into the designated processor
`internal register, and advance the program counter to point to
`the next instruction
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`2. Instruction Decode - Decipher the work needed by the
`instruction
`
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`1 Declaration of Christopher L. Evans in support of Plaintiffs’ Opening Claim Construction
`Brief (hereinafter “Evans Decl.”), Ex. 18: Decl. of Dr. El-Ghazawi at ¶ 9.
`2 Id.
`3 Id.
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`PLAINTIFFS’ OPENING
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`CASE NO. 2:18-CV-317-JLR
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`BREMER LAW GROUP PLLC
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`Case 2:18-cv-00317-JLR Document 114 Filed 11/05/18 Page 6 of 26
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`3. Execute - carry out the work needed if data is available
`internally, if not then prepare the address of the data
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`4. Data Memory Access - read/write data from/to memory
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`5. Write back - write the results into an internal register
` This is referred to as the fetch-execute cycle. Because of their architecture, conventional
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`computers must operate in a sequential manner.4
`B. Field Programmable Gate Arrays.
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`A field programmable gate array (FPGA) is a reprogrammable integrated circuits that
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`contains an array of configurable logic blocks (functional units) connected by configurable
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`interconnects.5 The user can configure the FPGA to perform a desired computation by
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`configuring (or instantiating) the configurable logic blocks to perform the desired operations
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`(arithmetic, logical, control, data movement, etc.) and then configuring the interconnects so
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`that the configured logic is interconnected in the order needed to perform the desired
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`computation.6 An FPGA is configured by loading a file called a bitstream into the FPGA.7
`C. The Patents-in-Suit.
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`The inventors of the patents-in-suit pioneered the use of FPGAs as general-purpose
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`processors to create small, energy efficient, supercomputers that outperform conventional
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`computers by a factor of 100x (or more) while using 99% less power. Since SRC created an
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`entirely new computer architecture that radically departs from the traditional Von Neumann
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`model they encountered and solved many different types of technical problems.
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`Accordingly, the patents-in-suit (across both cases) cover many different aspects of the
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`reconfigurable computers that SRC invented.
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`4 Id. at ¶ 10.
`5 Id. at ¶ 11.
`6 Id.
`7 Id.
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`PLAINTIFFS’ OPENING
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`CASE NO. 2:18-CV-317-JLR
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`BREMER LAW GROUP PLLC
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`Intel Exhibit 1016 - 6
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`Case 2:18-cv-00317-JLR Document 114 Filed 11/05/18 Page 7 of 26
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`III. LEGAL STANDARD FOR CLAIM CONSTRUCTION
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`Claim terms are generally given their ordinary and customary meaning as the term
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`would have been understood by a person of ordinary skill in the art at the time of the
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`invention.8 The “intrinsic evidence of record, i.e., the patent itself, including the claims, the
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`specification and, if in evidence, the prosecution history,” is “the most significant source of
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`the legally operative meaning of [the] disputed claim language.”9 Even though the
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`“specification may aid the court in interpreting the meaning of disputed claim language,
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`particular embodiments and examples appearing in the specification will not generally be
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`read into the claims.”10 But constructions that exclude a preferred embodiment from the
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`scope of the claims are “rarely, if ever, correct.”11 The claim construction process may not
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`be used to redefine the claims by inserting unclaimed elements or limitations.12
`IV. DISPUTED TERMS FROM THE ’324 AND ’800 PATENTS
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`Because these two patents are asserted against both Microsoft and Amazon, the Court
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`consolidated the claim construction hearing for issues related to these two patents.13
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`Accordingly, Plaintiffs are only briefing terms at issue in both cases once (here) and hereby
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`incorporate by reference this section into their claim construction brief in the Microsoft case.
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`Plaintiffs will serve a copy of this brief on Microsoft.
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`8 Phillips v. AWH Corp., 415 F.3d 1303, 1312-13 (Fed. Cir. 2005).
`9 Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576, 1582 (Fed. Cir. 1996).
`10 Comark Commc’ns, Inc. v. Harris Corp., 156 F.3d 1182, 1187 (Fed. Cir. 1998).
`11 Vitronics ,90 F.3d at 1583.
`12 See Phillips, 415 F.3d at 1312 (“Because the patentee is required to ‘define precisely what his
`invention is,’ the Court explained, it is ‘unjust to the public, as well as an evasion of the law, to
`construe it in a manner different from the plain import of its terms.’”).
`13 Dkt. 96.
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`PLAINTIFFS’ OPENING
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`Intel Exhibit 1016 - 7
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`Case 2:18-cv-00317-JLR Document 114 Filed 11/05/18 Page 8 of 26
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`A. “systolic”/systolically
`Plaintiffs’ Construction
`This term has its plain and
`ordinary meaning and need
`not be construed. In the
`alternative, this term may
`be construed as:
`
`rhythmically computing
`and passing data in a
`transport triggered manner
`
`Amazon’s Construction
`rhythmically computing
`and passing data directly
`between processing
`elements “without a
`program counter or clock
`that drives the movement
`of data” and operating in a
`manner that is “transport
`triggered, i.e., by the arrival
`of a data object”
`
`Microsoft’s Construction
`The characteristic of
`rhythmically computing and
`passing data directly between
`processing elements “without
`a program counter or clock
`that drives the movement of
`data” and operating in a
`manner that is “transport
`triggered, i.e., by the arrival
`of a data object”
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`The issue here is whether there is any reason to depart from the plain meaning of this
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`term. Departing from a term’s plain meaning is appropriate only when the patentee acted as
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`its own lexicographer or when there was a disavowal.14 The standard for finding either of
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`these is “exacting” and requires that the patentee either (i) “clearly set forth a definition of
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`the disputed claim term” and “clearly express[ed] an intent to define the term” or (ii) the
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`specification or prosecution history makes “clear that the invention does not include a
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`particular feature.”15 Neither is present here so the plain meaning should control.
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`The term “systolic” has had a well-known and customary meaning to a person of
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`ordinary skill in the art of reconfigurable processing since long before the ’324 patent’s
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`priority date. This is not in dispute. The concept of systolic computing architecture was
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`invented by H.T. Kung in 1978.16 Dr. Kung described a systolic system as follows:
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`In a systolic system, data flows from the computer memory in a
`rhythmic fashion, passing through many processing elements
`before it returns to memory, much as blood circulates to and
`from the heart.17
`
`
`14 Pacing Techs., LLC v. Garmin Int'l, Inc., 778 F.3d 1021, 1024 (Fed. Cir. 2015).
`15 Id.
`16 Evans Decl., Ex. 3 at p. 5.
`17 Evans Decl., Ex. 4 at 37.
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`Case 2:18-cv-00317-JLR Document 114 Filed 11/05/18 Page 9 of 26
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`SRC confirmed that it was using the ordinary meaning of “systolic” during prosecution:
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`Instantiation is a term well known to one of ordinary skill in the
`art of reconfigurable processing… Similarly the term systolic
`computation is derived from continual and pulsating pumping
`of the human heart. In computer architecture a systolic array is
`an arrangement of data processing units similar to a central
`processing unit but without a program counter or clock that
`drives the movement of data. That is because the operation of
`the systolic array is transport triggered, i.e. by the arrival of a
`data object. Data flows across the array between functional
`units, usually with different data flowing in different directions.
`David J. Evans in his work, Systolic algorithms … define[s] a
`Systolic system as a “network of processors which rhythmically
`compute an[d] pass data through the system.”18
`In this excerpt, SRC merely described what the ordinary meaning of “systolic” would be to
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`one of ordinary skill in the art. SRC did not redefine the term or evince any intent to do so.
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`Consistent with this ordinary meaning, in the ’324 patent computation loops “are
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`executed concurrently in a systolic fashion such that data computed within each
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`computation unit is seamlessly and concurrently passed between computational units.”19
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`By contrast, Defendants have bolted together a Frankenstein’s monster of phrases from
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`SRC’s description of the ordinary meaning of the term “systolic” and, presumably will
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`justify this by arguing that SRC acted as its own lexicographer. But the standard for “finding
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`lexicography” is exacting and requires the patentee to “clearly set forth a definition of the
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`disputed claim term” and “clearly express an intent to define the term.”20 There is no such
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`18 Dkt. 113-12: Ex. L - ’324 patent prosecution history at MS_SRC-SRMT_0473096-97
`(emphasis added).
`19 Id. at MS_SRC-SRMT_0473099.
`20 Pacing Techs., LLC, 778 F.3d at 1024; Ancora Techs., Inc. v. Apple, Inc., 744 F.3d 732, 734 (Fed.
`Cir. 2014) (“A claim term should be given its ordinary meaning in the pertinent context, unless
`the patentee has made clear its adoption of a different definition or otherwise disclaimed that
`meaning.”).
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`PLAINTIFFS’ OPENING
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`CASE NO. 2:18-CV-317-JLR
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`BREMER LAW GROUP PLLC
`1700 SEVENTH AVENUE, SUITE 2100
`SEATTLE, WA 98101
`TELEPHONE: 206.357.8442
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`Intel Exhibit 1016 - 9
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`Case 2:18-cv-00317-JLR Document 114 Filed 11/05/18 Page 10 of 26
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`intent here.
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`In addition, Microsoft relies on Dr. Houh’s opinion on “how a Skilled Artisan would
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`understand” the terms “systolic” and “systolically” to support its construction.21 But when
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`asked whether he had ever heard these terms used in the context of computer science before
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`this case, Dr. Houh said “I think that I probably have at some point. I don’t recall exactly
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`when I first heard it.”22 So his opinion concerning “how a Skilled Artisan would
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`understand” the terms should be given little weight.
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`Finally, Defendants’ limitation that systolic means “without a program counter or
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`clock” is contrary to the patent specification and the reality that all computers, even
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`reconfigurable computers, have a clock. The specification clearly states that the claimed
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`invention will use a clock because it talks about how “the computing system logic is
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`operative on every clock cycle.”23 Defendants’ proposed construction adds in unnecessary
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`ambiguity by suggesting that no clock would be present in a systolic system.
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`Thus, no further construction of “systolic” or “systolically” is necessary.
`B. “pass computed data seamlessly”
`Plaintiffs’ Construction
`communicating the computed data over
`the reconfigurable routing resources
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`Defendants’ Construction
`to communicate computed data directly
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`Plaintiffs’ proposed construction comes directly from the intrinsic record. During
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`prosecution, the patentee argued that the use of the words “protocol independent” in the
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`claims was intended to “impart the ability of the functional units to seamlessly pass
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`computed data between computational loops comprised of functional units.”24 But to
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`21 Evans Decl., Ex. 26: Decl. of Dr. Houh at ¶¶ 206-207.
`22 Evans Decl., Ex. 23: Deposition of Dr. Houh (“Houh Depo.”) at 163:5-14.
`23 Dkt. 113-4: Ex. D - ’324 patent, 6:13-20; see also id. at 8:27-40, Fig. 4(b).
`24 Dkt. 113-12: Ex. L - ’324 patent prosecution history at MS_SRC-SRMT_0473096.
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`PLAINTIFFS’ OPENING
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`Intel Exhibit 1016 - 10
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`Case 2:18-cv-00317-JLR Document 114 Filed 11/05/18 Page 11 of 26
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`
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`overcome a written description rejection and alleviate any apparent confusion the “protocol
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`independent” language was removed and replaced with “an ‘interconnection’ between
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`functional units that is established by reconfigurable routing resources inside each chip.”25
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`The patentee explained that “communication between other reconfigurable processors
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`within the system would require communication protocol but communication between
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`functional units within an individual reconfigurable processor is free of such a
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`requirement.”26
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`The prosecution history makes clear that “seamlessly” meant “protocol independent”
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`and that protocol independence is achieved by utilizing the reconfigurable routing resources.
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`Plaintiffs’ proposed construction captures this meaning by defining “seamlessly” to mean
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`“over the reconfigurable routing resources.”
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`By contrast, Defendants’ definition is overly broad as it includes connections over
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`reconfigurable routing resources as well as other undefined direct connections.
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`Accordingly, the Court should adopt Plaintiffs’ proposed construction.
`C. “instantiated” / “instantiating”/ “instantiation”
`Plaintiffs’ Construction
`Amazon’s
`Construction
`Creating or
`configuring to
`perform a defined
`calculation, each
`creation or
`configuration for
`each calculation is
`unique.
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`This term has its plain
`and ordinary meaning
`and need not be
`construed. In the
`alternative, this term
`may be construed as:
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`Configured, configuring,
`configuration
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`Microsoft’s Construction
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`Configuring/configured/configuration,
`such that each configuration for each
`calculation is unique
`
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`25 Compare id. with id. at MS_SRC-SRMT_0473086-87. The “pass computed data seamlessly”
`element was also added in this amendment.
`26 Id. at MS_SRC-SRMT_0473086-87.
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`PLAINTIFFS’ OPENING
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`Case 2:18-cv-00317-JLR Document 114 Filed 11/05/18 Page 12 of 26
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`The issue here is whether there is any reason to depart from the plain meaning of this
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`term. Departing from a term’s plain meaning is appropriate only when the patentee acted as
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`its own lexicographer or when there was a disavowal.27 The standard for finding either of
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`these is “exacting” and requires that the patentee either (i) “clearly set forth a definition of
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`the disputed claim term” and “clearly express[ed] an intent to define the term” or (ii) the
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`specification or prosecution history makes “clear that the invention does not include a
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`particular feature.”28 Neither is present here so the plain meaning should control.
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`The terms “instantiated/instantiating” have a well-known and customary meaning to a
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`person of ordinary skill in the art of reconfigurable computers since long before the ’324
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`patent’s priority date.29 During prosecution, the examiner “requested that the Applicant
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`further define the term instantiated.”30 SCR responded by explaining the ordinary meaning:
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`Instantiation is a term well known to one of ordinary skill in the
`art of reconfigurable processing. A reconfigurable processor is
`essentially a blank processor that must be configured
`(instantiated) to conduct a particular task. To instantiate means
`to create such an instance or configuration by, for example,
`defining one particular variation of the processor’s structure.
`This involves allocation of a structure with types specified by a
`template and the initialization of instance variables with either
`default values or those provided by a constructor function. In
`reconfigurable computing a hard macro library file is typically
`inserted into a design file. A design may include multiple
`instances of the same library file with each possessing a unique
`name. Thus in Applicant’s invention the reconfigurable
`
`
`27 Pacing Techs., LLC, 778 F.3d at 1024.
`28 Id.
`29 Evans Decl., Ex. 26: Decl. of Dr. Houh at ¶¶ 199-200 (“ordinary meaning” of instantiate is
`“creating, such as by configuring, a particular structure”).
`30 Dkt. 113-12: Ex. L - ’324 patent prosecution history at MS_SRC-SRMT_0473096.
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`Case 2:18-cv-00317-JLR Document 114 Filed 11/05/18 Page 13 of 26
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`processor is instantiated and designed to perform the defined
`calculation. Each instantiation for each calculation is unique.31
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`After analyzing this paragraph, Microsoft’s expert, Dr. Stone,32 opined that instantiation
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`means configuration: “A Skilled Artisan would therefore have understood that applicant’s
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`reply to have defined the term ‘instantiate’ to mean ‘create, such as by configuring, a
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`particular structure,’ since the definition parenthetically equates ‘instantiation’ with
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`configuration.”33 Dr. Stone then concluded that “a Skilled Artisan would have understood
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`that ‘‘instantiate’ was used in substantially the same way in the prior art.”34
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`This is further confirmed by the ’324 patent’s specification, which uses the term
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`instantiate to describe configuring the functional units needed to solve a problem:
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`Reconfigurable processors instantiate only the functional units
`needed to solve a particular application, and as a result, have
`available space to instantiate as many functional units as may
`be required to solve the problem up to the total capacity of the
`integrated circuit chips they employ.35
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`The method comprises: defining a calculation for the
`reconfigurable computing system; instantiating at least two of
`the functional units to perform the calculation…36
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`Nevertheless, Defendants seek to read in additional meaning that would require each
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`“instantiation for each calculation to be unique.” But this circular definition does not clarify
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`the term’s meaning.
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`And this construction deviates from the definition of “instantiate” that Microsoft
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`31 Id. at MS_SRC-SRMT_0473097.
`32 Dr. Stone is Microsoft’s expert in the two requests for inter partes review it recently filed
`against the ’324 patent. Evans Decl., Ex. 5: Decl. of Dr. Stone in IPR2018-01601.
`33 Evans Decl., Ex. 5: Declaration of Dr. Stone at ¶¶ 86-87.
`34 Id. at ¶ 88.
`35 Dkt. 113-4: Ex. D - ’324 patent, 2:1-5.
`36 Id. at 2:51-54.
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`Case 2:18-cv-00317-JLR Document 114 Filed 11/05/18 Page 14 of 26
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`advocates for in its Petition for Inter Partes Review of the ’324 patent that it filed on
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`September 5, 2018.37 In the IPR, Microsoft argues that based on the prosecution history a
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`“Skilled Artisan” would have understood SRC to have “defined the term ‘instantiate’ to
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`mean ‘create, such as by configuring, a particular structure’ because it parenthetically
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`equates ‘instantiation’ with configuration.”38 But claims must be construed the same for
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`both infringement and validity so Microsoft cannot seek a different construction here than in
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`the IPR.39 And Microsoft has agreed to construe “instantiated” in the closely-related ’687
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`patent to mean “configured.”40
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`Thus, no further construction of “instantiated” or “instantiating” is necessary.
`V. DISPUTED TERM FOR THE ’311 PATENT
`A. “a data maintenance block” – claim 1
`Plaintiffs’ Construction
`This term has its plain and ordinary
`meaning and need not be construed.
`
`Defendants’ Construction
`a device separate from the memory
`controller that drives self-refresh command
`inputs and stores DRAM memory data
`when the reconfigurable logic device is
`reconfigured
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`The issue here is whether the term “data maintenance block” must be physically
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`separate from the memory controller and store DRAM memory data as Amazon contends.
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`The term “a data maintenance block” is defined by the claim itself:
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`1. A computer system comprising:
`a DRAM memory;
`a reconfigurable logic device having a memory controller coupled to selected
`inputs and outputs of said DRAM memory; and
`a data maintenance block coupled to said reconfigurable logic device and self-
`refresh command inputs of said DRAM memory, said data maintenance
`
`
`37 Evans Decl., Ex. 7 at 16.
`38 Id. at 17.
`39 Abbott Labs. v. Sandoz, Inc., 566 F.3d 1282, 1317 (Fed. Cir. 2009).
`40 Dkt. 113 at 18 (Agreed Construction of “instantiating” is “configuring”).
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`Case 2:18-cv-00317-JLR Document 114 Filed 11/05/18 Page 15 of 26
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`block operative to provide stable input levels on said self-refresh command
`inputs while said reconfigurable logic device is reconfigured.
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`Claim one requires “a data maintenance block” to (i) be connected to the “reconfigurable
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`logic device” and the “self-refresh command inputs” of “a DRAM memory” and to (ii)
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`“provide stable input levels” to the “self-refresh command inputs” when the reconfigurable
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`logic device is reconfigured. Accordingly, no further construction is needed.
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`Nevertheless, Amazon seeks to read in two additional limitations from the specification:
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`(i) a requirement that the data maintenance block be physically separate from the memory
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`controller and (ii) a requirement that the data maintenance block store DRAM memory
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`data. But this construction is contrary to the intrinsic evidence and violates several cannons
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`of claim construction.
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`First, Amazon’s physically separate requirement is arbitrary and unsupported by the
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`intrinsic record.