UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`INTEL CORPORATION,
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`Petitioner
`
`V.
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`FG SRC LLC,
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`Patent Owner
`
`CASE NO.: 2020-01449
`PATENT NO. 7,149,867
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`DECLARATION OF RAJESH K. GUPTA, PH.D.
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`
`Alexandria, VA 22313-1450
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`Intel Exhibit 1010 - 1
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`

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`I, Dr. Rajesh K. Gupta, declare as follows:
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`1.
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`I am currently Professor and Qualcomm Endowed Chair at the
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`Department of Computer Science and Engineering at University of California, San
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`Diego ("UCSD"). I have served in that role since 2002.
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`2.
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`I conduct research in advancing computing technologies and computer
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`system architecture, and supervise Ph.D. students.
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`Concurrent Systems Architecture Group ("CSAG")
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`3.
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`From 1994 to 1996, I was an assistant professor of Computer Science
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`at the University of Illinois, Urbana-Champaign ("UIUC"). While at UIUC, I
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`collaborated closely with Dr. Andrew A. Chien, who ran the Concurrent Systems
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`Architecture Group ("CSAG") at UIUC from 1990 to 1998. The CSAG was
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`Professor Chien's research group, and its original website address was www(cid:173)
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`csag.cs.uiuc.edu/. That website, and the links and information provided on the
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`website, was available to the general public.
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`4.
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`One of the research projects unde1taken by CSAG, which began at
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`least as early as 1996, was called the "Multiprocessor with Reconfigurable
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`Parallel Hardware" ("MORPH") project. I led a later implementation of the
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`MORPH project research into a machine prototype, called the "Adaptive Memory
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`Reconfiguration Management" ("AMRM") project, when I moved to the
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`University of California, Irvine in the Fall of 1996. These projects related to the
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`same ideas about reconfigurable computer processor architecture and systems, and,
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`thus, were referred to as the MORPH/ AMRM project.
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`5.
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`Dr. Chien and I collaborated closely together at UIUC and thereafter,
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`including by jointly applying for a research grant for the MORPH/ AMRM project
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`from the National Science Foundation ("NSF") and later to the Defense Advanced
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`Research Project Agency ("DARPA"). See paragraph 9, below.
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`2
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`Intel Exhibit 1010 - 2
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`6.
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`In 1996, I took a position as an assistant professor in the Department
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`of Information and Computer Sciences at University of California, Irvine ("UCI").
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`Dr. Chien and I continued to collaborate on the MORPH project (including with
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`others) even after I had joined UCI. While at UCI, I helped maintain a website
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`page for the AMRM project hosted by UCI which was accessible by the public via
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`the link at https://www.ics.uci.edu/~amrm/. That website continues to be publicly
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`available today.
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`7.
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`I left UCI to join UC San Diego (UCSD) in 2002. Dr. Chien and I
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`worked together at UCSD between 2002 and 2006. When Dr. Chien joined UCSD
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`in 1998, the work of the CSAG moved also, and the website was hosted by the
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`Systems and Networking Group in the Department of Computer Science and
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`Engineering at UCSD, via the link http://www-csag.ucsd.edu/. That website, and
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`the links and information provided on the website, was available to the general
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`public.
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`8.
`
`Clicking on the link titled "MORPH/ AMRM: High Perfonnance
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`computing based on Sma1i Reconfiguration" on the
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`http://cseweb.ucsd.edu/groups/csag/html/ website takes users to the AMRM project
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`website hosted by UCI via the link at https://www.ics.uci.edu/~amrm/. That
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`website, and the links and information provided on the website, was and continues
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`to be available to the general public.
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`National Science Foundation Grant
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`9.
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`In 1996, Dr. Chien and I applied for a research grant from the Office
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`of Advanced Cyberinfrastructure of the National Science Foundation ("NSF").
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`10. The NSF required award grantees to follow certain procedures as set
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`out in Grant Policy Manual NSF95-26 ("GPM"), which was in effect from 1995 to
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`July 2002. The GPM is still publicly available and can be accessed via
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`https://www.nsf.gov/pubs/stisl 995/nsf9526 (accessed June 22, 2020).
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`3
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`Intel Exhibit 1010 - 3
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`11. One condition of the NSF award was that we submit annual reports
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`and a final report. We were also required to make infonnation about the project
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`publicly accessible through publications, at conferences, or by other means,
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`including Principal Investigator (PI) Meetings held by the community of
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`researchers and the NSF. A number of the publications and conferences are
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`discussed at paragraphs 17-25, below.
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`MORPH Project
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`12. The application that Dr. Chien and I submitted in 1996 was
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`successful, and we jointly received NSF Grant Award ASC-96-34947 ("the NSF
`
`Grant").
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`13. The award grant was for $100,000, the period of the grant began in or
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`around August 15, 1996 and was set to expire on or about July 31, 1998. The
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`working title of the project was "PDS: A Flexible Architecture for Executing
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`Component Software at 100 Teraops". Attached as Exhibit A is a true and correct
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`copy of the award abstract, which is publicly available and can be accessed via
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`https://www.nsf.gov/awardsearch/showAward? A WD ID=9634947.
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`14. Our research pursuant to the NSF Grant concluded in or around July
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`1998.
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`Publications of MORPH/AMRM Papers
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`15.
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`From July 1998 until about October 1998, Dr. Chien and I
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`collaborated on the preparation of the Final Project Report.
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`16.
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`I submitted the Final Project Report to the NSF around October 1998.
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`17.
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`In addition to submitting the Final MORPH Report, Dr. Chien and I
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`additionally disseminated the results of the research conducted pursuant to the NSF
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`Grant through various conferences and papers, including at least the following
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`papers described in paragraphs 18-26 below.
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`4
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`Intel Exhibit 1010 - 4
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`18.
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`In the first half of 1996, Dr. Chien and I coauthored a paper entitled
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`MORPH: A System Architecture for Robust H;gher Pe,formance Using
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`Customization. We presented this paper at Frontiers '96, The Sixth Symposium on
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`the Frontiers of Massively Parallel Computing. ("Frontiers '96 Conference"). The
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`Frontiers '96 Conference was sponsored by the Institute of Electrical and
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`Electronics Engineers, Inc. ("IEEE") and held in Annapolis, Maryland between
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`October 27-31 , 1996. The IEEE is the world's largest technical professional
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`organization, and is a widely-recognized publisher of technical papers spanning a
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`wide range of technologies including electronics, electrical engineering,
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`telecommunications, computing, and more. The IEEE publishes thousands of
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`conference papers every year, including by making them publicly available via its
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`Xplore digital library. The IEEE's collection of publications is recognized by
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`academics and industry workers around the world as an authoritative source of
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`consolidated published papers in electrical engineering, computer science, and
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`related fields. Based on my experience in attending conferences sponsored by the
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`IEEE, and based on the general practice in the scientific and engineering
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`community, I believe this paper was distributed to the conference attendees prior to
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`or during the conference.
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`19. This paper was subsequently published as pp. 336-345 of the Frontiers
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`'96 Conference Proceedings by the IEEE in 1996. As with other IEEE
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`conferences, this paper was made available in 1996 to conference attendees at
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`Frontiers '96, and I understand that it has been available from the IEEE Xplore
`
`website (https://ieeexplore.ieee.org/document/558112) since at least as early as
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`August 6, 2002.
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`20.
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`I have reviewed Exhibit 1005, and it is a true and correct copy of this
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`article, MORPH: A System Architecture for Robust Higher Performance Using
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`Customization (an NSF 100 TeraOps point design study), which was publicly
`
`5
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`Intel Exhibit 1010 - 5
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`available at the '96 Conference in 1996, published by IEEE in 1996, and publicly
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`available in Xplore at least as early as August 2002.
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`21.
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`In 1997, after I had joined the faculty at UCI, I co-authored a paper
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`entitled Architectural Adaptation of Application-Specific Locality Optimizations
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`with Xingbin Zhang, Ali Dasdan, and Dr. Chien (all at UIUC at the time) and
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`Martin Schulz (at the Institut fir Informatik, Technische Universitat Milnchen).
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`We presented this paper at the International Corzference on Computer Design -
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`VLSI in Computers and Processors ("VLSI '97 Conference"). The VLSI '97
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`Conference was sponsored by the IEEE and was held in Austin, Texas between
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`October 12-15, 1997. Based on my experience in attending conferences organized
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`by the IEEE, and based on the general practice in the scientific and engineering
`
`community, I believe this paper was distributed to the conference attendees prior to
`
`or during the conference.
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`22. This paper was subsequently published as pp. 150-156 of the
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`VLSI '97 Conference Proceedings by the IEEE in 1997. It was made available in
`
`1997 to the conference attendees at VLSI '97 Conference, and I understand that it
`
`has been available from the IEEE Xplore website
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`(https://ieeexplore.ieee.org/document/628862) at least as early as August 6, 2002.
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`23 .
`
`I have reviewed Exhibit 1003, and it is a true and con-ect copy of this
`
`article, Architectural Adaptation of Application-Specific Locality Optimizations,
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`which was publicly available at the VLSI '97 Conference in 1997, published by
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`IEEE in 1997, and publicly available in Xplore at least as early as August 2002.
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`24.
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`In 2000, I authored a research paper entitled Architectural Adaptation
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`in AA1RM Machines. I presented this paper at the Proceedings of the IEEE
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`Computer Society Workshop on VLSI 2000 ("VLSI '00 Workshop"). The
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`VLSI '00 Workshop was held in Orlando, Florida between April 27/28, 2000.
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`Based on my experience in attending conferences organized by the IEEE, and
`
`6
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`Intel Exhibit 1010 - 6
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`

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`based on the general practice in the scientific and engineering community, I
`
`believe this paper was distributed to the conference attendees prior to or during the
`
`conference.
`
`25. This paper was subsequently published as pp. 75-80 of the VLSI '00
`
`Workshop Proceedings by the IEEE in 1997. It was made available to the
`
`conference attendees at VLSI '97 Conference, and I understand that it has been
`
`available from the IEEE Xplore website
`
`(https://ieeexplore.ieee.org/document/844533) at least as early as August 6, 2002.
`
`26.
`
`I have reviewed Exhibit 1004, and it is a true and con-ect copy of this
`
`article, Architectural Adaptation in AMRM Machines, which was publicly
`
`available at the VLSI ' 00 Conference in 1997, published by IEEE in 1997, and
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`publicly available in Xplore at least as early as August 2002.
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`I declare under penalty of pe1jury that the foregoing is true and correct.
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`Date: August 10, 2020
`
`R1lje K . Gu
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`7
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`Intel Exhibit 1010 - 7
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`Exhibit A
`Exhibit A
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`Intel Exhibit 1010 - 8
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`Intel Exhibit 1010 - 8
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`7/30/2020
`
`
`NSF Award Search: Award#9634947 - PDS: A Flexible Architecture for Executing Component Software at 100 Teraops
`
`RESEARCH AREAS
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`Award Abstract #9634947
` PDS: A Flexible Architecture for Executing Component Software at
`100 Teraops
`
`NSF Org:
`
`OAC
`Office of Advanced Cyberinfrastructure (OAC)
`
`Initial Amendment Date:
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`August 22, 1996
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`Latest Amendment Date:
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`August 22, 1996
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`Award Number:
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`9634947
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`Award Instrument:
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`Standard Grant
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`Program Manager:
`
`Charles H. Koelbel
`OAC Office of Advanced Cyberinfrastructure (OAC)
`CSE Direct For Computer & Info Scie & Enginr
`
`Start Date:
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`August 15, 1996
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`End Date:
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`July 31, 1998 (Estimated)
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`Awarded Amount to Date:
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`$100,000.00
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`Investigator(s):
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`Andrew Chien achien@cs.uchicago.edu (Principal Investigator)
`Rajesh Gupta (Co-Principal Investigator)
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`Sponsor:
`
`University of Illinois at Urbana-Champaign
`1901 South First Street
`Champaign, IL 61820-7406 (217)333-2187
`
`NSF Program(s):
`
`ADVANCED COMP RESEARCH PROGRAM,
`COMPUTER SYSTEMS ARCHITECTURE
`
`Program Reference Code(s):
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`9216, HPCC
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`Program Element Code(s):
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`4080, 4715, Z665
`
`ABSTRACT
`
`Application software for 100 TeraOps machines be based on the increasing use of
`component software (libraries, GUIs, problem solving environments) and extensive use of
`interoperability frameworks (CORBA, OLE, SOM, etc.), producing applications which are
`complex conglomerates of variegated programs. To support these applications, the
`machine must present a programmable interface (i.e. efficient shared address spaces and
`data movement) and scaleable high performance. This project will study a flexible machine
`architecture that recognizes these technological realities and not only supports advanced
`software structures, but exploits them to configure its programmable hardware, adapting
`itself to the application. The programming flexibility can provide a wide range of
`convenient interfaces, ranging from uniform cache-coherent shared memory, to clusters of
`smaller shared memory systems, to fully distributed memory. In addition to a range of
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`https://www.nsf.gov/awardsearch/showAward?AWD_ID=9634947
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`1/2
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`Intel Exhibit 1010 - 9
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`7/30/2020
`
`NSF Award Search: Award#9634947 - PDS: A Flexible Architecture for Executing Component Software at 100 Teraops
`interfaces, this flexible machine can customize both operations and protocols, exploiting
`appropriate mechanisms and policies to minimize the critical performance aspect--
`communication--at all levels of the system. This machine design leverages the wealth of
`research into optimal architectural mechanisms, customizable cache-coherence, as well as
`technological advances in interprocedural analysis, programmable hardware, and hardware
`synthesis technology, to achieve general-purpose high performance.
`
`
`
`Please report errors in award information by writing to: awardsearch@nsf.gov.
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`https://www.nsf.gov/awardsearch/showAward?AWD_ID=9634947
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`2/2
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`Intel Exhibit 1010 - 10
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