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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`INTEL CORPORATION,
`Petitioner,
`v.
`FG SRC LLC,
`Patent Owner.
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`IPR2020-01449
`Patent No. 7,149,867
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`DECLARATION OF WILLIAM MANGIONE-SMITH, PH.D., IN
`SUPPORT OF FG SRC LLC’S RESPONSE TO PETITION
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`I, Dr. William Mangione-Smith, under the penalty of perjury under the laws
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`of the United States, declare that the following is true and correct based on the best
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`of my ability.
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`Date: July 2, 2021
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`Signed:
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`WILLIAM MANGIONE-SMITH, PH.D.
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`1.
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`I have been retained by DiMuro Ginsberg, P.C., as an independent
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`technical expert in the Inter Partes Review dispute between FG SRC, and Intel
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`Corp, case, No. IPR2020-01449 which involves U.S. Patent No. 7,149,867 (“’867
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`Patent”).
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`2.
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`I have been paid for my work as a technical expert at my customary
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`hourly rate. My compensation does not in any way depend on the outcome of this
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`matter, and I have no personal interest in the outcome of this matter.
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`I.
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`Qualifications
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`3. My technical background and experience cover most aspects of
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`computer system design, including low level circuitry, computer architecture,
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`computer networking, digital rights management, cryptography, digital media,
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`communications, information technology, application software, client-server
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`application, Web technology, and system software (e.g., operating systems and
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`compilers). I am a member of the Institute of Electrical and Electronics Engineers
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`and the Association for Computing Machinery, which are the two most significant
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`professional organizations in my profession. I have been employed as a design
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`engineer, research engineer, professor, and technical expert. Over my professional
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`career, I have been an active inventor with 121 issued U.S. patents, 200 published
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`and pending U.S. patent applications and many unpublished U.S. patent
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`applications.
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`4.
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`From 1984 until 1991, I attended the University of Michigan in Ann
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`Arbor, Michigan, where I was awarded the degrees of Bachelor of Science and
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`Engineering, Master of Science and Engineering, and Doctor of Philosophy. My
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`doctoral research focused on high performance computing systems including
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`computer architecture, applications and operating system software, and compiler
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`technology. One of my responsibilities during my graduate studies included
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`teaching senior undergraduate students who were about to enter the profession.
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`5.
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`After graduating from the University of Michigan, I was employed by
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`Motorola in Schaumburg, Illinois. While at Motorola, I was part of a team
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`designing and manufacturing the first commercial battery-powered product capable
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`of delivering Internet email over a wireless (i.e., radio frequency) link and one of
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`the first personal digital assistants. I also served as the lead architect on the
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`second-generation of this device with control over the entire system design
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`including the memory subsystem architecture, embedded processor, ASIC, power
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`system, and analog circuitry. Part of my responsibilities at Motorola involved the
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`specification, design, and testing of system control Application-Specific Integrated
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`Circuits (“ASICs”). I conducted the initial research and advanced design that
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`resulted in the Motorola M*Core embedded microprocessor. M*Core was
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`designed to provide the high performance of desktop microprocessors with the low
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`power of contemporaneous embedded processors. The M*Core received
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`widespread use in many communications products including various cellular
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`handsets, advanced pagers, and embedded infrastructure.
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`6.
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`From 1995 until 2005, I was employed by the University of California
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`at Los Angeles (“UCLA”) as a professor of Electrical Engineering. I was the
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`director of the laboratory for Compiler and Architecture Research in Embedded
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`Systems (“CARES”) and served as the field chair for Embedded Computing
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`Systems. The CARES research team focused on research, engineering, and design
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`challenges in the context of battery-powered and multi-media mobile computing
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`devices. One of the key developments of my lab was the Mediabench software
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`tool, which is widely used to design and evaluate multi-media embedded devices.
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`Key elements of Mediabench include software that is essential for modern digital
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`wireless communications. My primary responsibility, in addition to classroom
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`teaching, involved directing the research and training of graduate students. I was a
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`tenured member of the faculty and had responsibilities for teaching as well as
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`scholarly research. My colleagues at UCLA were some of the leading scientists
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`and engineers in the world with a long list of innovations from computer network
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`security devices to the nicotine patch. The graduate student researchers in my
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`laboratory came from a diverse set of backgrounds, all with undergraduate degrees
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`in computer engineering, electrical engineering, or computer science, many with
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`multiple years of experience working as professional engineers in areas such as
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`digital rights management, cryptography, and some combination of digital media,
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`communications, information technology, software development, computer system
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`design, or computer science and ASIC circuit design.
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`7.
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`From 2005 until 2009, I was employed at Intellectual Ventures in
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`Bellevue, Washington. My responsibilities at Intellectual Ventures included
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`business development, technology assessment, market forecasting, university
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`outreach, collaborative inventing, intellectual property licensing support, and
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`intellectual property asset pricing. My colleagues and co-inventors at Intellectual
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`Ventures included the former lead intellectual property strategist at Intel, Intel’s
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`former lead IP counsel, Microsoft’s former chief software architect, the founder of
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`Microsoft research, the designer of the Mach operating system, the architect of the
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`U.S. Defense Department’s Strategic Defense Initiative, the founder of Thinking
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`Machines (a seminal parallel processing computer system), and Bill Gates. I had
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`responsibility for hiring and managing over 15 staff members including multiple
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`Ph.Ds. with degrees in electrical engineering or computer science, and decades of
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`experience in product design and engineering.
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`8.
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`A summary of some of my qualifications for forming the opinions in
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`this declaration are as follows: I have more than 30 years of experience as a
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`computer architect, computer system designer, communication system designer,
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`educator, and as an executive in the PC and electronics business. I am also a
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`member of several professional associations, such as the ACM and IEEE, and have
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`been intimately involved in professional research through the International
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`Symposium on Microarchitecture (Program Chair for 26th and General Chair for
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`36th), IEEE Transactions on Computers (Associate Editor), ACM Transactions on
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`Embedded Computing Systems (Associate Editor), and IEEE Computer (Associate
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`Editor). I also have been on the program committees for ISCA, MICRO, ISLPED,
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`Network Processors Workshop, FPL, Complexity-Effective Design, RAW,
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`Workshop on Mediaprocessors, and DSP, FPT, and INTERACT.
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`9.
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`I also have extensive experience and expertise with FPGA technology
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`in general and reconfigurable computing in particular. My research was funded by
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`the US Defense Advanced Research Projects Agency (DARPA), published in
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`leading journals in my field, and appeared on the cover of Scientific American
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`(June 1997). Specific research areas included cryptography, network security,
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`fault-tolerance, and intellectual property protection.
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`10. For further details regarding my employment and academic history,
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`please refer to my curriculum vitae provided in Appendix A to my declaration
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`EX2027 in this matter.
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`II. Basis Of Opinions
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`11. The basis and reasoning of my opinions include my education,
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`training, and experience as an engineer, including my 30 years of experience
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`designing microprocessors. In the course of conducting my analysis and forming
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`my opinions, I have further considered the materials listed below:
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`a. U.S. Patent No. 7,149,867 to Daniel Poznanovic, et al., filed June16,
`2004, and issued on December12, 2006 (“’867 patent”) and its file
`history;
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`b. X. Zhang et al., Architectural Adaptation of Application-Specific
`Locality Optimizations, IEEE (1997) (“Zhang”);
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`c. R. Gupta, Architectural Adaptation in AMRM Machines, IEEE (2000)
`(“Gupta”);
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`d. A. Chien and R. Gupta, MORPH: A System Architecture for Robust
`Higher Performance Using Customization,” IEEE (1996)(“Chien”);
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`e. Chien et al., Safe and Protected Execution for the Morph/AMRM
`Reconfigurable Processor, IEEE (1999);
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`f. Declaration of Stanley Shanfield, Ph.D.;
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`g. Declaration of Rajesh K. Gupta;
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`h. Provision Application No. 60-479,339;
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`i. 2020-08-10 Intel's Petition for IPR Review of U.S. Patent No.
`7,149,867;
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`j. U.S. Patent 8,713,518;
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`k. Book: John L. Hennessy and David A. Patterson, “Computer
`Architecture: A Quantitative Approach” (The Morgan Kaufmann Series
`in Computer Architecture and Design); and
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`l. Book: David Culler, “Parallel Computer Architecture: A
`Hardware/Software Approach” (The Morgan Kaufmann Series in
`Computer Architecture and Design);
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`m. Intel’s IPR petition in this matter and its exhibits;
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`n. Declaration Of Ryan Kastner, Ph.D. In Support Of FG SRC LLC’s
`Opening Claim Construction Brief in FG SRC LLC v. Intel Corp., No.
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`6:20-cv-00315-ADA (W.D. Texas), filed April 24, 2020;
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`o. FG’SRC’s Preliminary Response in this proceeding (Paper 9);
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`p. Declaration Of Vojin G. Oklobdzija, Ph.D., In Support Of FG SRC
`LLC’s Preliminary Response (EX2001)1;
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`q. Institution Decision in this proceeding (Paper 13);
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`r. and any other materials referenced herein.
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`III. Level Of Ordinary Skill In The Art
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`12. My opinions in this declaration are based on the understanding of a
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`person of ordinary skill in the art at the time of the invention of the claims in the
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`’867 Patent.
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`13.
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`In assessing the level of skill of a person of ordinary skill in the art, I
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`have considered the type of problems encountered in the art, the prior solutions to
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`those problems found in the prior art references, the rapidity with which
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`innovations are made, the sophistication of the technology, the level of education
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`of active workers in the field, and my own experience working with those of skill
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`in the art at the time of the invention.
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`14. A person of ordinary skill in the art (“POSITA”) at the time of the
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`filing of the ’867 patent would typically have at least an M.S. Degree in Computer
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`Engineering, Computer Science, or Electrical Engineering, or equivalent work
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`1 I have reviewed EX2001 in detail and incorporated and reproduced
`particularly relevant portions thereof in my report. I have reviewed all such portions
`in detail and confirm that it accurately reflects my opinions.
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`experience, along with at least three years of experience related specifically to
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`computer architecture, hardware design, and reconfigurable processors. In
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`addition, a POSITA would be familiar with hardware description languages and
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`design tools and methodologies used to program a reconfigurable processor.
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`15.
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`I am very familiar with this level of skill. In the course of my 30
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`years of processor design and research, I have supervised and worked with
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`engineers in this field having the level of skill identified above.
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`IV. Legal Framework
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`16. A patent has several components, including an abstract, drawings, a
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`written description detailing different embodiments of the invention (i.e., the
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`specification), and numbered claims at the end of the patent. It is the numbered
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`claims that define metes and bounds of the properties that the patentee has the right
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`to exclude other from infringing.
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`17.
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`I understand that the words of a claim are generally given their
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`ordinary and customary meaning, that is, the meaning that the term would have to
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`a person of ordinary skill in the art in question at the time of the invention.
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`18.
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`I understand that a claim term that does not use the word “means” is
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`presumed not to be a means-plus-function term. I understand that a term that does
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`not use the word “means” would be construed as a means-plus-function term if it
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`does not describe structure to a POSITA. Conversely, I understand that if a term
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`describes structure to a POSITA, it is not a means-plus-function term.
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`19.
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`I understand that a patent, once issued or granted, is entitled to a
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`presumption of validity. However, this presumption can be overcome by clear and
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`convincing evidence to the contrary. Validity may be challenged post-issuance,
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`and courts may invalidate the patent, on the ground that the patent fails to meet one
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`or more statutory requirements, e.g., by claiming a non-patentable subject matter,
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`such as an abstract idea, in violation of 35 U.S.C. § 101; by being not novel and
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`anticipated by prior art under § 102; by being obvious in view of prior art under §
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`103; or lacking sufficient disclosures or being indefinite, in violation of § 112.
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`20.
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`I understand that Section 102 first defines “prior art” that would
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`anticipate and, thus, invalidate the patent. The term “prior art” is a patent term of
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`art for the technology that was known or used before the filing of the patent. For
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`example, if the subject matter of the invention was already patented or described in
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`a printed publication anywhere in the world before the invention claimed in the
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`patent, such prior art would invalidate the patent. 35 U.S.C. § 102(a) (pre-AIA).
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`21.
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`I understand that § 103 is broader than § 102 in a sense that § 103
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`forbids issuance of a patent even if “the invention is not identically disclosed or
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`described as set forth in section 102, if the differences between the subject matter
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`sought to be patented and the prior art are such that the subject matter as a whole
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`would have been obvious at the time the invention was made to a person having
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`ordinary skill in the art to which said subject matter pertains.” 35 U.S.C. § 103(a)
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`(pre-AIA).
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`22.
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`I understand that, measuring the obviousness under § 103, a court
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`determines “the scope and content of the prior art,” ascertains “differences between
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`the prior art and the claims at issue,” and resolves “the level of ordinary skill in the
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`pertinent art.” Graham v. John Deere Co., 383 U.S. 1, 17 (1966). Secondary
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`considerations such as “commercial success, long felt but unsolved needs, failure
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`of others . . . might be utilized to give light to the circumstances surrounding the
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`origin of the subject matter sought to be patented.” Id. at 17-18; see KSR Int’l Co.
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`v. Teleflex Inc., 550 U.S. 398, 415 (2007) (“Graham set forth a broad inquiry and
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`invited courts, where appropriate, to look at any secondary considerations that
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`would prove instructive.”).
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`23.
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`It is my understanding that the information that is used to evaluate
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`whether an invention is new and not obvious is generally referred to as “prior art.”
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`Prior art generally includes U.S. and foreign patents and U.S. and foreign printed
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`publications (e.g., published patent applications (before issued as a patent), books,
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`journal publications, presentation files, posters, articles on websites, product
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`manuals, etc.) that existed before the earliest filing date (the “effective filing date”)
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`of the claims in the patent. A patent will be prior art if it was filed before the
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`effective filing date of the claimed invention, while a printed publication will be
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`prior art if it was publicly available before that date.
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`24.
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`In addition to the patents and printed publications, a product used in
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`public or on sale in the U.S. more than one year prior to the effective filing date of
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`a patent can be prior art to that patent. I understand that a product is considered
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`“on sale” when (i) the product embodying the invention is offered for commercial
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`sale, and (ii) the invention was ready for patenting. An invention is shown to be
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`“ready for patenting” when there is proof of a reduction to practice or proof that
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`prior to the critical date the inventor had prepared drawings or other descriptions of
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`the invention that were sufficiently specific to enable a person skilled in the art to
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`practice the invention.
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`25.
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`It is my understanding that a claimed invention is not patentable if it
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`would have been obvious to a person of ordinary skill in the field of the invention
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`at the time the invention was made.
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`26.
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`It is my understanding that the following standards govern the
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`determination of whether a claim in a patent is obvious.
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`27. To find a claim in a patent obvious, one must make certain findings
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`regarding the claimed invention and the prior art. Specifically, the obviousness
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`question requires consideration of four factors:
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` the scope and content of the prior art;
` the differences between the prior art and the claims at issue;
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` the knowledge of a person of ordinary skill in the pertinent art; and
` whatever objective factors indicating obviousness or non-obviousness may
`be present in any particular case.
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`28.
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`It is my understanding that the obviousness inquiry should not be
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`done in hindsight but must be done using the perspective of a person of ordinary
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`skill in the relevant art as of the effective filing date of the patent claim. The
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`prohibition against using hindsight applies to both the invention and the
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`identification of the problem that the invention solves.
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`29.
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`It is my understanding that the obviousness inquiry may also consider
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`certain objective indicia of non-obviousness. Such objective factors indicating
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`obviousness or non-obviousness may include: commercial success of products
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`covered by the patent claims; a long-felt need for the invention; failed attempts by
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`others to make the invention; copying of the invention by others in the field;
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`unexpected results achieved by the invention; praise of the invention by the
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`infringer or others in the field; the taking of licenses under the patent by others;
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`expressions of surprise by experts and those skilled in the art at the making of the
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`invention; and the patentee proceeded contrary to the accepted wisdom of the prior
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`art.
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`30. With respect to the evidence offered for each secondary consideration,
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`one must ascertain whether there is a nexus between the claimed invention and the
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`evidence establishing the secondary consideration (commercial success, industry
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`praise, etc.) and determine the value of secondary-considerations evidence for
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`rebutting a prima facie case of obviousness.
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`31.
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`I understand that the obviousness analysis requires a comparison of
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`the properly construed claim language to the prior art on a limitation-by-limitation
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`basis. The Supreme Court in KSR elaborated upon the framework for analyzing
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`obviousness it had set forth in previous cases. See 550 U.S. 398. KSR rejected the
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`Federal Circuit’s rigid application of the teaching, suggestion, or motivation test
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`for obviousness in favor of an expansive and flexible approach using common
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`sense. See id. at 415-22. KSR specifically cautioned against granting patents that
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`claim nothing more than combinations of known elements driven by non-
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`innovative factors such as market demands. Id. at 415-19. The Court there also
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`stressed the need for caution before upholding the validity of patents that are
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`merely combinations of elements found in the prior art. Id. The Court has
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`observed that, if a person of ordinary skill in the art can implement the claimed
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`invention as a predictable variation of a known invention, it is obvious. Id. Also,
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`“hindsight” reconstruction cannot be used to combine references together to reach
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`a conclusion of obviousness. Id. at 421.
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`32.
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`It is my understanding that exemplary rationales that may support a
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`conclusion of obviousness include:
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` combining prior art elements according to known methods to yield
`predictable results;
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` simple substitution of one known element for another to obtain predictable
`results;
` use of known techniques to improve similar devices (methods or products)
`in the same way;
` applying a known technique to a known device (method or product) ready
`for improvement to yield predictable results;
` “obvious to try,” i.e., choosing from a finite number of identified,
`predictable solutions with a reasonable expectation of success;
` known work in one field of endeavor may prompt variations of it for use in
`either the same field or a different one based on design incentives or other
`market forces if the variations would have been predictable to one of
`ordinary skill in the art; and
` some teaching, suggestion, or motivation in the prior art that would have led
`one of ordinary skill to modify the prior art reference or to combine prior art
`reference teachings to arrive at the claimed invention.
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`33. Thus, when considering a prior art reference for purposes of an
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`obviousness analysis, I have been informed that a reference must be taken for
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`everything it teaches.
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`34.
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`I understand that a claim might be obvious in light of a single
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`reference, without the need to combine references, if the elements of the claim that
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`are not found explicitly or inherently in the reference can be supplied by the
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`knowledge of one skilled in the art, including the common sense of one of skill in
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`the art.
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`35. An obviousness evaluation can also be based on a combination of
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`multiple prior art references. The prior art references themselves may provide a
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`suggestion, motivation, or reason to combine, but other times the nexus linking two
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`or more prior art references is simple common sense. I further understand that an
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`obviousness analysis recognizes that market demand, rather than scientific
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`literature, often drives innovation, and that a motivation to combine references may
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`be supplied by the direction of the marketplace.
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`36.
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`I understand that practical and common-sense considerations should
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`guide a proper obviousness analysis, because familiar items may have obvious uses
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`beyond their primary purposes. A person of ordinary skill in the art looking to
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`overcome a problem will often be able to fit the teachings of multiple publications
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`together like pieces of a puzzle. An obviousness analysis, therefore, takes into
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`account the inferences and creative steps that a person of ordinary skill in the art
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`would employ under the circumstances.
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`37.
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`I understand that a particular combination may be proven obvious
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`merely by showing that it was obvious to try the combination. For example, when
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`there is a design need or market pressure to solve a problem and there are a finite
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`number of identified, predictable solutions, a person of ordinary skill has good
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`reason to pursue the known options within his or her technical grasp because the
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`result is likely the product not of innovation but of ordinary skill and common
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`sense which led to a reasonable expectation of success.
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`38.
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`It is my understanding that the combination of familiar elements
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`according to known methods is likely to be obvious when it does no more than
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`yield predictable results. When a work is available in one field of endeavor, design
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`incentives and other market forces can prompt variations of it, either in the same
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`field or a different one.
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`39.
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`I understand that when a patent simply arranges known elements with
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`each performing the same function it had been known to perform and yields no
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`more than one of ordinary skill in the art would reasonably expect from such an
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`arrangement, the combination is obvious. A proper obviousness analysis focuses
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`on what was known or obvious to a person of ordinary skill in the art, not just the
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`patentee. Accordingly, any need or problem known in the field of endeavor at the
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`time of invention and addressed by the patent can provide a reason for combining
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`the elements in the manner claimed.
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`40.
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`In sum, it is my understanding that prior art teachings are properly
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`combined where a person of ordinary skill in the art, having the understanding and
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`knowledge reflected in the prior art and motivated by the general problem facing
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`the inventor, would have been led to make the combination of elements recited in
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`the claims.
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`41. Under this analysis, the prior art references, or any need or problem
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`known in the relevant field at the time of the invention, can provide a reason for
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`combining the elements of multiple prior art references in the claimed manner.
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`But, as stated previously, I understand that “hindsight” reconstruction cannot be
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`used to combine references together to reach a conclusion of obviousness.
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`V. Conventional Computer Architecture
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`42. Conventional computers utilize general purpose processors (aka
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`microprocessors) employing a Von Neumann architecture. In a conventional
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`computer, hardware is fixed and cannot be changed after manufacturing. To
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`execute a software program, the processor goes through a fixed routine of steps
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`called the fetch-execute cycle consisting of instruction fetch, instruction decode,
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`instruction execution, data memory access, and data write back.
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`43. Since 1965, the speed of processors has risen exponentially, which
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`predicted that the number of transistors on processors would double nearly every
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`24 months (Moore’s law). Moore’s law held true until the early 2000s, when
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`microprocessor manufacturers were no longer able to dramatically increase
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`processor performance by increasing transistor density. Focus shifted to multicore
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`chips to continue improving processor performance. This shift has resulted in
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`microprocessors with much higher power consumption, which has made electricity
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`a considerable operating expense for large computing centers.
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`44. At the time of the ’867 patent, there was considerable pressure in the
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`industry for computing systems with drastically higher performance, lower
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`operating expense, lower power usage, and lower space requirements. The
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`inventions of the ’867 patent very drastically improved all of these areas. It is my
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`understanding that addressing a long-felt industry need is an important indication
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`of non-obviousness which must be considered in any obviousness analysis.
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`45. The ’867 patent relates to the use of reconfigurable processors such as
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`FPGAs. Ex. 1001, 1:16-24, 5:26-29. An FPGA is a reprogrammable integrated
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`circuit that contains an array of programmable logic blocks and memory elements
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`connected via a programmable interconnect. FPGA are programmable to perform
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`specific functions. Programming an FPGA creates a hardware accelerated
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`implementation of a particular algorithm that efficiently executes the algorithm.
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`Hardware is thus able to adapt to the requirements of the software. For example,
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`hardware can be designed to add two 64-bit number together. If a subsequent
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`design works with 32-bit numbers, the hardware can be reprogrammed for a more
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`efficient and optimized configuration. A binary file called bitstream is used to
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`configure an FPGA. Reconfigurable processors like FPGA’s thus do not use
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`software “instructions” like a conventional CPU.
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`46. Conventional CPUs, on the other hand, execute an algorithm by
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`performing a sequence of software instructions. This sequencing allows great
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`flexibility in a conventional CPU; it can implement any algorithm. But it is unable
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`to be customized towards the any particular algorithm, because the hardware is
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`fixed. Therefore, while a conventional CPU is more versatile, FPGAs are much
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`more efficient at the particular algorithm for which their hardware is configured.
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`47. A simple memory request for data is issued by the processor when it
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`is required for computation. Prefetching, in contrast, requests data before it is
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`required, so that it is available when needed. To perform this task, the prefetch
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`unit must be configured to know what data to retrieve, and when.
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`VI. The Prior Art
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`48. Dr. Shanfield testifies that “unlike general-purpose processors, which
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`have fixed hardware, FPGA processors have user-programmable functional units
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`and interconnections that are customizable for whatever particular software
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`application is to be run on the processor. See Ex. 1001, 6:5-19. Thus, instead of
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`adapting a program’s instructions to match the requirements of the computer
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`hardware resources as in a conventional general-purpose processor, the hardware
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`resources of an FPGA (or related programmable logic technology) are
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`essentially adapted to conform to the program (and specifically, to perform the
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`algorithms in the program using reconfigurable hardware logic circuits).” Ex.
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`1006, ¶ 73 (emphasis added).
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`49. Thus, Dr. Shanfield admits that an FPGA does not have program
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`instructions, and instead is adapted to conform to the program. This admission
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`disqualifies Zhang, Chien, and Gupta, as they are all dealing with a fixed hardware
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`CPU which runs under the program instructions, according to Dr. Shanfield’s own
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`declaration. Dr. Shanfield further opines that “some of the names given to
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`computer processors that are implemented in FPGA include “FPGA processors,”
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`“reconfigurable processors,” “soft processors,” and “soft processor cores.” Id.
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`This matches the terminology used in the ’867 patent. In contrast, Zhang, Chien,
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`and Gupta are referring to a “fixed function hard wired CPU or processor”
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`operating under the program’s instructions, i.e., conventional CPUs.
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`50. Dr. Shanfield recognizes that the ’867 patent includes a reconfigurable
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`processor:
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`The ’867 patent seeks to accomplish this by employing a ‘data
`prefetch unit’ to prefetch from memory ‘only data required for
`computation … within
`the memory hierarchy’ of the
`reconfigurable processor before the data is needed for
`processing. Id., 7:23-8:41. Logic block 300 is ‘a simple logic
`block’ that may include computational functional units 301,
`control functional units (not shown), and data access units 302,
`303 and 403. Id., 7:25-28. Logic block 300 can read and write
`data stored on ‘memory device 305 or block RAM memory
`307’ of the reconfigurable processor. Id., 7:28-32. Also
`attached to the reconfigurable processor is the external
`memory at the top of Figure 5.”
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`Ex. 1006, ¶ 79 (emphasis added). This differentiates the ’867 patent substantially
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`from the asserted prior art in Chien, Zhang, and Gupta.
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`51. The very same argument was cited as a reason for Allowance issued
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`on July 26, 2006, as cited by Dr. Shanfield:
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`Specifically the prior art of record does not teach in combination
`a reconfigurable processor with a data prefetch unit,” “only
`fetching computational data required by an algorithm in addition
`to a first memory and the prefetch unit being configurable to
`conform to the requirements (needs) of a particular algorithm
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`where the data prefetch unit is configured to match format and
`location of the [data] in the second memory (claim 1).
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`Ex. 1002, at 231. Chien, Zhang and Gupta are therefore prior art that was
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`considered in the prosecution of the ’867 patent.
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`A.
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`Chien
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`52. Chien and Gupta’s MORPH concept is a flexible 100 TeraOp (100
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`trillion operations) architecture.
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`Ex. 1005, at Fig. 1.
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`53.
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` Chien envisions 8192 processing nodes and memory elements
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`embedded in a scalable interconnect.
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`Ex. 1005, at 10.
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`54. Each of these processing nodes also includes cache memory (L1, L2)
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`that can be shared among CPU’s.
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`Ex. 1005, at 10.
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`55. Chien recognizes the benefits of reconfigurable logic.
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`Ex. 1005, at 7.
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`56. Nevertheless, the use of FPGA logic (reconfigurable processor of our
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`invention) in MORPH was intended only for small local blocks of customization.
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`MORPH clearly teaches away from the use of reconfigurable logic for application-
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`specific functional units or co