UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`
`
`INTEL CORPORATION,
`Petitioner,
`v.
`FG SRC LLC,
`Patent Owner.
`
`
`
`
`
`
`
`IPR2020-01449
`Patent No. 7,149,867
`
`
`
`
`
`
`
`
`
`
`
`
`
`DECLARATION OF WILLIAM MANGIONE-SMITH, PH.D., IN
`SUPPORT OF FG SRC LLC’S RESPONSE TO PETITION
`
`
`
`
`
`I, Dr. William Mangione-Smith, under the penalty of perjury under the laws
`
`of the United States, declare that the following is true and correct based on the best
`
`of my ability.
`
`
`
`Date: July 2, 2021
`
`Signed:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`WILLIAM MANGIONE-SMITH, PH.D.
`
`
`
`
`
`
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`
`
`INTEL CORPORATION,
`Petitioner,
`v.
`FG SRC LLC,
`Patent Owner.
`
`
`
`
`
`
`
`IPR2020-01449
`Patent No. 7,149,867
`
`
`
`
`
`
`
`
`
`
`
`
`
`DECLARATION OF WILLIAM MANGIONE-SMITH, PH.D., IN
`SUPPORT OF FG SRC LLC’S RESPONSE TO PETITION
`
`
`
`
`
`I, Dr. William Mangione-Smith, under the penalty of perjury under the laws
`
`of the United States, declare that the following is true and correct based on the best
`
`of my ability.
`
`
`
`Date: July 2, 2021
`
`Signed:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`WILLIAM MANGIONE-SMITH, PH.D.
`
`
`
`
`
`
`
`1.
`
`I have been retained by DiMuro Ginsberg, P.C., as an independent
`
`technical expert in the Inter Partes Review dispute between FG SRC, and Intel
`
`Corp, case, No. IPR2020-01449 which involves U.S. Patent No. 7,149,867 (“’867
`
`Patent”).
`
`2.
`
`I have been paid for my work as a technical expert at my customary
`
`hourly rate. My compensation does not in any way depend on the outcome of this
`
`matter, and I have no personal interest in the outcome of this matter.
`
`I.
`
`Qualifications
`
`3. My technical background and experience cover most aspects of
`
`computer system design, including low level circuitry, computer architecture,
`
`computer networking, digital rights management, cryptography, digital media,
`
`communications, information technology, application software, client-server
`
`application, Web technology, and system software (e.g., operating systems and
`
`compilers). I am a member of the Institute of Electrical and Electronics Engineers
`
`and the Association for Computing Machinery, which are the two most significant
`
`professional organizations in my profession. I have been employed as a design
`
`engineer, research engineer, professor, and technical expert. Over my professional
`
`career, I have been an active inventor with 121 issued U.S. patents, 200 published
`
`and pending U.S. patent applications and many unpublished U.S. patent
`
`applications.
`
`
`
`2
`
`
`
`
`
`
`
`4.
`
`From 1984 until 1991, I attended the University of Michigan in Ann
`
`Arbor, Michigan, where I was awarded the degrees of Bachelor of Science and
`
`Engineering, Master of Science and Engineering, and Doctor of Philosophy. My
`
`doctoral research focused on high performance computing systems including
`
`computer architecture, applications and operating system software, and compiler
`
`technology. One of my responsibilities during my graduate studies included
`
`teaching senior undergraduate students who were about to enter the profession.
`
`5.
`
`After graduating from the University of Michigan, I was employed by
`
`Motorola in Schaumburg, Illinois. While at Motorola, I was part of a team
`
`designing and manufacturing the first commercial battery-powered product capable
`
`of delivering Internet email over a wireless (i.e., radio frequency) link and one of
`
`the first personal digital assistants. I also served as the lead architect on the
`
`second-generation of this device with control over the entire system design
`
`including the memory subsystem architecture, embedded processor, ASIC, power
`
`system, and analog circuitry. Part of my responsibilities at Motorola involved the
`
`specification, design, and testing of system control Application-Specific Integrated
`
`Circuits (“ASICs”). I conducted the initial research and advanced design that
`
`resulted in the Motorola M*Core embedded microprocessor. M*Core was
`
`designed to provide the high performance of desktop microprocessors with the low
`
`power of contemporaneous embedded processors. The M*Core received
`
`
`
`3
`
`
`
`
`
`
`
`widespread use in many communications products including various cellular
`
`handsets, advanced pagers, and embedded infrastructure.
`
`6.
`
`From 1995 until 2005, I was employed by the University of California
`
`at Los Angeles (“UCLA”) as a professor of Electrical Engineering. I was the
`
`director of the laboratory for Compiler and Architecture Research in Embedded
`
`Systems (“CARES”) and served as the field chair for Embedded Computing
`
`Systems. The CARES research team focused on research, engineering, and design
`
`challenges in the context of battery-powered and multi-media mobile computing
`
`devices. One of the key developments of my lab was the Mediabench software
`
`tool, which is widely used to design and evaluate multi-media embedded devices.
`
`Key elements of Mediabench include software that is essential for modern digital
`
`wireless communications. My primary responsibility, in addition to classroom
`
`teaching, involved directing the research and training of graduate students. I was a
`
`tenured member of the faculty and had responsibilities for teaching as well as
`
`scholarly research. My colleagues at UCLA were some of the leading scientists
`
`and engineers in the world with a long list of innovations from computer network
`
`security devices to the nicotine patch. The graduate student researchers in my
`
`laboratory came from a diverse set of backgrounds, all with undergraduate degrees
`
`in computer engineering, electrical engineering, or computer science, many with
`
`multiple years of experience working as professional engineers in areas such as
`
`
`
`4
`
`
`
`
`
`
`
`digital rights management, cryptography, and some combination of digital media,
`
`communications, information technology, software development, computer system
`
`design, or computer science and ASIC circuit design.
`
`7.
`
`From 2005 until 2009, I was employed at Intellectual Ventures in
`
`Bellevue, Washington. My responsibilities at Intellectual Ventures included
`
`business development, technology assessment, market forecasting, university
`
`outreach, collaborative inventing, intellectual property licensing support, and
`
`intellectual property asset pricing. My colleagues and co-inventors at Intellectual
`
`Ventures included the former lead intellectual property strategist at Intel, Intel’s
`
`former lead IP counsel, Microsoft’s former chief software architect, the founder of
`
`Microsoft research, the designer of the Mach operating system, the architect of the
`
`U.S. Defense Department’s Strategic Defense Initiative, the founder of Thinking
`
`Machines (a seminal parallel processing computer system), and Bill Gates. I had
`
`responsibility for hiring and managing over 15 staff members including multiple
`
`Ph.Ds. with degrees in electrical engineering or computer science, and decades of
`
`experience in product design and engineering.
`
`8.
`
`A summary of some of my qualifications for forming the opinions in
`
`this declaration are as follows: I have more than 30 years of experience as a
`
`computer architect, computer system designer, communication system designer,
`
`educator, and as an executive in the PC and electronics business. I am also a
`
`
`
`5
`
`
`
`
`
`
`
`member of several professional associations, such as the ACM and IEEE, and have
`
`been intimately involved in professional research through the International
`
`Symposium on Microarchitecture (Program Chair for 26th and General Chair for
`
`36th), IEEE Transactions on Computers (Associate Editor), ACM Transactions on
`
`Embedded Computing Systems (Associate Editor), and IEEE Computer (Associate
`
`Editor). I also have been on the program committees for ISCA, MICRO, ISLPED,
`
`Network Processors Workshop, FPL, Complexity-Effective Design, RAW,
`
`Workshop on Mediaprocessors, and DSP, FPT, and INTERACT.
`
`9.
`
`I also have extensive experience and expertise with FPGA technology
`
`in general and reconfigurable computing in particular. My research was funded by
`
`the US Defense Advanced Research Projects Agency (DARPA), published in
`
`leading journals in my field, and appeared on the cover of Scientific American
`
`(June 1997). Specific research areas included cryptography, network security,
`
`fault-tolerance, and intellectual property protection.
`
`10. For further details regarding my employment and academic history,
`
`please refer to my curriculum vitae provided in Appendix A to my declaration
`
`EX2027 in this matter.
`
`II. Basis Of Opinions
`
`11. The basis and reasoning of my opinions include my education,
`
`training, and experience as an engineer, including my 30 years of experience
`
`
`
`6
`
`
`
`
`
`
`
`designing microprocessors. In the course of conducting my analysis and forming
`
`my opinions, I have further considered the materials listed below:
`
`a. U.S. Patent No. 7,149,867 to Daniel Poznanovic, et al., filed June16,
`2004, and issued on December12, 2006 (“’867 patent”) and its file
`history;
`
`b. X. Zhang et al., Architectural Adaptation of Application-Specific
`Locality Optimizations, IEEE (1997) (“Zhang”);
`
`c. R. Gupta, Architectural Adaptation in AMRM Machines, IEEE (2000)
`(“Gupta”);
`
`d. A. Chien and R. Gupta, MORPH: A System Architecture for Robust
`Higher Performance Using Customization,” IEEE (1996)(“Chien”);
`
`e. Chien et al., Safe and Protected Execution for the Morph/AMRM
`Reconfigurable Processor, IEEE (1999);
`
`f. Declaration of Stanley Shanfield, Ph.D.;
`
`g. Declaration of Rajesh K. Gupta;
`
`h. Provision Application No. 60-479,339;
`
`i. 2020-08-10 Intel's Petition for IPR Review of U.S. Patent No.
`7,149,867;
`
`j. U.S. Patent 8,713,518;
`
`k. Book: John L. Hennessy and David A. Patterson, “Computer
`Architecture: A Quantitative Approach” (The Morgan Kaufmann Series
`in Computer Architecture and Design); and
`
`l. Book: David Culler, “Parallel Computer Architecture: A
`Hardware/Software Approach” (The Morgan Kaufmann Series in
`Computer Architecture and Design);
`
`m. Intel’s IPR petition in this matter and its exhibits;
`
`n. Declaration Of Ryan Kastner, Ph.D. In Support Of FG SRC LLC’s
`Opening Claim Construction Brief in FG SRC LLC v. Intel Corp., No.
`
`
`
`7
`
`
`
`
`
`
`
`6:20-cv-00315-ADA (W.D. Texas), filed April 24, 2020;
`
`o. FG’SRC’s Preliminary Response in this proceeding (Paper 9);
`
`p. Declaration Of Vojin G. Oklobdzija, Ph.D., In Support Of FG SRC
`LLC’s Preliminary Response (EX2001)1;
`
`q. Institution Decision in this proceeding (Paper 13);
`
`r. and any other materials referenced herein.
`
`III. Level Of Ordinary Skill In The Art
`
`12. My opinions in this declaration are based on the understanding of a
`
`person of ordinary skill in the art at the time of the invention of the claims in the
`
`’867 Patent.
`
`13.
`
`In assessing the level of skill of a person of ordinary skill in the art, I
`
`have considered the type of problems encountered in the art, the prior solutions to
`
`those problems found in the prior art references, the rapidity with which
`
`innovations are made, the sophistication of the technology, the level of education
`
`of active workers in the field, and my own experience working with those of skill
`
`in the art at the time of the invention.
`
`14. A person of ordinary skill in the art (“POSITA”) at the time of the
`
`filing of the ’867 patent would typically have at least an M.S. Degree in Computer
`
`Engineering, Computer Science, or Electrical Engineering, or equivalent work
`
`
`1 I have reviewed EX2001 in detail and incorporated and reproduced
`particularly relevant portions thereof in my report. I have reviewed all such portions
`in detail and confirm that it accurately reflects my opinions.
`
`
`
`8
`
`
`
`
`
`
`
`experience, along with at least three years of experience related specifically to
`
`computer architecture, hardware design, and reconfigurable processors. In
`
`addition, a POSITA would be familiar with hardware description languages and
`
`design tools and methodologies used to program a reconfigurable processor.
`
`15.
`
`I am very familiar with this level of skill. In the course of my 30
`
`years of processor design and research, I have supervised and worked with
`
`engineers in this field having the level of skill identified above.
`
`IV. Legal Framework
`
`16. A patent has several components, including an abstract, drawings, a
`
`written description detailing different embodiments of the invention (i.e., the
`
`specification), and numbered claims at the end of the patent. It is the numbered
`
`claims that define metes and bounds of the properties that the patentee has the right
`
`to exclude other from infringing.
`
`17.
`
`I understand that the words of a claim are generally given their
`
`ordinary and customary meaning, that is, the meaning that the term would have to
`
`a person of ordinary skill in the art in question at the time of the invention.
`
`18.
`
`I understand that a claim term that does not use the word “means” is
`
`presumed not to be a means-plus-function term. I understand that a term that does
`
`not use the word “means” would be construed as a means-plus-function term if it
`
`
`
`9
`
`
`
`
`
`
`
`does not describe structure to a POSITA. Conversely, I understand that if a term
`
`describes structure to a POSITA, it is not a means-plus-function term.
`
`19.
`
`I understand that a patent, once issued or granted, is entitled to a
`
`presumption of validity. However, this presumption can be overcome by clear and
`
`convincing evidence to the contrary. Validity may be challenged post-issuance,
`
`and courts may invalidate the patent, on the ground that the patent fails to meet one
`
`or more statutory requirements, e.g., by claiming a non-patentable subject matter,
`
`such as an abstract idea, in violation of 35 U.S.C. § 101; by being not novel and
`
`anticipated by prior art under § 102; by being obvious in view of prior art under §
`
`103; or lacking sufficient disclosures or being indefinite, in violation of § 112.
`
`20.
`
`I understand that Section 102 first defines “prior art” that would
`
`anticipate and, thus, invalidate the patent. The term “prior art” is a patent term of
`
`art for the technology that was known or used before the filing of the patent. For
`
`example, if the subject matter of the invention was already patented or described in
`
`a printed publication anywhere in the world before the invention claimed in the
`
`patent, such prior art would invalidate the patent. 35 U.S.C. § 102(a) (pre-AIA).
`
`21.
`
`I understand that § 103 is broader than § 102 in a sense that § 103
`
`forbids issuance of a patent even if “the invention is not identically disclosed or
`
`described as set forth in section 102, if the differences between the subject matter
`
`sought to be patented and the prior art are such that the subject matter as a whole
`
`
`
`10
`
`
`
`
`
`
`
`would have been obvious at the time the invention was made to a person having
`
`ordinary skill in the art to which said subject matter pertains.” 35 U.S.C. § 103(a)
`
`(pre-AIA).
`
`22.
`
`I understand that, measuring the obviousness under § 103, a court
`
`determines “the scope and content of the prior art,” ascertains “differences between
`
`the prior art and the claims at issue,” and resolves “the level of ordinary skill in the
`
`pertinent art.” Graham v. John Deere Co., 383 U.S. 1, 17 (1966). Secondary
`
`considerations such as “commercial success, long felt but unsolved needs, failure
`
`of others . . . might be utilized to give light to the circumstances surrounding the
`
`origin of the subject matter sought to be patented.” Id. at 17-18; see KSR Int’l Co.
`
`v. Teleflex Inc., 550 U.S. 398, 415 (2007) (“Graham set forth a broad inquiry and
`
`invited courts, where appropriate, to look at any secondary considerations that
`
`would prove instructive.”).
`
`23.
`
`It is my understanding that the information that is used to evaluate
`
`whether an invention is new and not obvious is generally referred to as “prior art.”
`
`Prior art generally includes U.S. and foreign patents and U.S. and foreign printed
`
`publications (e.g., published patent applications (before issued as a patent), books,
`
`journal publications, presentation files, posters, articles on websites, product
`
`manuals, etc.) that existed before the earliest filing date (the “effective filing date”)
`
`of the claims in the patent. A patent will be prior art if it was filed before the
`
`
`
`11
`
`
`
`
`
`
`
`effective filing date of the claimed invention, while a printed publication will be
`
`prior art if it was publicly available before that date.
`
`24.
`
`In addition to the patents and printed publications, a product used in
`
`public or on sale in the U.S. more than one year prior to the effective filing date of
`
`a patent can be prior art to that patent. I understand that a product is considered
`
`“on sale” when (i) the product embodying the invention is offered for commercial
`
`sale, and (ii) the invention was ready for patenting. An invention is shown to be
`
`“ready for patenting” when there is proof of a reduction to practice or proof that
`
`prior to the critical date the inventor had prepared drawings or other descriptions of
`
`the invention that were sufficiently specific to enable a person skilled in the art to
`
`practice the invention.
`
`25.
`
`It is my understanding that a claimed invention is not patentable if it
`
`would have been obvious to a person of ordinary skill in the field of the invention
`
`at the time the invention was made.
`
`26.
`
`It is my understanding that the following standards govern the
`
`determination of whether a claim in a patent is obvious.
`
`27. To find a claim in a patent obvious, one must make certain findings
`
`regarding the claimed invention and the prior art. Specifically, the obviousness
`
`question requires consideration of four factors:
`
` the scope and content of the prior art;
` the differences between the prior art and the claims at issue;
`
`
`
`12
`
`
`
`
`
`
`
` the knowledge of a person of ordinary skill in the pertinent art; and
` whatever objective factors indicating obviousness or non-obviousness may
`be present in any particular case.
`
`28.
`
`It is my understanding that the obviousness inquiry should not be
`
`done in hindsight but must be done using the perspective of a person of ordinary
`
`skill in the relevant art as of the effective filing date of the patent claim. The
`
`prohibition against using hindsight applies to both the invention and the
`
`identification of the problem that the invention solves.
`
`29.
`
`It is my understanding that the obviousness inquiry may also consider
`
`certain objective indicia of non-obviousness. Such objective factors indicating
`
`obviousness or non-obviousness may include: commercial success of products
`
`covered by the patent claims; a long-felt need for the invention; failed attempts by
`
`others to make the invention; copying of the invention by others in the field;
`
`unexpected results achieved by the invention; praise of the invention by the
`
`infringer or others in the field; the taking of licenses under the patent by others;
`
`expressions of surprise by experts and those skilled in the art at the making of the
`
`invention; and the patentee proceeded contrary to the accepted wisdom of the prior
`
`art.
`
`30. With respect to the evidence offered for each secondary consideration,
`
`one must ascertain whether there is a nexus between the claimed invention and the
`
`evidence establishing the secondary consideration (commercial success, industry
`
`
`
`13
`
`
`
`
`
`
`
`praise, etc.) and determine the value of secondary-considerations evidence for
`
`rebutting a prima facie case of obviousness.
`
`31.
`
`I understand that the obviousness analysis requires a comparison of
`
`the properly construed claim language to the prior art on a limitation-by-limitation
`
`basis. The Supreme Court in KSR elaborated upon the framework for analyzing
`
`obviousness it had set forth in previous cases. See 550 U.S. 398. KSR rejected the
`
`Federal Circuit’s rigid application of the teaching, suggestion, or motivation test
`
`for obviousness in favor of an expansive and flexible approach using common
`
`sense. See id. at 415-22. KSR specifically cautioned against granting patents that
`
`claim nothing more than combinations of known elements driven by non-
`
`innovative factors such as market demands. Id. at 415-19. The Court there also
`
`stressed the need for caution before upholding the validity of patents that are
`
`merely combinations of elements found in the prior art. Id. The Court has
`
`observed that, if a person of ordinary skill in the art can implement the claimed
`
`invention as a predictable variation of a known invention, it is obvious. Id. Also,
`
`“hindsight” reconstruction cannot be used to combine references together to reach
`
`a conclusion of obviousness. Id. at 421.
`
`32.
`
`It is my understanding that exemplary rationales that may support a
`
`conclusion of obviousness include:
`
` combining prior art elements according to known methods to yield
`predictable results;
`
`
`
`14
`
`
`
`
`
`
`
` simple substitution of one known element for another to obtain predictable
`results;
` use of known techniques to improve similar devices (methods or products)
`in the same way;
` applying a known technique to a known device (method or product) ready
`for improvement to yield predictable results;
` “obvious to try,” i.e., choosing from a finite number of identified,
`predictable solutions with a reasonable expectation of success;
` known work in one field of endeavor may prompt variations of it for use in
`either the same field or a different one based on design incentives or other
`market forces if the variations would have been predictable to one of
`ordinary skill in the art; and
` some teaching, suggestion, or motivation in the prior art that would have led
`one of ordinary skill to modify the prior art reference or to combine prior art
`reference teachings to arrive at the claimed invention.
`
`33. Thus, when considering a prior art reference for purposes of an
`
`obviousness analysis, I have been informed that a reference must be taken for
`
`everything it teaches.
`
`34.
`
`I understand that a claim might be obvious in light of a single
`
`reference, without the need to combine references, if the elements of the claim that
`
`are not found explicitly or inherently in the reference can be supplied by the
`
`knowledge of one skilled in the art, including the common sense of one of skill in
`
`the art.
`
`35. An obviousness evaluation can also be based on a combination of
`
`multiple prior art references. The prior art references themselves may provide a
`
`suggestion, motivation, or reason to combine, but other times the nexus linking two
`
`or more prior art references is simple common sense. I further understand that an
`
`
`
`15
`
`
`
`
`
`
`
`obviousness analysis recognizes that market demand, rather than scientific
`
`literature, often drives innovation, and that a motivation to combine references may
`
`be supplied by the direction of the marketplace.
`
`36.
`
`I understand that practical and common-sense considerations should
`
`guide a proper obviousness analysis, because familiar items may have obvious uses
`
`beyond their primary purposes. A person of ordinary skill in the art looking to
`
`overcome a problem will often be able to fit the teachings of multiple publications
`
`together like pieces of a puzzle. An obviousness analysis, therefore, takes into
`
`account the inferences and creative steps that a person of ordinary skill in the art
`
`would employ under the circumstances.
`
`37.
`
`I understand that a particular combination may be proven obvious
`
`merely by showing that it was obvious to try the combination. For example, when
`
`there is a design need or market pressure to solve a problem and there are a finite
`
`number of identified, predictable solutions, a person of ordinary skill has good
`
`reason to pursue the known options within his or her technical grasp because the
`
`result is likely the product not of innovation but of ordinary skill and common
`
`sense which led to a reasonable expectation of success.
`
`38.
`
`It is my understanding that the combination of familiar elements
`
`according to known methods is likely to be obvious when it does no more than
`
`yield predictable results. When a work is available in one field of endeavor, design
`
`
`
`16
`
`
`
`
`
`
`
`incentives and other market forces can prompt variations of it, either in the same
`
`field or a different one.
`
`39.
`
`I understand that when a patent simply arranges known elements with
`
`each performing the same function it had been known to perform and yields no
`
`more than one of ordinary skill in the art would reasonably expect from such an
`
`arrangement, the combination is obvious. A proper obviousness analysis focuses
`
`on what was known or obvious to a person of ordinary skill in the art, not just the
`
`patentee. Accordingly, any need or problem known in the field of endeavor at the
`
`time of invention and addressed by the patent can provide a reason for combining
`
`the elements in the manner claimed.
`
`40.
`
`In sum, it is my understanding that prior art teachings are properly
`
`combined where a person of ordinary skill in the art, having the understanding and
`
`knowledge reflected in the prior art and motivated by the general problem facing
`
`the inventor, would have been led to make the combination of elements recited in
`
`the claims.
`
`41. Under this analysis, the prior art references, or any need or problem
`
`known in the relevant field at the time of the invention, can provide a reason for
`
`combining the elements of multiple prior art references in the claimed manner.
`
`But, as stated previously, I understand that “hindsight” reconstruction cannot be
`
`used to combine references together to reach a conclusion of obviousness.
`
`
`
`17
`
`
`
`
`
`V. Conventional Computer Architecture
`
`
`
`42. Conventional computers utilize general purpose processors (aka
`
`microprocessors) employing a Von Neumann architecture. In a conventional
`
`computer, hardware is fixed and cannot be changed after manufacturing. To
`
`execute a software program, the processor goes through a fixed routine of steps
`
`called the fetch-execute cycle consisting of instruction fetch, instruction decode,
`
`instruction execution, data memory access, and data write back.
`
`43. Since 1965, the speed of processors has risen exponentially, which
`
`predicted that the number of transistors on processors would double nearly every
`
`24 months (Moore’s law). Moore’s law held true until the early 2000s, when
`
`microprocessor manufacturers were no longer able to dramatically increase
`
`processor performance by increasing transistor density. Focus shifted to multicore
`
`chips to continue improving processor performance. This shift has resulted in
`
`microprocessors with much higher power consumption, which has made electricity
`
`a considerable operating expense for large computing centers.
`
`44. At the time of the ’867 patent, there was considerable pressure in the
`
`industry for computing systems with drastically higher performance, lower
`
`operating expense, lower power usage, and lower space requirements. The
`
`inventions of the ’867 patent very drastically improved all of these areas. It is my
`
`
`
`18
`
`
`
`
`
`
`
`understanding that addressing a long-felt industry need is an important indication
`
`of non-obviousness which must be considered in any obviousness analysis.
`
`45. The ’867 patent relates to the use of reconfigurable processors such as
`
`FPGAs. Ex. 1001, 1:16-24, 5:26-29. An FPGA is a reprogrammable integrated
`
`circuit that contains an array of programmable logic blocks and memory elements
`
`connected via a programmable interconnect. FPGA are programmable to perform
`
`specific functions. Programming an FPGA creates a hardware accelerated
`
`implementation of a particular algorithm that efficiently executes the algorithm.
`
`Hardware is thus able to adapt to the requirements of the software. For example,
`
`hardware can be designed to add two 64-bit number together. If a subsequent
`
`design works with 32-bit numbers, the hardware can be reprogrammed for a more
`
`efficient and optimized configuration. A binary file called bitstream is used to
`
`configure an FPGA. Reconfigurable processors like FPGA’s thus do not use
`
`software “instructions” like a conventional CPU.
`
`46. Conventional CPUs, on the other hand, execute an algorithm by
`
`performing a sequence of software instructions. This sequencing allows great
`
`flexibility in a conventional CPU; it can implement any algorithm. But it is unable
`
`to be customized towards the any particular algorithm, because the hardware is
`
`fixed. Therefore, while a conventional CPU is more versatile, FPGAs are much
`
`more efficient at the particular algorithm for which their hardware is configured.
`
`
`
`19
`
`
`
`
`
`
`
`47. A simple memory request for data is issued by the processor when it
`
`is required for computation. Prefetching, in contrast, requests data before it is
`
`required, so that it is available when needed. To perform this task, the prefetch
`
`unit must be configured to know what data to retrieve, and when.
`
`VI. The Prior Art
`
`48. Dr. Shanfield testifies that “unlike general-purpose processors, which
`
`have fixed hardware, FPGA processors have user-programmable functional units
`
`and interconnections that are customizable for whatever particular software
`
`application is to be run on the processor. See Ex. 1001, 6:5-19. Thus, instead of
`
`adapting a program’s instructions to match the requirements of the computer
`
`hardware resources as in a conventional general-purpose processor, the hardware
`
`resources of an FPGA (or related programmable logic technology) are
`
`essentially adapted to conform to the program (and specifically, to perform the
`
`algorithms in the program using reconfigurable hardware logic circuits).” Ex.
`
`1006, ¶ 73 (emphasis added).
`
`49. Thus, Dr. Shanfield admits that an FPGA does not have program
`
`instructions, and instead is adapted to conform to the program. This admission
`
`disqualifies Zhang, Chien, and Gupta, as they are all dealing with a fixed hardware
`
`CPU which runs under the program instructions, according to Dr. Shanfield’s own
`
`declaration. Dr. Shanfield further opines that “some of the names given to
`
`
`
`20
`
`
`
`
`
`
`
`computer processors that are implemented in FPGA include “FPGA processors,”
`
`“reconfigurable processors,” “soft processors,” and “soft processor cores.” Id.
`
`This matches the terminology used in the ’867 patent. In contrast, Zhang, Chien,
`
`and Gupta are referring to a “fixed function hard wired CPU or processor”
`
`operating under the program’s instructions, i.e., conventional CPUs.
`
`50. Dr. Shanfield recognizes that the ’867 patent includes a reconfigurable
`
`processor:
`
`The ’867 patent seeks to accomplish this by employing a ‘data
`prefetch unit’ to prefetch from memory ‘only data required for
`computation … within
`the memory hierarchy’ of the
`reconfigurable processor before the data is needed for
`processing. Id., 7:23-8:41. Logic block 300 is ‘a simple logic
`block’ that may include computational functional units 301,
`control functional units (not shown), and data access units 302,
`303 and 403. Id., 7:25-28. Logic block 300 can read and write
`data stored on ‘memory device 305 or block RAM memory
`307’ of the reconfigurable processor. Id., 7:28-32. Also
`attached to the reconfigurable processor is the external
`memory at the top of Figure 5.”
`
`Ex. 1006, ¶ 79 (emphasis added). This differentiates the ’867 patent substantially
`
`from the asserted prior art in Chien, Zhang, and Gupta.
`
`51. The very same argument was cited as a reason for Allowance issued
`
`on July 26, 2006, as cited by Dr. Shanfield:
`
`Specifically the prior art of record does not teach in combination
`a reconfigurable processor with a data prefetch unit,” “only
`fetching computational data required by an algorithm in addition
`to a first memory and the prefetch unit being configurable to
`conform to the requirements (needs) of a particular algorithm
`
`
`
`21
`
`
`
`
`
`
`
`where the data prefetch unit is configured to match format and
`location of the [data] in the second memory (claim 1).
`
`Ex. 1002, at 231. Chien, Zhang and Gupta are therefore prior art that was
`
`considered in the prosecution of the ’867 patent.
`
`A.
`
`Chien
`
`52. Chien and Gupta’s MORPH concept is a flexible 100 TeraOp (100
`
`trillion operations) architecture.
`
`Ex. 1005, at Fig. 1.
`
`53.
`
` Chien envisions 8192 processing nodes and memory elements
`
`embedded in a scalable interconnect.
`
`
`
`
`
`22
`
`
`
`
`
`
`
`Ex. 1005, at 10.
`
`
`
`54. Each of these processing nodes also includes cache memory (L1, L2)
`
`that can be shared among CPU’s.
`
`Ex. 1005, at 10.
`
`55. Chien recognizes the benefits of reconfigurable logic.
`
`
`
`
`
`Ex. 1005, at 7.
`
`56. Nevertheless, the use of FPGA logic (reconfigurable processor of our
`
`invention) in MORPH was intended only for small local blocks of customization.
`
`MORPH clearly teaches away from the use of reconfigurable logic for application-
`
`specific functional units or co
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
