UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INTEL CORPORATION,
`Petitioner,
`v.
`FG SRC LLC,
`Patent Owner.
`
`IPR2020-01449
`Patent No. 7,149,867
`
`PATENT OWNER FG SRC LLC’S MOTION TO AMEND
`
`Paper No. 26
`Filed: May 26, 2021
`
`

`

`
`
`Exhibit No.
`2001
`2002
`2003
`
`2004
`
`2005
`
`2006
`
`2007
`2008
`
`2009
`2009-1
`
`2009-2
`
`2010
`
`2011
`
`2012
`
`2013
`
`LIST OF EXHIBITS
`
`Descriptions
`Declaration of Dr. Vojin Oklobdzija
`Cray, Britannica Online Encyclopedia
`Declaration of Brandon Freeman dated 10/25/18
`SRC Labs LLC and Saint Regis Mohawk Tribe v. Microsoft
`Corporation, No. 2:18-cv-00321-JLR, Dkt. 125 (W.D. Wash. Oct.
`25, 2018)
`Plaintiff’s Original Complaint For Patent Infringement in FG SRC
`LLC v. Intel Corp., No. 6:20-cv-00315-ADA (W.D. Texas), filed
`April 24, 2020
`Plaintiff’s First Amended Complaint For Patent Infringement in
`FG SRC LLC v. Intel Corp., No. 6:20-cv-00315-ADA (W.D.
`Texas), filed April 24, 2020
`Declaration of Mark Wollgast dated 09/10/18
`Xilinx, Inc. v. Saint Regis Mohawk Tribe, IPR2018-0195
`COTS Journal, UAVs Lead Push for Embedded Supercomputing
`Press Release: SRC Computers Chosen by Lockheed Martin for
`U.S. Army Program
`Declaration of Henning Schmidt
`Declaration of Henning Schmidt, Exhibit A, IEEE Xplore:
`Advanced Search
`Declaration of Henning Schmidt, Exhibit B, IEEE Xplore:
`Advanced Search Results
`Declaration Of Ryan Kastner, Ph.D. In Support Of FG SRC
`LLC’s Opening Claim Construction Brief in FG SRC LLC v. Intel
`Corp., No. 6:20-cv-00315-ADA (W.D. Texas), filed April 24,
`2020
`Peter McMahon, High Performance Reconfigurable Computing for
`Science and Engineering Applications (Thesis Oct. 2006).
`Caliga, Delivering Acceleration: The Potential for Increased HPC
`Application Performance Using Reconfigurable Logic
`D. A. Buell, D. Caliga, J. P. Davis, G. Quan, “The DARPA
`boolean equation benchmark on a reconfigurable computer,”
`Proceedings of the Military and Aerospace Programmable Logic
`Devices (MAPLD) Conference, Washington, DC, 8-10 September
`2004
`
`
`
`
`
`i
`
`

`

`Exhibit No.
`2014
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`2015
`
`2016
`
`2017
`
`2018
`
`2019
`
`2020
`
`2021
`
`2022
`2023
`
`2024
`
`2025
`
`2026
`2027
`
`Descriptions
`El-Araby, The Promise of High-Performance Reconfigurable
`Computing
`FG SRC LLC’s Opening Claim Construction Brief in FG SRC
`LLC v. Intel Corp., No. 6:20-cv-00315-ADA (W.D. Texas),
`filed April 24, 2020
`Kerr Machine Co. d/b/a Kerr Pumps v. Vulcan Industrial
`Holdings, LLC, No. 6:20-cv-00200, Text Order dated Aug. 2, 2020
`(W.D. Tex.)
`MultiMedia Content Mgmt LLC v. Dish Network L.L.C., No. 6:18-
`cv-00207, Dkt. 73 (W.D. Tex.)
`Solas OLED v. Dell Techs. Inc., No. 6:19-cv-00514, Text Order
`dated June 23, 2020
`Kerr Machine Co. v. Vulcan Indus. Holdings, LLC, No. 6:20-cv-
`200, Dkt. 28 (W.D. Tex. July 31, 2020)
`Kerr Machine Co. v. Vulcan Indus. Holdings, LLC, No. 6:20-cv-
`200, Dkt. 24 (W.D. Tex. June 14, 2020)
`Kerr Machine Co. v. Vulcan Indus. Holdings, LLC, No. 6:20-cv-
`200, Dkt. 12 (W.D. Tex., June 14, 2020)
`Email from J. Yi to Counsel (Aug. 3, 2020)
`FG SRC LLC v. Intel Corp., No. 1:20-cv-00834, Dkt. 48 (W.D.
`Tex. Nov. 23, 2020) (Amended Schedule)
`Continental Intermodal Group - Trucking LLC v. Sand Revolution
`LLC, No. 7:18-cv-00147, Text Order dated July 22, 2020 (W.D.
`Tex.)
`Solas OLED v. Dell Techs. Inc., No. 6:19-cv-00515, Text Order
`dated Jun. 23, 2020
`2019-07-11 - DirectStream MSFT - Huppenthal Declaration
`Declaration of William Mangione-Smith, Ph.D., In Support of FG
`SRC LLC’s Motion to Amend
`
`
`
`
`ii
`
`

`

`
`TABLE OF CONTENTS
`INTRODUCTION .................................................................................................... 1
`I.
`II. MOTION TO AMEND PILOT PROGRAM ........................................................... 2
`III. A REASONABLE NUMBER OF CLAIMS ARE AMENDED. ............................ 2
`IV. PROPOSED AMENDED CLAIMS ARE PATENTABLE. ................................... 2
`A.
`Proposed Amended Claim 20 (Replacing Claim 1). ...................................... 4
`B.
`Proposed Amended Claim 28 (Replacing Claim 9). ...................................... 8
`C.
`Proposed Amended Claim 32 (Replacing Claim 13)................................... 10
`V. WRITTEN DESCRIPTION SUPPORT FOR THE PROPOSED
`AMENDED CLAIMS ............................................................................................ 12
`VI. CONCLUSION ...................................................................................................... 12
`APPENDIX A ................................................................................................................... 18
`
`
`
`
`
`
`
`
`
`iii
`
`

`

`
`
`TABLE OF AUTHORITIES
`
`CASES:
`Aqua Products, Inc. v. Matal,
`872 F.3d 1290 (Fed. Cir. 2017) ....................................................................................... 4
`
`
`Ariad Pharms., Inc. v. Eli Lilly & Co.,
`598 F.3d 1336 (Fed. Cir. 2010) ....................................................................................... 3
`STATUTES:
`35 U.S.C. § 101 ................................................................................................................... 5
`
`35 U.S.C. § 103 ......................................................................................................... 5, 8, 11
`
`35 U.S.C. § 112 ................................................................................................................... 5
`
`35 U.S.C. § 316 ................................................................................................................... 2
`REGULATIONS:
`37 CFR § 42.121 ........................................................................................................ passim
`OTHER AUTHORITIES:
` Lectrosonics, Inc. v. Zaxcom, Inc., IPR2018-01129, Paper 15 at 4-5
` (PTAB, February 25, 2019) ..................................................................................... 2, 3, 5
`
`
`Nichia Corp. v. Emcore Corp., IPR2012-00005, Paper 27 at 3
` (PTAB June 3, 2013) ...................................................................................................... 3,
`
`
`
`iv
`
`

`

`
`
`INTRODUCTION
`I.
`Patent Owner FG SRC LLC (hereinafter “SRC” or “Patent Owner”)
`
`respectfully submits this Motion to Amend (“Motion”) to request amendment of
`
`certain claims of U.S. Patent No. 7,149,867 (the “’867 patent). Patent Owner
`
`proposes a reasonable number of substitute claims. The proposed amendments do
`
`not enlarge the scope of the claims, are responsive to at least one ground of
`
`unpatentability instituted in this proceeding, do not introduce new matter, are
`
`supported by the original application, and are patentable over the presumed prior
`
`art.1
`
`Petitioner has challenged claims 1 – 19 of the ’867 patent on the following
`
`grounds:
`
`Ground 1 – Claims 1-2, 4-8, 13-19 are unpatentable as obvious over
`
`Zhang in view of Gupta as understood by one of ordinary skill in the art.
`
`Ground 2 – Claims 3 and 9-12 are unpatentable as obvious over Zhang in
`
`view of Gupta and Chien as understood by one of ordinary skill in the art.
`
`Patent Owner requests amendments of independent claims 1, 9, and 13 to
`
`provide further limitation and clarification of its claimed invention and reflect the
`
`proper scope of these claims considering the specification.
`
`
`1 Patent Owner contends that Petitioner has not sufficiently established that either
`Zhang, Gupta, or Chien, each of which is a non-patent publication, qualifies as prior art.
`That issue will be addressed more fully in Patent Owner’s Response. For purposes of this
`Motion, the prior art status of Zhang, Gupta, and Chien will be presumed.
`1
`
`

`

`
`
`II. MOTION TO AMEND PILOT PROGRAM
`Pursuant to 84 FR 9497, Patent Owner requests that this Motion to Amend be
`
`subject to the MTA Pilot Program. This IPR was instituted on March 3, 2021, see
`
`Paper 13, and therefore it qualifies for the MTA Pilot Program effective on March
`
`15, 2019. Patent Owner requests preliminary guidance from the Board on this
`
`Motion to Amend and whether to file a revised Motion to Amend. Patent Owner
`
`reserves the right to file a revised Motion to Amend subject to the Board’s
`
`preliminary guidance.
`
`III. A REASONABLE NUMBER OF CLAIMS ARE AMENDED.
`Pursuant to 37 C.F.R § 42.121(a)(3), a motion to amend may propose a
`
`reasonable number of substitute claims for each challenged claim. Generally, it is
`
`presumed “that only one substitute claim would be needed to replace each
`
`challenged claim,” but that challenge may be rebutted by a showing of need. 37
`
`CFR § 42.121(a)(3); Lectrosonics, Inc. v. Zaxcom, Inc., IPR2018-01129, Paper 15
`
`at 4-5 (PTAB Feb. 25, 2019). Petitioner challenges claims 1 through 19. SRC
`
`proposes only one substitute claim each for challenged independent claims 1, 9, and
`
`13. Dependent claims 21-27, 29-31, and 33-38 are amended only by virtue of
`
`depending from proposed amended independent claims 1, 9, and 13.
`
`IV. PROPOSED AMENDED CLAIMS ARE PATENTABLE.
`In accordance with 35 U.S.C. § 316(d)(1)(B), Patent Owner may propose a
`
`reasonable number of substitute claims for each claim challenged by Petitioner.
`
`2
`
`

`

`
`
`These substitutions may not broaden the scope of the claims or introduce new
`
`claimed matter. 35 U.S.C. § 316(d)(3); 37 CFR § 42.121(a)(2)(ii). Proposed
`
`amendments should respond to a ground of unpatentability raised by the Petitioner
`
`in the trial. 37 CFR § 42.121(a)(2)(i). The claim listing in Appendix A clearly
`
`indicates the specific changes for each proposed amended claim and sets forth: (1)
`
`the support in the original disclosure of the patent for each added or amended claim;
`
`and (2) the support for each claim in an earlier-filed disclosure for which benefit of
`
`the filing of the earlier filed disclosure is sought.
`
`Appendix A thereby shows that the amended claims would reasonably convey
`
`to one of ordinary skill in the art that the inventors were in possession of the claimed
`
`subject matter as of the filing date of the ’867 patent. 37 CFR §§ 42.121(b)(1)-(2);
`
`see also Nichia Corp. v. Emcore Corp., IPR2012-00005, Paper 27 at 3 (PTAB Jun.
`
`3, 2013) (citing Ariad Pharms., Inc. v. Eli Lilly & Co., 598 F.3d 1336, 1351 (Fed.
`
`Cir. 2010) (en banc)). The date of the provisional patent application from which the
`
`’867 patent derives priority is irrelevant since the presumed prior art predates both.
`
`The proposed amended claims do not exceed the scope of the original claims
`
`of the ’867 Patent. Any deletions are solely for correcting syntax in the proposed
`
`amended claims, and no limitations are removed so as to impermissibly expand the
`
`scope of the claims. The added claim elements further narrow the scope of the
`
`claims.
`
` The proposed amended claims
`
`thus meet
`
`the requirements of
`
`§ 42.121(a)(2)(i) and (ii). Lectrosonics, IPR2018-01129, Paper 15 at 5-6.
`3
`
`

`

`
`
`Patent Owner’s proposals are directly responsive to Petitioner’s grounds for
`
`invalidation of the current claims. The burden thus shifts to Petitioner to show that
`
`the amended claims are unpatentable over the prior art. Aqua Products, Inc. v.
`
`Matal, 872 F.3d 1290, 1324 (Fed. Cir. 2017). Nonetheless, Patent Owner confirms
`
`that no combination of the prior art of record teaches the subject matter of the
`
`proposed amended claims. Patent Owner here discusses the closest known art to the
`
`features discussed above, which Patent Owner believes is the art raised by Intel in
`
`its petition. As explained herein, the proposed amended claims are patentable over
`
`the presumed art at issue in this proceeding, i.e., Zhang, Gupta, and Chien.
`
`Proposed Amended Claim 20 (Replacing Claim 1)
`A.
`Proposed Amended Claim 20 is set forth below. Brackets are used to indicate
`
`deletions, and underlining is used to indicate additions.
`
`Proposed Amended Claim 20. A reconfigurable processor that instantiates
`an algorithm as hardware comprising:
`a first memory having a first characteristic memory bandwidth and/or
`memory utilization; and
`a data prefetch unit coupled to the memory, wherein the data prefetch unit
`[retrieves] transfers only computational data required by the algorithm
`from a second memory of second characteristic memory bandwidth
`and/or memory utilization and places the [retrieved] computational
`data in the first memory wherein the data prefetch unit operates
`independent of and in parallel with logic blocks using the
`computational data, and wherein at least the first memory and data
`prefetch unit are configured to conform to needs of the algorithm, and
`the data prefetch unit is configured to match format and location of
`data in the second memory[.], and
`
`4
`
`

`

`
`
`wherein computations performed by the algorithm are performed by an
`FPGA.
`A motion to amend is proper where the amendment “respond[s] to a ground
`
`of unpatentability involved in the trial.” 37 CFR § 42.121(a)(2)(i). Where the
`
`proposed amendment is intended to address the grounds for institution, additional
`
`modifications may be permissible to address potential § 101 or § 112 issues.
`
`Lectrosonics, IPR2018-01129, Paper 15, 5-6. The Petition here necessarily alleges
`
`that every element of each challenged claim is disclosed by a combination of prior
`
`art references under 35 U.S.C. §103. Based thereon, the Board found in its
`
`institution decision that “Petitioner has shown sufficiently that Zhang in
`
`combination with Gupta would have rendered claims 1, 2, 4–8, 13–19 obvious.”
`
`Paper 13, at 71. Adding the proposed substantive limitations is, thus, responsive to
`
`this ground for institution.
`
`Proposed amended claim 20 is narrower than the original claim 1. The additional
`
`claim element that “computations performed by the algorithm are performed by an
`
`FPGA” is not taught by Zhang, Gupta, or Chien. “By requiring that computations that
`
`are performed by the algorithm that is instantiated by the reconfigurable processor are
`
`performed in an FPGA, the amendment excludes the use of a conventional CPU together
`
`with only limited reprogrammable peripheral components from the claim scope.”
`
`EX2027 ¶21. The new limitation that computations that are performed by the algorithm
`
`that is instantiated by the reconfigurable processor are performed in an FPGA further
`
`5
`
`

`

`
`
`“explicitly excludes the use of a conventional CPU as the computational unit of the
`
`claimed reconfigurable processor together with only limited reprogrammable peripheral
`
`components from the claim scope. This is directly responsive to the Zhang, Gupta, and
`
`Chien prior art, which relies on the use of a CPU together with only “small pockets of
`
`reprogrammable logic.” EX2027 ¶22 (citing Ex. 1003, at 13, col. 2:44-49).
`
`As shown by Dr. Mangione-Smith, Zhang discloses that “the processor running
`
`the main application is a conventional CPU, not a reconfigurable processor.”
`
`
`
`EX2027 ¶23 (citing Ex. 1003, Fig. 2). Zhang discloses the use of programmable logic
`
`(i.e., an FPGA) “only as means to deliver data for use by that conventional CPU. Zhang
`
`specifically states that it includes only ‘small blocks of programmable logic implemented
`
`into key elements of a baseline architecture’ to enable ‘the customization of architectural
`
`6
`
`

`

`
`
`mechanisms and policies to match an application.’” EX2027 ¶23 (citing Ex. 1003, at 13,
`
`col. 2:44-49). Zhang’s small blocks of programmable hardware facilitate movement of
`
`data between memory hierarchies to reduce latency at the point of data consumption. Id.
`
`Unlike the ’867 patent however, the final consumer is a conventional CPU, not a
`
`reconfigurable processor. Id. Thus, the combination of Zhang and Gupta does not teach
`
`or suggest the proposed amended limitations and does not render obvious proposed
`
`amended claim 20.
`
`Similarly, the claim element “[the] data prefetch unit retrieves” computational
`
`data from the second memory and “places the retrieved computational data in the first
`
`memory” is simplified by the amendment as the data prefetch unit transfers
`
`computational data from the second memory to the first memory. As Dr. Mangione-
`
`Smith explains, this amendment does not broaden the proper scope of the claim:
`
`Rather, this amendment emphasizes the fact that the claimed
`inventions relate to moving computational data from one memory to
`another, but only that data that is actually used for the computation.
`The claim is narrowed by explicitly not covering a situation where
`some data is read from the second memory but not placed in the first
`memory. This amendment addresses the prior art examples directed
`to sparse-matrix operations where descriptors for the sparse-matrix
`data are read, in order to retrieve the computational data but are not
`computational data themselves.
`EX2027 ¶24. Therefore, new proposed amended claim 20 is narrower than original
`
`claim 1.
`
`7
`
`

`

`
`
`Proposed Amended Claim 28 (Replacing Claim 9)
`B.
`Proposed Amended Claim 28 is set forth below. Brackets are used to indicate
`
`deletions, and underlining is used to indicate additions.
`
`Proposed Amended Claim 28. A reconfigurable hardware system,
`comprising:
`a common memory; and
`one or more reconfigurable processors that can instantiate an algorithm as
`hardware coupled to the common memory, wherein at least one of the
`reconfigurable processors includes a data prefetch unit to read data,
`including computational data, and write only computational data
`required for computations by the algorithm between the data prefetch
`unit and the common memory wherein the data prefetch unit operates
`independent of and in parallel with logic blocks using the
`computational data, and wherein the data prefetch unit is configured to
`conform to needs of the algorithm and match format and location of
`data in the common memory[.], and
`wherein the data prefetch unit is configured to conform to the needs of the
`algorithm, and
`wherein computations performed by the algorithm are performed by an
`FPGA.
`As detailed previously, an amendment must “respond to a ground of
`
`unpatentability involved in the trial.” 37 CFR § 42.121(a)(2)(i). The Petition here
`
`necessarily alleges that every element of each challenged claim is disclosed by a
`
`combination of prior art references under 35 U.S.C. §103. Based thereon, the Board
`
`found in its institution decision that “Petitioner has adequately shown that Zhang,
`
`Gupta, and Chien teach the limitations in claim 9 for purposes of institution.” Paper
`
`13, at 73. Adding the proposed substantive limitations is thus responsive to this
`
`ground for institution.
`
`8
`
`

`

`
`
`Proposed amended claim 28 is narrower than the original claim 9. The additional
`
`claim elements add additional limitations that narrow the claim. First, the limitation that
`
`“computations performed by the algorithm are performed by an FPGA,” narrows the
`
`claim scope for the reasons explained above regarding proposed amended claim 20.
`
`“The amendment explicitly excludes the use of a conventional CPU as the computational
`
`unit of the claimed reconfigurable processor, which is directly responsive to the Zhang,
`
`Gupta, and Chien prior art, which relies on the use of a CPU together with only “small
`
`pockets of reprogrammable logic.” EX2027 ¶27 (citing Ex. 1003, at 13, col. 2:44-49;
`
`and Fig. 2). Second, the addition of the claim element “wherein the data prefetch unit is
`
`configured to conform to the needs of the algorithm” further limits claim scope by
`
`requiring that “not just the claimed reconfigurable processor instantiates an algorithm as
`
`hardware, but that the claimed data prefetch unit must be configured to conform to the
`
`needs of the algorithm as well.” EX2027 ¶27. “This amendment explicitly excludes the
`
`use of only small blocks of peripheral reprogrammable hardware as disclosed in Zhang,
`
`Gupta, and Chien.” Id. (citing Ex. 1003, at 13, col. 2:44-49; see also id. at Fig. 2).
`
`Thus, the combination of Zhang, Gupta, and Chien does not teach or suggest the
`
`proposed amended limitations and does not render obvious proposed amended claim 28.
`
`Similarly, the claim element “data prefetch unit to … read and write only data
`
`required for computations by the algorithm” is simplified by the amendment, which
`
`provides that the data prefetch unit reads data, including computational data, and writes
`
`9
`
`

`

`
`
`only data required for computations by the algorithm. As Dr. Mangione-Smith explains,
`
`this amendment does not broaden the proper scope of the claim:
`
`Rather, this amendment emphasizes the fact that the claimed
`inventions relate to moving computational data from one memory to
`another, but only that data that is actually used for the computation.
`The claim is narrowed by explicitly not covering a situation where
`some data is read from the second memory but not placed in the first
`memory. This amendment addresses the prior art examples directed
`to sparse-matrix operations where descriptors for the sparse-matrix
`data are read, in order to retrieve the computational data but are not
`computational data themselves.
`EX2027 ¶28. Therefore, new proposed amended claim 28 is narrower than original
`
`claim 9.
`
`Proposed Amended Claim 32 (Replacing Claim 13)
`C.
`Proposed Amended Claim 32 is set forth below. Brackets are used to indicate
`
`deletions, and underlining is used to indicate additions.
`
`Proposed Amended Claim 32. A method of transferring data comprising:
`transferring data between a memory and a data prefetch unit in a
`reconfigurable processor, and
`transferring the data between a computational unit and the data access unit,
`wherein the computational unit and the data access unit, and the data
`prefetch unit are configured to conform to needs of an algorithm
`implemented on the computational unit and transfer only data
`necessary for computations by the computational unit to the data
`access units, and wherein the prefetch unit operates independent of and
`in parallel with the computational unit[.], and
`wherein the computational unit is implemented in an FPGA.
`As detailed previously, an amendment must “respond to a ground of
`
`unpatentability involved in the trial.” 37 CFR § 42.121(a)(2)(i). The Petition here
`
`10
`
`

`

`
`
`necessarily alleges that every element of each challenged claim is disclosed by a
`
`combination of prior art references under 35 U.S.C. §103. Based thereon, the Board
`
`found in its institution decision that “Petitioner has shown sufficiently that Zhang in
`
`combination with Gupta would have rendered claims 1, 2, 4–8, 13–19 obvious.”
`
`Paper 13, at 71. Adding the proposed substantive limitations is thus responsive to
`
`this ground for institution.
`
`Proposed amended claim 32 is narrower than the original claim 13. The additional
`
`claim elements add additional limitations that narrow the claim. The limitation that “the
`
`computational unit is implemented in an FPGA” narrows the claim scope for the reasons
`
`explained above regarding proposed amended claim 20. “The amendment explicitly
`
`excludes the use of a conventional CPU as the computational unit of the claimed
`
`reconfigurable processor, which is directly responsive to the Zhang, Gupta, and Chien
`
`prior art, which relies on the use of a CPU together with only ‘small pockets of
`
`reprogrammable logic.’” EX2027 ¶31 (citing Ex. 1003, at 13, col. 2:44-49; and Fig. 2).
`
`Thus, the combination of Zhang, Gupta, and Chien does not teach or suggest the
`
`proposed amended limitations and does not render obvious proposed amended claim 32.
`
`Similarly, the claim element “the data access unit, and the data prefetch unit …
`
`transfer only data necessary for computations by the computational unit” is clarified to
`
`indicate that the data is transferred to the data access units. This amendment does not
`
`broaden the proper scope of the claim. To the contrary, specifying the target of the
`
`11
`
`

`

`
`
`transfer narrows claim scope because the data must be transferred there specifically,
`
`instead of just “transferred” to any component. As Dr. Mangione-Smith explains:
`
`This amendment emphasizes the fact that the claimed inventions
`relate to moving computational data from one memory to another, but
`only that data that is actually used for the computation. The claim is
`narrowed by explicitly not covering a situation where some data is
`read from the second memory but not placed in the first memory. This
`amendment addresses the prior art examples directed to sparse-matrix
`operations where descriptors for the sparse-matrix data are read in
`order to retrieve the computational data but are not computational data
`themselves.
`EX2027 ¶32. Therefore, in the aggregate, new proposed amended claim 32 is narrower
`
`than original claim 13.
`
`V. WRITTEN DESCRIPTION SUPPORT FOR THE PROPOSED
`AMENDED CLAIMS
`The below tables identify the written description support for the proposed
`
`amended claims, including the original claim elements and the proposed amendments.
`
`A. AMENDED CLAIM 20 REPLACING ORIGINAL CLAIM 1
`Amended Claim 20
`Support in ’867 Pat.
`20. A reconfigurable processor that
`Passim, including Abstract; 3:64-
`instantiates an algorithm as hardware
`4:26; 5:19-25; 5:26-29; 5:30-33;
`comprising:
`5:34-37; 5:59-6:4; 6:5-31, 6:47-58;
`6:58-7:4; 7:49-62; Figs. 1-7 and
`related descriptions.
`
`4:4-10; 6:5-31; 7:5-22; 7:34-48;
`7:49-62; 8:3-11; 8:12-21; 8:22-41;
`8:42-51; 62-9:13; Figs. 3-7 and
`related descriptions.
`Abstract; 4:4-10; 4:19-26; 5:51-54;
`7:23-32; 7:49-62; 7:63-8:41; 8:42-
`51; 8:62-9:13; Figs. 3, 8-14 and
`related descriptions.
`
`a data prefetch unit coupled to the memory,
`wherein the data prefetch unit [retrieves]
`transfers only computational data required
`by the algorithm from a second memory of
`12
`
`a first memory having a first characteristic
`memory bandwidth and/or memory
`utilization; and
`
`

`

`
`
`second characteristic memory bandwidth
`and/or memory utilization and places the
`[retrieved] computational data in the first
`memory wherein the data prefetch unit
`operates independent of and in parallel
`with logic blocks using the computational
`data, and wherein at least the first memory
`and data prefetch unit are configured to
`conform to needs of the algorithm, and the
`data prefetch unit is configured to match
`format and location of data in the second
`memory[.], and
`
`wherein computations performed by the
`algorithm are performed by an FPGA.
`
`Abstract; 3:64-4:3; 5:19-29; 5:34-
`37; 5:59-6:4; 6:5-31, 6:47-58; Figs.
`1-7 and related descriptions.
`B. AMENDED CLAIM 28 REPLACING ORIGINAL CLAIM 9
`Amended Claim 28
`Support in ’867 Pat.
`28. A reconfigurable hardware system,
`Passim, including Abstract; 3:64-
`comprising:
`4:26; 5:19-25; 5:26-29; 5:30-33;
`5:34-37; 5:59-6:4; 6:5-31, 6:47-58;
`6:58-7:4; 7:49-62; Figs. 1-7 and
`related descriptions.
`Abstract; 4:4-10; 4:11-18; 6:5-31;
`7:5-22; 7:34-48; 7:49-62; 8:3-11;
`8:12-21; 8:22-41; 8:42-51; 62-9:13;
`Figs. 3-7 and related descriptions.
`
`a common memory; and
`
`13
`
`

`

`
`
`one or more reconfigurable processors that
`can instantiate an algorithm as hardware
`coupled to the common memory, wherein
`at least one of the reconfigurable
`processors includes a data prefetch unit to
`read data, including computational data,
`and write only computational data required
`for computations by the algorithm between
`the data prefetch unit and the common
`memory wherein the data prefetch unit
`operates independent of and in parallel
`with logic blocks using the computational
`data, and wherein the data prefetch unit is
`configured to conform to needs of the
`algorithm and match format and location of
`data in the common memory[.], and
`
`Passim, including Abstract; 3:64-
`4:26; 5:19-25; 5:26-29; 5:30-33;
`5:34-37; 5:51-54; 5:59-6:4; 6:5-31,
`6:47-58; 6:58-7:4; 7:23-32; 7:49-
`62; 7:63-8:41; Figs. 1-7 and related
`descriptions (reconfigurable
`processor); Figs. 3, 8-14 (prefetch
`and memory configurations).
`
`wherein computations performed by the
`algorithm are performed by an FPGA.
`
`wherein the data prefetch unit is configured
`to conform to the needs of the algorithm,
`and
`
`Abstract; 4:4-10; 4:19-26; 5:51-54;
`7:23-32; 7:49-62; 7:63-8:41; 8:42-
`51; 8:62-9:13; Figs. 3, 8-14 and
`related descriptions.
`Abstract; 3:64-4:3; 5:19-29; 5:34-
`37; 5:59-6:4; 6:5-31, 6:47-58; Figs.
`1-7 and related descriptions.
`C. AMENDED CLAIM 32 REPLACING ORIGINAL CLAIM 13
`Amended Claim 32
`Support in ’867 Pat.
`32. A method of transferring data
`Passim, including abstract; 4:19-
`comprising:
`26; 5:51-54; 7:23-32; Figs. 8-14.
`
`transferring data between a memory and a
`data prefetch unit in a reconfigurable
`processor, and
`
`transferring the data between a
`computational unit and the data access unit,
`wherein the computational unit and the
`data access unit, and the data prefetch unit
`14
`
`Abstract; 3:64-4:26; 5:19-25; 5:26-
`29; 5:30-33; 5:34-37; 5:51-54;
`5:59-6:4; 6:5-31, 6:47-58; 6:58-7:4;
`7:23-32; 7:49-62; 7:63-8:41; 8:42-
`51; 8:62-9:13; Figs. 3, 8-14
`(prefetch and memory
`configurations).
`Abstract; 3:64-4:26; 5:19-25; 5:26-
`29; 5:30-33; 5:34-37; 5:51-54;
`5:59-6:4; 6:5-31, 6:47-58; 6:58-7:4;
`7:23-32; 7:49-62; 7:63-8:41; 8:42-
`
`

`

`
`
`are configured to conform to needs of an
`algorithm implemented on the
`computational unit and transfer only data
`necessary for computations by the
`computational unit to the data access units,
`and wherein the prefetch unit operates
`independent of and in parallel with the
`computational unit[.], and
`
`51; 8:62-9:13; Figs. 3, 8-14
`(prefetch and memory
`configurations).
`
`wherein the computational unit is
`implemented in an FPGA.
`
`Abstract; 3:64-4:3; 5:19-29; 5:34-
`37; 5:59-6:4; 6:5-31, 6:47-58; Figs.
`1-7 and related descriptions.
`
`VI. CONCLUSION
`For the reasons set forth herein, Patent Owner asserts that the proposed
`
`amended claims meet all statutory requirements and respectfully requests that the
`
`Board allow proposed amended claims 20, 28, and 32, and dependent amended
`
`claims 21-27, 29-31, and 33-38.
`
`15
`
`

`

`
`
`Date: May 26, 2021
`
`
`
`
`
`
`
`Respectfully submitted,
`
`
`
`
`
`
`
`
`/s/ Jay P. Kesan
`
`DiMuroGinsberg, PC-
`DGKeyIP Group
`Jay P. Kesan
`Reg. No. 37,488
`Cecil E. Key (admission pro hac vice
`pending)
`1750 Tysons Blvd., Suite 1500
`Tysons Corner, VA 22102
`Phone: 703-289-5118
`jkesan@dimuro.com
`ckey@dimuro.com
`
`Ari B. Rafilson
`arafilson@shorechan.com
`SHORE CHAN LLP
`901 Main Street, Suite 3300
`Dallas, Texas 75202
`Telephone: 214-593-9110
`Facsimile: 214-593-9111
`
`
`
`
`
`
`
`16
`
`

`

`
`
`CERTIFICATE OF SERVICE
`
`
`Pursuant to 37 C.F.R. §§ 42.6(e)(4) and 42.25(b), the undersigned certifies that on
`May 26, 2021, a complete copy of Patent Owner FG SRC LLC’s Motion to Amend was
`filed electronically through the Patent Trial and Appeal Board’s PTABE2E System and
`provided, via electronic service, to the Petitioner by serving the correspondence address
`of record as follows:
`Brian C. Nash, brian.nash@pillsburylaw.com
`PILLSBURY WINTHROP SHAW PITTMAN LLP
`401 Congress Avenue, Ste. 1700
`Austin, Texas 78701
`
`Evan Finkel, evan.finkel@pillsburylaw.com
`PILLSBURY WINTHROP SHAW PITTMAN LLP
`725 South Figueroa Street, Ste. 2800
`Los Angeles, CA 90017-5406
`
`Matthew W. Hindman, matthew.hindman@pillsburylaw.com
`PILLSBURY WINTHROP SHAW PITTMAN LLP
`2550 Hanover Street
`Palo Alto, CA 94304
`
`
`
`
`/s/ Jay P. Kesan
`Jay P. Kesan
`
`
`17
`
`

`

`
`
`APPENDIX A
`Patent Owner’s proposed amended claims are set forth below, including (1) the
`
`support in the original disclosure of U.S. Patent No. 7,149,867 (“’867 patent”) for each
`
`amended claim; and (2) the support for each claim in provisional application No.
`
`60/479,339, filed on Jun. 18, 2003 (“’339 application”). Use of brackets indicates deleted
`
`text (if any) and underlining indicates inserted text. For ease of reference, the below table
`
`indicates the correspondence between original and amended claims:
`
`Original Claim Amended Claim
`1
`20 (Amended)
`2
`21
`3
`22
`4
`23
`5
`24
`6
`25
`7
`26
`8
`27
`9
`28 (Amended)
`10
`29
`11
`30
`12
`31
`13
`32 (Amended)
`14
`33
`15
`34
`16
`35
`17
`36
`18
`37
`19
`38
`
`The indicated claims 20, 28, and 32 are amended; the claims 21-27, 29-31, and 33-38 are
`
`amended only by virtue of depending from an amended claim.
`
`
`
`18
`
`

`

`
`
`1.
`
`AMENDED CLAIM 20 REPLACING ORIGINAL CLAIM 1
`Amended Claim 20
`Support in ’867 Pat.
`20. A reconfigurable processor that
`Passim, including Abstract; 3:64-
`instantiates an algorithm as hardware
`4:26; 5:19-25; 5:26-29; 5:30-33;
`comprising:
`5:34-37; 5:59-6:4; 6:5-31, 6:47-58;
`6:58-7:4; 7:49-62; Figs. 1-7 and
`related descriptions.
`
`4:4-10; 6:5-31; 7