UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INTEL CORPORATION,
`Petitioner,
`V.
`FG SRC LLC,
`Patent Owner.
`
`IPR2020-01449
`Patent No. 7,149,867
`
`DECLARATION OF WILLIAM MANGIONE-SMITH, PH.D., IN
`SUPPORT OF FG SRC LLC'S MOTION TO AMEND
`
`I, Dr. William Mangione-Smith, under the penalty of perjury under the laws
`
`of the United States, declare that the following is true and correct based on the best
`
`of my ability.
`
`Date: May 26, 2021
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`Signed:
`
`WILLIAM MANGIONE-SMITH, PH.D.
`
`Patent Owner FG SRC LLC
`IPR2020-01449, Ex. 2027, p. 1
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`1.
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`I have been retained by DiMuro Ginsberg, P.C., as an independent
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`technical expert in the Inter Partes Review dispute between FG SRC, and Intel
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`Corporation, No. IPR2020-01449 which involves U.S. Patent No. 7,149,867 (“’867
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`Patent”).
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`2.
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`I have been paid for my work as a technical expert at my customary
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`hourly rate. My compensation does not in any way depend on the outcome of this
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`matter, and I have no personal interest in the outcome of this matter.
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`I.
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`Qualifications
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`3. My technical background and experience cover most aspects of
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`computer system design, including low level circuitry, computer architecture,
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`computer networking, digital rights management, cryptography, digital media,
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`communications, information technology, application software, client-server
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`application, Web technology, and system software (e.g., operating systems and
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`compilers). I am a member of the Institute of Electrical and Electronics Engineers
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`and the Association for Computing Machinery, which are the two most significant
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`professional organizations in my profession. I have been employed as a design
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`engineer, research engineer, professor, and technical expert. Over my professional
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`career, I have been an active inventor with 121 issued U.S. patents, 200 published
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`and pending U.S. patent applications and many unpublished U.S. patent
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`applications.
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`Patent Owner FG SRC LLC
`IPR2020-01449, Ex. 2027, p. 2
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`4.
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`From 1984 until 1991, I attended the University of Michigan in Ann
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`Arbor, Michigan, where I was awarded the degrees of Bachelor of Science and
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`Engineering, Master of Science and Engineering, and Doctor of Philosophy. My
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`doctoral research focused on high performance computing systems including
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`computer architecture, applications and operating system software, and compiler
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`technology. One of my responsibilities during my graduate studies included
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`teaching senior undergraduate students who were about to enter the profession.
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`5.
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`After graduating from the University of Michigan, I was employed by
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`Motorola in Schaumburg, Illinois. While at Motorola, I was part of a team
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`designing and manufacturing the first commercial battery-powered product capable
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`of delivering Internet email over a wireless (i.e., radio frequency) link and one of
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`the first personal digital assistants. I also served as the lead architect on the
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`second-generation of this device with control over the entire system design
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`including the memory subsystem architecture, embedded processor, ASIC, power
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`system, and analog circuitry. Part of my responsibilities at Motorola involved the
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`specification, design, and testing of system control Application-Specific Integrated
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`Circuits (“ASICs”). I conducted the initial research and advanced design that
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`resulted in the Motorola M*Core embedded microprocessor. M*Core was
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`designed to provide the high performance of desktop microprocessors with the low
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`power of contemporaneous embedded processors. The M*Core received
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`widespread use in many communications products including various cellular
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`handsets, advanced pagers, and embedded infrastructure.
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`6.
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`From 1995 until 2005, I was employed by the University of California
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`at Los Angeles (“UCLA”) as a professor of Electrical Engineering. I was the
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`director of the laboratory for Compiler and Architecture Research in Embedded
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`Systems (“CARES”) and served as the field chair for Embedded Computing
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`Systems. The CARES research team focused on research, engineering, and design
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`challenges in the context of battery-powered and multi-media mobile computing
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`devices. One of the key developments of my lab was the Mediabench software
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`tool, which is widely used to design and evaluate multi-media embedded devices.
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`Key elements of Mediabench include software that is essential for modern digital
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`wireless communications. My primary responsibility, in addition to classroom
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`teaching, involved directing the research and training of graduate students. I was a
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`tenured member of the faculty and had responsibilities for teaching as well as
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`scholarly research. My colleagues at UCLA were some of the leading scientists
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`and engineers in the world with a long list of innovations from computer network
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`security devices to the nicotine patch. The graduate student researchers in my
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`laboratory came from a diverse set of backgrounds, all with undergraduate degrees
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`in computer engineering, electrical engineering, or computer science, many with
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`multiple years of experience working as professional engineers in areas such as
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`Patent Owner FG SRC LLC
`IPR2020-01449, Ex. 2027, p. 4
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`digital rights management, cryptography, and some combination of digital media,
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`communications, information technology, software development, computer system
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`design, or computer science and ASIC circuit design.
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`7.
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`From 2005 until 2009, I was employed at Intellectual Ventures in
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`Bellevue, Washington. My responsibilities at Intellectual Ventures included
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`business development, technology assessment, market forecasting, university
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`outreach, collaborative inventing, intellectual property licensing support, and
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`intellectual property asset pricing. My colleagues and co-inventors at Intellectual
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`Ventures included the former lead intellectual property strategist at Intel, Intel’s
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`former lead IP counsel, Microsoft’s former chief software architect, the founder of
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`Microsoft research, the designer of the Mach operating system, the architect of the
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`U.S. Defense Department’s Strategic Defense Initiative, the founder of Thinking
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`Machines (a seminal parallel processing computer system), and Bill Gates. I had
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`responsibility for hiring and managing over 15 staff members including multiple
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`Ph.Ds. with degrees in electrical engineering or computer science, and decades of
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`experience in product design and engineering.
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`8.
`
`A summary of some of my qualifications for forming the opinions in
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`this declaration are as follows: I have more than 30 years of experience as a
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`computer architect, computer system designer, communication system designer,
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`educator, and as an executive in the PC and electronics business. I am also a
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`Patent Owner FG SRC LLC
`IPR2020-01449, Ex. 2027, p. 5
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`
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`member of several professional associations, such as the ACM and IEEE, and have
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`been intimately involved in professional research through the International
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`Symposium on Microarchitecture (Program Chair for 26th and General Chair for
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`36th), IEEE Transactions on Computers (Associate Editor), ACM Transactions on
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`Embedded Computing Systems (Associate Editor), and IEEE Computer (Associate
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`Editor). I also have been on the program committees for ISCA, MICRO, ISLPED,
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`Network Processors Workshop, FPL, Complexity-Effective Design, RAW,
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`Workshop on Mediaprocessors, and DSP, FPT, and INTERACT.
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`9.
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`I also have extensive experience and expertise with FPGA technology
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`in general and reconfigurable computing in particular. My research was funded by
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`the US Defense Advanced Research Projects Agency (DARPA), published in
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`leading journals in my field, and appeared on the cover of Scientific American
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`(June 1997). Specific research areas included cryptography, network security,
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`fault-tolerance, and intellectual property protection.
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`10. For further details regarding my employment and academic history,
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`please refer to my curriculum vitae provided in Appendix A.
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`II. Bases Of Opinions
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`11. The basis and reasoning of my opinions include my education,
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`training, and experience as an engineer, including my 35 years of experience
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`Patent Owner FG SRC LLC
`IPR2020-01449, Ex. 2027, p. 6
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`
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`designing microprocessors. In the course of conducting my analysis and forming
`
`my opinions, I have considered the materials listed below:
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`a. U.S. Patent No. 7,149,867 to Daniel Poznanovic, et al., filed June16,
`2004, and issued on December12, 2006 (“’867 patent”) and its file
`history;
`
`b. X. Zhang et al., Architectural Adaptation of Application-Specific
`Locality Optimizations, IEEE (1997) (“Zhang”);
`
`c. R. Gupta, Architectural Adaptation in AMRM Machines, IEEE (2000)
`(“Gupta”);
`
`d. A. Chien and R. Gupta, MORPH: A System Architecture for Robust
`Higher Performance Using Customization,” IEEE (1996) (“Chien”);
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`e. Chien et al., Safe and Protected Execution for the Morph/AMRM
`Reconfigurable Processor, IEEE (1999);
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`f. Declaration of Stanley Shanfield, Ph.D.;
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`g. Declaration of Rajesh K. Gupta;
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`h. Declaration of J. Munford;
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`i. Provisional Application No. 60/479,339;
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`j. U.S. Patent 8,713,518;
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`k. Book: John L. Hennessy and David A. Patterson, “Computer
`Architecture: A Quantitative Approach” (The Morgan Kaufmann Series
`in Computer Architecture and Design); and
`
`l. Book: David Culler, “Parallel Computer Architecture: A
`Hardware/Software Approach” (The Morgan Kaufmann Series in
`Computer Architecture and Design);
`
`m. Intel’s IPR petition in this matter and its exhibits;
`
`n. Declaration of Ryan Kastner, Ph.D. In Support Of FG SRC LLC’s
`Opening Claim Construction Brief in FG SRC LLC v. Intel Corp., No.
`6:20-cv-00315-ADA (W.D. Texas), filed April 24, 2020;
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`
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`7
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`Patent Owner FG SRC LLC
`IPR2020-01449, Ex. 2027, p. 7
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`
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`o. FG’SRC’s Preliminary Response in this proceeding (Paper 9);
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`p. Declaration of Vojin G. Oklobdzija, Ph.D., In Support of FG SRC
`LLC’s Preliminary Response (EX2001);
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`q. Institution Decision in this proceeding (Paper 13); and
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`r. any other materials referenced herein.
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`12. My opinions in this declaration are based on the understanding of a
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`person of ordinary skill in the art at the time of the invention of the claims in the
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`’867 Patent.
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`13.
`
`In assessing the level of skill of a person of ordinary skill in the art I
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`have considered the type of problems encountered in the field, the prior solutions
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`to those problems found in the prior art references, the pace with which
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`innovations are made, the sophistication of the technology, the level of education
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`of active workers in the field, and my own experience working with those of skill
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`in the art at the time of the invention.
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`14. A person of ordinary skill in the art (“POSITA”) at the time of the
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`filing of the ’867 patent would typically have at least an MS Degree in Computer
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`Engineering, Computer Science, or Electrical Engineering, or equivalent work
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`experience, along with at least three years of experience related specifically to
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`computer architecture, hardware design, and reconfigurable processors. In
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`addition, a POSITA would be familiar with hardware description languages and
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`design tools and methodologies used to program a reconfigurable processor.
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`8
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`Patent Owner FG SRC LLC
`IPR2020-01449, Ex. 2027, p. 8
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`15.
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`I am very familiar with this level of skill. In the course of my 35
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`years of processor design and research, I have supervised and worked with
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`engineers in this field having the level of skill identified above.
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`16.
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`I understand that the words of a claim are generally given their
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`ordinary and customary meaning, that is, the meaning that the term would have to
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`a person of ordinary skill in the art in question at the time of the invention
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`17.
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`I understand that a claim term that does not use the word “means” is
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`presumed not to be a means-plus-function term. I understand that a term that does
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`not use the word “means” would be construed as a means-plus-function term if it
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`does not describe structure to a POSITA. Conversely, I understand that if a term
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`describes structure to a POSITA, it is not a means-plus-function term.
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`III. ANALYSIS OF PROPOSED CLAIM AMENDMENTS
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`18.
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`I have been asked to provide my expert opinion regarding proposed
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`amended claims 20 (replacing claim 1), 28 (replacing claim 9), and 32 (replacing
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`claim 13), and specifically, whether the proposed amendments to the proposed
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`amended claims are (1) responsive to a ground for unpatentability at issue in this
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`IPR per the institution decision; (2) enlarging the claim scope; or (3) introduce new
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`subject matter; and (4) whether the proposed amended claims, as a whole, are (a)
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`supported by the patent specification; and (b) supported by the provisional
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`application to which they claim priority.
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`9
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`Patent Owner FG SRC LLC
`IPR2020-01449, Ex. 2027, p. 9
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`A.
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`Proposed Amended Claim 20 (Replacing Claim 1)
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`19. Proposed Amended Claim 20 appears below. I have been provided
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`these amended claims along with editing that shows brackets to indicate deletions
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`and underlining to indicate additions.
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`Proposed Amended Claim 20. A reconfigurable processor that
`instantiates an algorithm as hardware comprising:
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`a first memory having a first characteristic memory bandwidth and/or
`memory utilization; and
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`a data prefetch unit coupled to the memory, wherein the data prefetch
`unit [retrieves] transfers only computational data required by the
`algorithm from a second memory of second characteristic
`memory bandwidth and/or memory utilization and places the
`[retrieved] computational data in the first memory wherein the
`data prefetch unit operates independent of and in parallel with
`logic blocks using the computational data, and wherein at least
`the first memory and data prefetch unit are configured to
`conform to needs of the algorithm, and the data prefetch unit is
`configured to match format and location of data in the second
`memory[.], and
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`wherein computations performed by the algorithm are performed by an
`FPGA.
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`20.
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`I understand that the Board in its institution decision found that
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`“Petitioner has shown sufficiently that Zhang in combination with Gupta would
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`have rendered claims 1, 2, 4–8, 13–19 obvious.” Paper 13, at 71. Based on my
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`understanding of the requirements of patentability and obviousness, the addition of
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`substantive limitations supported by the patent specification that are not obvious is
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`10
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`Patent Owner FG SRC LLC
`IPR2020-01449, Ex. 2027, p. 10
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`one approach for responding to a ground for institution. The proposed
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`amendments shown here directly address the grounds for institution.
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`21.
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`In my expert opinion, proposed amended claim 20 does not broaden
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`claim scope. To the contrary, as a result of the addition of the limiting element
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`requiring that “computations performed by the algorithm are performed by an
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`FPGA,” the claim scope is narrowed. By requiring that computations that are
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`performed by the algorithm that is instantiated by the reconfigurable processor are
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`performed in an FPGA, the amendment excludes from the claim scope the use of a
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`conventional CPU together with only limited reprogrammable peripheral
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`components. Therefore, this is a scope limiting amendment.
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`22. Further, as a result of the requirement that computations that are
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`performed by the algorithm that is instantiated by the reconfigurable processor are
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`performed in an FPGA, the amendment explicitly excludes from the claim scope
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`the use of a conventional CPU as the computational unit of the claimed
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`reconfigurable processor together with only limited reprogrammable peripheral
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`components. This narrowing of the claim is directly responsive to the Zhang,
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`Gupta, and Chien prior art, which relies on the use of a CPU together with only
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`“small pockets of reprogrammable logic.” Ex. 1003, at 13, col. 2:44-49.
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`23.
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`In Zhang, the processor running the main application is a conventional
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`CPU, not a reconfigurable processor. This is shown in Fig. 2 of Zhang.
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`11
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`Patent Owner FG SRC LLC
`IPR2020-01449, Ex. 2027, p. 11
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`
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`Ex. 1003, Fig. 2. Zhang uses programmable logic (FPGA) only as means to
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`deliver data for use by that conventional CPU. Zhang specifically states that it
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`includes only “small blocks of programmable logic implemented into key elements
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`of a baseline architecture” to enable “the customization of architectural
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`mechanisms and policies to match an application.” Ex. 1003, at 13, col. 2:44-49.
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`Zhang’s small blocks of programmable hardware facilitate movement of data
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`between memory hierarchies to reduce latency at the point of data consumption.
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`Id. Unlike the ’867 patent however, the final consumer is a conventional CPU, not
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`a reconfigurable processor.
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`24. Similarly, the claim element “data prefetch unit retrieves”
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`computational data from the second memory and “places the retrieved
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`
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`12
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`Patent Owner FG SRC LLC
`IPR2020-01449, Ex. 2027, p. 12
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`computational data in the first memory” is simplified by the amendment as the data
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`prefetch unit transfers computational data from the second memory to the first
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`memory. This amendment does not broaden the proper scope of the claim. Rather,
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`this amendment emphasizes the fact that the claimed inventions relate to moving
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`computational data from one memory to another, but only that data that is actually
`
`used for the computation. The claim is narrowed by explicitly not covering a
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`situation where some data is read from the second memory but not placed in the
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`first memory. This amendment addresses the prior art examples of Zhang directed
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`to sparse-matrix operations where descriptors for the sparse-matrix data are read,
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`in order to retrieve the computational data but are not computational data
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`themselves.
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`B.
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`Proposed Amended Claim 28 (Replacing Claim 9)
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`25. Proposed Amended Claim 28 is set forth below. Brackets are used to
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`indicate deletions, and underlining is used to indicate additions.
`
`Proposed Amended Claim 28. A reconfigurable hardware system,
`comprising:
`
`a common memory; and
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`one or more reconfigurable processors that can instantiate an algorithm
`as hardware coupled to the common memory, wherein at least
`one of the reconfigurable processors includes a data prefetch unit
`to read data, including computational data, and write only
`computational data required for computations by the algorithm
`between the data prefetch unit and the common memory wherein
`the data prefetch unit operates independent of and in parallel
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`
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`13
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`Patent Owner FG SRC LLC
`IPR2020-01449, Ex. 2027, p. 13
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`
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`with logic blocks using the computational data, and wherein the
`data prefetch unit is configured to conform to needs of the
`algorithm and match format and location of data in the common
`memory[.], and
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`wherein the data prefetch unit is configured to conform to the needs of
`the algorithm, and
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`wherein computations performed by the algorithm are performed by an
`FPGA.
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`26.
`
`I understand that the Board in its institution decision found that
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`“Petitioner has adequately shown that Zhang, Gupta, and Chien teach the
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`limitations in claim 9 for purposes of institution.” Paper 13, at 73. Based on my
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`understanding of the requirements of patentability and obviousness, the addition of
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`substantive limitations supported by the patent specification that are not obvious is
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`responsive to a ground for institution. The proposed amendments shown here
`
`directly address the grounds for institution.
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`27.
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`In my expert opinion, proposed amended claim 28 does not broaden
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`claim scope. To the contrary, the addition of the two limiting elements narrows
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`claim scope. First, by requiring that “computations performed by the algorithm
`
`are performed by an FPGA,” the claim scope is narrowed for the reasons explained
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`above in reference to proposed amended claim 20. The amendment explicitly
`
`excludes the use of a conventional CPU as the computational unit of the claimed
`
`reconfigurable processor, which is directly responsive to the Zhang, Gupta, and
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`Chien prior art, which relies on the use of a CPU together with only “small pockets
`
`
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`14
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`Patent Owner FG SRC LLC
`IPR2020-01449, Ex. 2027, p. 14
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`
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`of reprogrammable logic.” Ex. 1003, at 13, col. 2:44-49; see also id. at Fig. 2.
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`Second, the addition of the claim element “wherein the data prefetch unit is
`
`configured to conform to the needs of the algorithm” limits claim scope by
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`requiring that not just the claimed reconfigurable processor instantiates an
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`algorithm as hardware, but that the claimed data prefetch unit must be configured
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`to conform to the needs of the algorithm as well. This amendment explicitly
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`excludes the use of only small blocks of peripheral reprogrammable hardware as
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`disclosed in Zhang, Gupta, and Chien. Ex. 1003, at 13, col. 2:44-49; see also id. at
`
`Fig. 2.
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`28. Similarly, the claim element “[the] data prefetch unit … read and
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`write only data required for computations by the algorithm” is simplified by the
`
`amendment as the data prefetch unit reads data, including computational data, and
`
`writes only data required for computations by the algorithm. This amendment does
`
`not broaden the proper scope of the claim. Rather, this amendment emphasizes the
`
`fact that the claimed inventions relate to moving computational data from one
`
`memory to another, but only that data that is actually used for the computation.
`
`The claim is narrowed by explicitly not covering a situation where some data is
`
`read from the second memory but not placed in the first memory. This amendment
`
`addresses the prior art examples directed to sparse-matrix operations in Zhang
`
`
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`15
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`Patent Owner FG SRC LLC
`IPR2020-01449, Ex. 2027, p. 15
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`
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`where descriptors for the sparse-matrix data are read, in order to retrieve the
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`computational data but are not computational data themselves.
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`C.
`
`Proposed Amended Claim 32 (Replacing Claim 13)
`
`29. Proposed Amended Claim 32 is set forth below. Brackets are used to
`
`indicate deletions, and underlining is used to indicate additions.
`
`Proposed Amended Claim 32. A method of transferring data
`comprising:
`
`transferring data between a memory and a data prefetch unit in a
`reconfigurable processor, and
`
`transferring the data between a computational unit and the data access
`unit, wherein the computational unit and the data access unit, and
`the data prefetch unit are configured to conform to needs of an
`algorithm implemented on the computational unit and transfer
`only data necessary for computations by the computational unit
`to the data access units, and wherein the prefetch unit operates
`independent of and in parallel with the computational unit[.], and
`
`wherein the computational unit is implemented in an FPGA.
`
`30.
`
`I understand that the Board in its institution decision found that
`
`“Petitioner has shown sufficiently that Zhang in combination with Gupta would
`
`have rendered claims 1, 2, 4–8, 13–19 obvious.” Based on my understanding of
`
`the requirements of patentability and obviousness, by adding substantive
`
`limitations supported by the patent specification that are not obvious a patent
`
`owner is responding to a ground for institution. The proposed amendments shown
`
`here directly address the grounds for institution.
`
`
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`16
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`Patent Owner FG SRC LLC
`IPR2020-01449, Ex. 2027, p. 16
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`31.
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`In my expert opinion, proposed amended claim 32 does not broaden
`
`claim scope. To the contrary, the addition of the limiting elements narrows claim
`
`scope. By requiring that “the computational unit is implemented in an FPGA,” the
`
`claim scope is narrowed for the reasons explained above in reference to proposed
`
`amended claim 20. The amendment explicitly excludes the use of a conventional
`
`CPU as the computational unit of the claimed reconfigurable processor, which is
`
`directly responsive to the Zhang, Gupta, and Chien prior art, which relies on the
`
`use of a CPU together with only “small pockets of reprogrammable logic.” Ex.
`
`1003, at 13, col. 2:44-49; see also id. at Fig. 2.
`
`32. Similarly, the claim element “[the] data access unit, and the data
`
`prefetch unit … transfer only data necessary for computations by the
`
`computational unit” is clarified by the amendment that the data is transferred to the
`
`data access units. This amendment does not broaden the proper scope of the claim.
`
`To the contrary, specifying the target of the transfer narrows claim scope because
`
`the data must be transferred there specifically, instead of just “transferred” to any
`
`component. This amendment emphasizes the fact that the claimed inventions
`
`relate to moving computational data from one memory to another, but only that
`
`data that is actually used for the computation. The claim is narrowed by explicitly
`
`not covering a situation where some data is read from the second memory but not
`
`placed in the first memory. This amendment addresses the prior art examples
`
`
`
`17
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`Patent Owner FG SRC LLC
`IPR2020-01449, Ex. 2027, p. 17
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`
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`directed to sparse-matrix operations in Zhang where descriptors for the sparse-
`
`matrix data are read in order to retrieve the computational data but are not
`
`computational data themselves.
`
`IV. REVISION OR SUPPLEMENTATION
`
`33. My opinions are subject to change or revision. I may acquire
`
`additional opinions that Petitioner or its expert may present or information I may
`
`receive in the future or additional work I may perform. With this in mind, based
`
`on the analysis I have conducted and for the reasons set forth, I have preliminarily
`
`reached the conclusions and opinions in this Report.
`
`V. EXHIBITS
`
`34.
`
`In the event of a hearing or trial in this matter, I may create and/or use
`
`various exhibits relevant to this case for the purposes of demonstrating my
`
`testimony as discussed in this Report. I have not yet selected the particular
`
`exhibits or created or assisted in the creation of demonstrative exhibits to assist me
`
`in testifying.
`
`VI. CONCLUSION
`
`35. For at least the reasons stated above, and others, it is my expert
`
`opinion that Petitioner’s references do not disclose all elements of any of the
`
`amended claims of the ’867 Patent.
`
`
`
`18
`
`Patent Owner FG SRC LLC
`IPR2020-01449, Ex. 2027, p. 18
`
`

`

`William Henry Mangione-Smith
`4146 118th Ave NE
`Kirkland WA, 98033
`(425) 654-1424
`billms@gmail.com
`
`Highlights
`
`Reviewed and valued thousands of patents.
`Priced over $500M worth in patent portfolios.
`Key technical support for licensing that has raised more than $1B.
`Significant experience developing claim charts and evidence of use.
`Former tenured professor at the University of California.
`Deposition and trial testifying experience.
`
`Education
`
`BSE (1987), MSE (1992), & Ph.D. University of Michigan
`Doctoral Thesis 1992: Performance Bounds and Buffer Space Requirements for
`Concurrent Processors
`
`Employment
`
`2009-Present
`
` Sole Proprietor of Phase Two LLC – Consulting and intellectual property
`services
`All IP related work since 2009 has been conducted under the auspices of
`Phase Two
`
`2012 May-June
`
`CTO Computers and Consumer Electronics at IP Navigation Group
`
`2005-2008
`2005
`2006
`2007
`2008
`
`2001-2005
`1995-2001
`
`1993-1995
`
`Intellectual Ventures, Bellevue Washington
`Patent valuation, licensing support, focus on computer patents
`Head of all IV valuation efforts – managed a team of 12
`Director of technology, outbound licensing in consumer electronics
`Director of investment strategy, inventor relations
`
`Associate Professor, EE UCLA
`Assistant Professor, EE UCLA
`Focus low power embedded multimedia communications systems
`
`Motorola Wireless Data Group
`Systems architect for General Magic wireless PDA
`
`APPENDIX A
`
`Patent Owner FG SRC LLC
`IPR2020-01449, Ex. 2027, p. 19
`
`

`

`1991-1992
`
`1986-1987
`
`Patents
`
`Motorola Corporate Research
`Parallel computer performance monitoring
`Low power processor architecture
`
`Chrysler Corporation
`Software Architect
`
`9,760,588 - Cross-media storage coordination
`9,747,426 - Handling masquerading elements
`9,716,548 - Data center with free-space optical communications
`9,692,887 - Component information and auxiliary information related to information …
`9,683,884 - Selective audio/sound aspects
`9,680,699 - Evaluation systems and methods for coordinating software agents
`9,659,188 - Obfuscating identity of a source entity affiliated with a communique …
`9,641,537 - Conditionally releasing a communique determined to be affiliated with a …
`9,583,141 - Implementing audio substitution options in media works
`9,513,157 - Selective audio/sound aspects
`9,479,535 - Transmitting aggregated information arising from appnet information
`9,455,035 - Management of memory refresh power consumption
`9,426,387 - Image anonymization
`9,374,242 - Using evaluations of tentative message content
`9,372,536 - Touch screen with tactile feedback
`9,367,833 - Data services outsourcing verification
`9,306,975 - Transmitting aggregated information arising from appnet information
`9,274,582 - Power consumption management
`9,230,601 - Media markup system for content alteration in derivative works
`9,219,815 - Identifier technique for communication interchange
`9,215,512 - Implementation of media content alteration
`9,191,341 - Packet routing within an on-chip network
`9,178,911 - Evaluation systems and methods for coordinating software agents
`9,158,771 - Component information and auxiliary information related to information …
`9,152,928 - Context parameters and identifiers for communication
`9,092,928 - Implementing group content substitution in media works
`9,065,979 - Promotional placement in media works
`9,008,117 - Cross-media storage coordination
`9,008,116 - Cross-media communication coordination
`8,984,579 - Evaluation systems and methods for coordinating software agents
`8,984,133 - Providing treatment-indicative feedback dependent on putative …
`8,966,630 - Generating and distributing a malware countermeasure
`8,949,337 - Generation and establishment of identifiers for communication
`
`Patent Owner FG SRC LLC
`IPR2020-01449, Ex. 2027, p. 20
`
`

`

`8,943,267 - Management of memory refresh power consumption
`8,929,208 - Conditionally releasing a communique determined to be affiliated …
`8,924,975 - Core selection for applications running on multiprocessor systems …
`8,913,753 - Selective audio/sound aspects
`8,910,033 - Implementing group content substitution in media works
`8,886,577 - Feedback during surgical events
`8,850,044 - Obfuscating identity of a source entity affiliated with a communique in …
`8,839,255 - Scheduling of threads by batch scheduling
`8,819,686 - Scheduling threads on different processor cores based on …
`8,818,196 - Data center with free-space optical communications
`8,799,912 - Application selection of memory request scheduling
`8,774,637 - Data center with free-space optical communications
`8,732,087 - Authorization for media content alteration
`8,730,836 - Conditionally intercepting data indicating one or more aspects …
`8,712,250 - Data center with free-space optical communications
`8,682,982 - Preliminary destination-dependent evaluation of message content
`8,655,187 - Data center with free-space optical communications
`8,640,248 - Handling masquerading elements
`8,640,247 - Receiving an indication of a security breach of a protected set of files
`8,627,402 - Evaluation systems and methods for coordinating software agents
`8,626,848 - Obfuscating identity of a source entity affiliated with a communique …
`8,626,731 - Component information and auxiliary information related to …
`8,613,095 - Smart distribution of a malware countermeasure
`8,607,336 - Evaluation systems and methods for coordinating software agents
`8,607,234 - Batch scheduling with thread segregation and per thread type marking …
`8,601,530 - Evaluation systems and methods for coordinating software agents
`8,601,207 - Management of memory refresh power consumption
`8,601,104 - Using network access port linkages for data structure update decisions
`8,588,618 - Data center with free-space optical communications
`8,583,553 - Conditionally obfuscating one or more secret entities with respect to …
`8,5