`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF TEXAS
`AUSTIN DIVISION
`
`FG SRC, LLC,
`
`Plaintiff
`
`-v-
`
`INTEL CORPORATION,
`Defendant
`
`§
`§
`§
`§
`§
`§
`§
`
`1-20-CV-00834-ADA
`
`AMENDED CLAIM CONSTRUCTION ORDER
`
`The Court held a Markman hearing on March 5, 2021. The parties elected to argue the first
`
`two terms only. The Court took the matter under advisement. After reviewing the parties’ briefs,
`
`the patent specification, the prosecution history, and the parties’ arguments, the Court entered a
`
`claim construction order on March 11, 2021 (ECF No. 67). The Court enters this Order to amend
`
`its March 11, 2021 claim construction order.
`
`SIGNED this 5th day of April, 2021.
`
`ALAN D ALBRIGHT
`UNITED STATES DISTRICT JUDGE
`
`Intel Exhibit 1033 - 1
`
`
`
`Case 1:20-cv-00834-ADA Document 73 Filed 04/05/21 Page 2 of 3
`
`Term
`
`“[the data prefetch unit]
`retrieves only computational
`data required by the algorithm
`from a second memory… and
`places the retrieved
`computational data in the first
`memory”
`
`Claim 1
`
`“read and write only data
`required for computations by
`the algorithm between the data
`prefetch unit and the common
`memory”
`
`Claim 9
`
`Plaintiff’s Proposed
`Construction
`“[the data prefetch unit]
`retrieves from a second
`memory that computational
`data which is required by the
`algorithm and no other
`computational data … and
`places the retrieved
`computational data in the first
`memory.”
`
`“read, using the data prefetch
`unit, only data required for
`computations by the algorithm
`from common memory and
`write, using the data prefetch
`unit, only data required for
`computations by the
`algorithm.”
`
`Defendants’ Proposed
`Construction
`“[the data prefetch unit]
`retrieves the data input to the
`algorithm implemented in
`computational logic and no
`other data or instruction from a
`second memory … and places
`the retrieved data in the first
`memory.”
`
`Court’s Final Construction
`
`“[the data prefetch unit]
`retrieves computational data
`required by the algorithm and
`no other data or instructions
`from a second memory … and
`places the retrieved data in the
`first memory”
`
`“read and write the data input
`to the algorithm implemented
`in computational logic and no
`other data or instruction
`between the data prefetch unit
`and the common memory.”
`
`“read and write data required
`for computations by the
`algorithm, and no other data or
`instruction, between the data
`prefetch unit and the common
`memory”
`
`Intel Exhibit 1033 - 2
`
`
`
`Case 1:20-cv-00834-ADA Document 73 Filed 04/05/21 Page 3 of 3
`
`Defendants’ Proposed
`Construction
`“can initiate and carry out its
`operations each of prior to, in
`parallel with, or after the
`requirement for the data input
`to the computational logic.”
`
`Court’s Final Construction
`
`The term “computional” in
`Claim 1 should be construed as
`“computational.”
`
`Plain-and-ordinary meaning
`
`Term
`
`“operates independent of and
`in parallel with logic blocks
`using the [computational data /
`computional [sic] data]”
`
`Claims 1, 9
`
`Plaintiff’s Proposed
`Construction
`The term “computional” in
`Claim 1 should be construed as
`“computational.”
`
`Otherwise, this term has its
`plain and ordinary meaning
`and need not be construed.
`
`In the alternative only,
`this term may be construed to
`have its plain and ordinary
`meaning, which is “executes a
`preconfigured operation
`without intervention of and in
`parallel with logic blocks using
`the computational data.”
`
`Intel Exhibit 1033 - 3
`
`