MULTIPLE UP/DOWN CONVERTERS-CHANNELIZED MULTIPLE UP/DOWN
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`PATHS IN A DIGITAL-ANALOG RADIO TRANSCEIVER
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`BACKGROUND
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`[0001] One way that a wireless cellular service provider can improve the coverage
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`provided by a given base station or group of base stations is by using a distributed
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`antenna system (DAS). In a DAS, radio frequency (RF) signals are communicated
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`between a host unit and one or more remote antenna units (RAUs). The host unit is
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`communicatively coupled to one or more base stations, for example, where the host unit
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`is directly connected to the base station using coaxial cabling or where the host unit
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`communicates with the base station wirelessly (that is, “over the air” or “on frequency”)
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`using a donor antenna and a bi-directional amplifier (BDA)). Downlink RF signals are
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`received from the base station at the host unit. The host unit uses the downlink RF
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`signals to generate a downlink transport signal for distributing to one or more of the
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`RAUs. Each such RAU receives the downlink transport signal and reconstructs the
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`downlink RF signals from the downlink transport signal and causes the reconstructed
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`downlink RF signals to be radiated from at least one antenna coupled to or included in
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`that RAU. A similar process is performed in the uplink direction. Uplink RF signals
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`received at one or more RAUs are used to generate respective uplink transport signals
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`that are transmitted from the respective RAUs to the host unit. The host unit receives and
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`combines the uplink transport signals transmitted from the RAUs. The host unit
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`reconstructs the uplink RF signals received at the RAUs and communicates the
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`reconstructed uplink RF signals to the base station. In this way, the coverage of the base
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`station can be expanded using the DAS. One or more intermediate devices (also referred
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`to as “expansion hubs” or “expansion units”) can be placed between the host unit and the
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`remote antenna units in order to increase the number of RAUs that a signal host unit can
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`feed and/or to increase the host-unit-to-RAU distance.
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`Attorney Docket No. 100.1077USPR
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`JMA v. Dali
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`J MA EX1 0 09
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`[0002] One type of DAS generates the downlink and uplink transport signals by down-
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`converting the respective downlink and uplink RF signals into baseband digital signals
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`for transport at a data rate that is suitable for transmission over an optical fiber (also
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`referred to herein as a DAS fiber).
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`[0003] However, when data to be transported is in separate spectral regions of the RF
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`spectrum, fiber bandwidth is wasted since the non-used spectral region between the
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`separated spectral regions of interest is transported in the timeslots that accommodate the
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`spectral regions of interest as well as the non-used spectral region between the separated
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`spectral regions of interest. For example, if two 5 MHz slices of RF spectrum include
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`data to be transported and the two 5 MHz slices of RF spectrum are separated by a 20
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`MHz non-used slices of the RF spectrum, then six (6) timeslots are transported across the
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`optical fiber in order to send the two 5 MHz data-carrying portions of RF. If the two 5
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`MHz slices of RF spectrum were in adjacent portions of the RF spectrum than only two
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`(2) timeslots would be required.
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`DRAWINGS
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`[0004] Figure l is a block diagram of one embodiment of a distributed antenna system
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`for distributing radio frequency signals within a coverage area in accordance with the
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`present invention;
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`[0005] Figure 2A is a block diagram of an embodiment of a complete-spectral region in
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`accordance with the present invention;
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`[0006] Figure 2B is a block diagram of an embodiment of assigned time slots in
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`accordance with the present invention;
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`[0007] Figure 3 is a block diagram of an embodiment of a digital-analog radio
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`transceiver in accordance with the present invention;
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`[0008] Figure 4 is a block diagram of an embodiment of a host unit in accordance with
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`the present invention;
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`[0009] Figure 5A is a block diagram of an embodiment of a complete-spectral region in
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`accordance with the present invention;
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`[0010] Figure 5B is a block diagram of an embodiment of assigned time slots in
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`accordance with the present invention;
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`[0011] Figure 6 is a flow diagram of one embodiment of a method to distribute radio
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`frequency signals in separated radio frequency spectral regions in accordance with the
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`present invention;
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`[0012] Figure 7 is a flow diagram of one embodiment of a method to generate digital
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`baseband data associated with a first and a second spectral region on a respective first and
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`second path in a digital-analog radio transceiver in accordance with the present invention;
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`[0013] Figure 8 is a flow diagram of one embodiment of a method to receive digital
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`signals associated with radio frequency signals in separate spectral regions in accordance
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`with the present invention; and
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`[0014] Figure 9 is a block diagram of an embodiment of a host unit in accordance with
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`the present invention.
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`[0015] Like reference numbers and designations in the various drawings indicate like
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`elements. The details of various embodiments of the claimed invention are set forth in
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`the accompanying drawings and the description below. Other features and advantages
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`will become apparent from the description, the drawings, and the claims.
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`DETAILED DESCRIPTION
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`[0016] Figure l is a block diagram of one embodiment of a distributed antenna system
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`(DAS) 10 for distributing radio frequency signals within a coverage area in accordance
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`with the present invention. The DAS 10 includes a host unit 100 and a remote antenna
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`unit 200 communicatively coupled by an optical fiber 50. The host unit 100 and the
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`remote antenna unit 200 each include a respective antenna 160 and 260. The antennas
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`160 and 260 fianction to radiate and receive radio frequency signals. The host unit 100
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`and the remote antenna unit 200 process radio frequency signals received at the
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`respective antennas 160 and 260 and transceive transport signals associated with radio
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`frequency signals in a first spectral region and in a second spectral region. A non-
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`relevant spectral region separates the second spectral region from the first spectral region.
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`The first spectral region, the second spectral region, and the intervening non-relevant
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`spectral region together form a complete-spectral region. Any information that may be
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`carried by the RF signals in the non-relevant spectral region is not relevant to devices that
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`are communicatively coupled to the remote antenna unit 200. That is, any device
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`communicatively coupled to the remote antenna unit 200 does not attempt to receive data
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`carried in the non-relevant spectral region, at least while the device is communicatively
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`coupled to the remote antenna unit 200.
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`[0017] Figure 2A is a block diagram of an embodiment of a complete-spectral region 300
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`in accordance with the present invention. The first spectral region 351 having a first
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`bandwidth BWl is separated from the second spectral region 352 having a second
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`bandwidth BW2 by the intervening non-relevant spectral region 350. The terms "spectral
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`region" and "radio frequency spectral region" are used interchangeably herein. In one
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`implementation of this embodiment, the complete spectral region 300 is 75 MHZ. In
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`another implementation of this embodiment, the complete spectral region 300 is 60 MHZ.
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`In yet another implementation of this embodiment, the complete spectral region 300
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`covers the wide RF spectrum for portable communication systems (PCS), which extends
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`over 65-70 MHZ. In the exemplary case shown in Figure 2A, the first bandwidth BWl is
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`greater than the second bandwidth BW2; however the first bandwidth BWl can be
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`smaller than the second bandwidth BW2.
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`[0018] As shown in Figure l, the host unit 100 includes a host digital-analog radio
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`transceiver (DART) 110, a host serialized radio frequency (SeRF) component 135, an
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`analog-to-digital (A/D) converter 140, and a digital-to-analog (D/A) converter 145. The
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`embodiment of host unit 100 shown in Figure l is communicatively coupled to a radio
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`frequency circuitry (RF) 150 and a host antenna 160. In one implementation of this
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`embodiment, the host unit 100 is communicatively coupled to a base station. In another
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`implementation of this embodiment, the radio frequency circuitry 150 is in the host unit
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`100. The host DART 110 is communicatively coupled to the host SeRF component 135
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`via link 40, which is configured to send digital baseband data in allocated time slots. The
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`host SeRF component 135 is configured to generate transport signals from the digital
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`baseband data in allocated time slots and to send the transport signals over the optical
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`fiber 50. RF circuitry 150 is communicatively coupled to receive input from the host
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`antenna 160 and from the digital-to-analog converter 145 and to send output to the
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`analog-to-digital converter 140 and the host antenna 160.
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`[0019] The host DART 110 is shown in Figure 1 as a host DART field programmable
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`gate array (FPGA) 110. The host SeRF component 135 is shown in Figure 1 as a host
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`SeRF FPGA 135. It is to be understood that the host DART 110 and/or the host SeRF
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`component 135 can be a programmable logic device (PLD) or an application-specific
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`integrated circuit (ASIC). The host DART 110 and/or the host SeRF component 135 can
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`also be designed from some future developed technology that provides the same
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`programmable function as the FPGA, the PLD, or the ASIC technologies. The host
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`DART 110 is also referred to herein as “DART FPGA 110,” or “host DART FPGA 110.”
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`The host SeRF component 135 is also referred to herein as “SeRF FPGA 135,” “host
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`SeRF FPGA 135,” or “SeRF component 135.”
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`[0020] The remote antenna unit 200 is similarly configured to include a remote DART
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`210, a remote SeRF component 235, an analog-to-digital (A/D) converter 240, and a
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`digital-to-analog (D/A) converter 245. The remote antenna unit 200 is communicatively
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`coupled to a remote antenna 260 via radio frequency circuitry (RF) 250. In one
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`implementation of this embodiment, the remote antenna unit 200 includes radio
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`frequency circuitry (RF) 250 and the remote antenna 260. The remote DART 210 is
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`communicatively coupled to the remote SeRF component 235 via link 60, which is
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`configured to send digital baseband data in allocated time slots. RF circuitry 250 is
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`communicatively coupled to receive input from the remote antenna 260 and the digital-
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`to-analog converter 245 and to send output to the analog-to-digital converter 240 and to
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`the remote antenna 260. The remote DART 210 is also referred to herein as “DART
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`FPGA 210,” or “remote DART FPGA 210.” The remote SeRF component 235 is also
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`referred to herein as “SeRF FPGA 235,” “remote SeRF FPGA 235,” or “SeRF
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`component 235.”
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`[0021] The host unit 100 and the remote antenna unit 200 process radio frequency signals
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`received at the respective antennas 160 and 260 by generating digital baseband data that
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`fit into adjacent assigned time slots. The host unit 100 generates digital transport signals
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`(referred to herein as “transport signals”) from the radio frequency signals received at the
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`antenna 160 in the first spectral region 351 and second spectral region 352 (Figure 2A).
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`Since digital baseband data is not generated or transported for the non-relevant spectral
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`region 350, fewer assigned time slots are required to accommodate the digital baseband
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`data than would be if the digital baseband data were generated for the non-relevant
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`spectral region 350. This results in bandwidth conservation in the optical fiber 50. Thus,
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`the host unit 100 sends transport signals that occupy a reduced bandwidth of the optical
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`fiber 50 to the remote antenna unit 200. The remote antenna unit 200 receives the
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`transport signals from the host unit 100 via the optical fiber 50. In one implementation of
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`this embodiment, the transport signals are transmitted at a 3.072 Gbps data rate.
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`[0022] The DAS 10 is bi-directional, so the remote antenna unit 200 generates digital
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`transport signals from the radio frequency signals received at the remote antenna 260 in
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`the first spectral region 351 and second spectral region 352 and sends transport signals
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`that occupy a reduced bandwidth of the optical fiber 50 to the host unit 100. The host
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`unit 100 receives transport signals from the remote antenna unit 200 via the optical fiber
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`50. In one implementation of this embodiment, the remote antenna unit 200 generates
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`digital transport signals from the radio frequency signals received at the remote antenna
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`260 in a third spectral region and a fourth spectral region and sends transport signals that
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`occupy a reduced bandwidth of the optical fiber 50 to the host unit 100.
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`[0023] The DAS 10 is implemented if a customer wants to use a low frequency band
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`(such as first spectral region 351) and a high frequency band (such as, second spectral
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`region 352) and does not want to use the in-between region of spectrum (such as non-
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`relevant spectral region 350). An implementation of embodiments of the methods and
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`systems described herein, allow a customer to use one DART board at the host unit (such
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`as host DART FPGA 110) and one DART board the remote antenna unit (such as remote
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`DART FPGA 210) to process all frequencies from low to high but to only actually
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`transport signals for the frequency ranges of interest that are separated by a non-relevant
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`spectral region or regions in adjacent time slots. Since time slots are not assigned for the
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`non-relevant spectral region, the number of assigned time slots is less than the number of
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`time slots associated with a complete-spectral region.
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`[0024] Figure 2B is a block diagram of an embodiment of assigned time slots 550 in
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`accordance with the present invention. The assigned timeslots 550 include a first time
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`slot (TSl) 551, a second time slot (TS2) 552, a third time slot (TS3) 553 and a fourth
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`time slot (TS4) 554. In this exemplary case, the first time slot 551, the second time slot
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`552, the third time slot 553 form a first set of time slots 501 and the fourth time slot
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`forms a second set of time slots 502. The digital signals associated with the first spectral
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`region 351 are assigned to the first set of time slots 501. The digital signals associated
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`with the second spectral region 352 are assigned to the second set of time slots 502. The
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`first set of time slots 501 and the second set of time slots 502 in total can include up to
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`the maximum number of time slots the DART is designed to process (for example, in one
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`embodiment a DART is designed for six time slots). The first set of time slots 501 and
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`the second set of time slots 502 do not overlap. No time slots are assigned to the non-
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`relevant spectral region 350. At least one time slot (such as time slot 553) in the first set
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`of time slots 501 is adjacent to at least one-other time slot (such as time slot 554) in the
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`second set of time slots 502.
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`[0025] Figure 1 only shows a single remote antenna unit 200, although it is to be
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`understood that the DAS 10 can include a plurality of remote antenna units 200 that are
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`communicatively coupled to the host unit 100.
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`[0026] Figure 3 is a block diagram of an embodiment of a host digital-analog radio
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`transceiver 110 in accordance with the present invention. The host DART 110 and link
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`41 of Figure 1 are shown in greater detail in Figure 3. The host DART 110 is shown as a
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`host DART FPGA 110 in Figure 3, although it is to be understood that the host DART
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`110 can be a PLD or an ASIC. The host DART 110 includes a user interface 109. The
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`host DART 110 includes conditioning logic 117, a first digital down converter 125, a
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`second digital down converter 126, a DART transmitter 121, a low-voltage digital
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`signaling circuit 115, a DART receiver (RX) 123, a first digital up converter 128, a
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`second digital up converter 129, and conditioning logic 119. In one implementation of
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`this embodiment, the conditioning logic 117 and the conditioning logic 119 are the same
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`conditioning logic.
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`[0027] An additional optional optical fiber 51 to communicatively couple the host unit
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`100 to the remote unit 200 (Figure 1) is shown in Figure 3. The optical fiber 51 is similar
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`in structure and filnction to the optical fiber 50 of Figure 1.
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`[0028] The DART FPGA 110 is communicatively coupled to the SeRF component 135
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`by the link 41, which is a bidirectional low-voltage digital signaling (LVDS) link. The
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`link 41 is also referred to herein as a “DART link 41 .” A first LVDS lane represented
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`generally at 45 and a second LVDS lane represented generally at 46 are supported by the
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`link 41. The link 41 runs at a fixed rate regardless of the payload (i.e., regardless of the
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`number of time slots sent). In one embodiment, up to a maximum of six (6) time slots are
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`supported by the link 41 for up to two (2) radio frequency slices (351, 352). In another
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`embodiment, up to a maximum of twelve (12) time slots are supported by the link 41 for
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`up to four (4) radio frequency slices (351, 352). One of ordinary skill in the art upon
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`reading this specification would appreciate that in other embodiments of the present
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`invention, the maximum number of supported time slots is based on the number of
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`timeslots supported by the particular DART FPGAs used.
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`[0029] The analog-to-digital converter 140 receives analog signals in the complete
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`spectral region 300 from the RF circuitry 150 (Figure 1) and outputs associated digital
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`data to the host DART FPGA 110 via link 141. The converted the radio frequency
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`signals are output from the analog-to-digital converter 140 as digital signals having an
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`input data rate. The terms “digital signals” and “digital data” are used herein
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`interchangeably. The terms “digital baseband signals” and “digital baseband data” are
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`used herein interchangeably. The link 141 transports the digital data at the input data
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`rate. The digital-to-analog converter 145 receives digital data from the host DART
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`FPGA 110 via link 146 and outputs associated analog signals to the RF circuitry 150.
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`The link 146 transports data an output data rate.
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`[0030] In one implementation of this embodiment, first LVDS lane 45 and second LVDS
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`lane 46 each transport digital baseband data at a 737.28 Mbps data rate. In this case, the
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`first LVDS lane 45 and second LVDS lane 46 together transport digital baseband data at
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`a 1474.56 Mbps data rate in up to six (6) timeslots in a DART link 41.
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`[0031] The SeRF component 135 is communicatively coupled to receive digital baseband
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`data allocated to time slots from the host DART FPGA 110. The digital baseband data
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`are allocated to the time slots based on the first bandwidth BWl and second bandwidth
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`BW2 of the first spectral region 351 and the second spectral region 352, respectively. RF
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`analog signals in an approximately 5 MHz slice are processed for sending in one (1) time
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`slots. RF analog signals in an approximately 36 MHz slice are processed for sending in
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`six (6) time slots. RF analog signals in an approximately 75 MHz slice are processed for
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`sending in twelve (12) time slots. The host unit 100 uses a dart FPGA 110 that includes
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`four lanes thus doubling the bandwidth to transmit data in 12 time slots.
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`[0032] The data related to the wider bandwidth is assigned to the first time slot. For
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`example, if the first bandwidth BWl of the first spectral region 351 is greater than the
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`second bandwidth BW2 of the second spectral region 352 (Figure 2A), the data
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`associated with the first spectral region 351 is assigned to the first time slot, the second
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`time slot, the third time slot, etc. until the data associated with the first spectral region
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`351 is all allocated. Once all the data for the first spectral region 351 is allotted, the data
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`associated with the second spectral region 352 is allocated to the at least one of the
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`remaining time slots. The data associated with separate RF spectral regions is
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`consecutively allocated in adjacent time slots. Thus, the number of time slots used to
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`transport the signals in the first spectral region 351 and the second spectral region 352 is
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`less than the number of time slots associated with a complete-spectral region 350.
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`[0033] The host DART FPGA 110 is built to know how many slots it can read. The host
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`DART FPGA 110 is provisioned based on the algorithm of N slots for the respective first
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`spectral region 351 and M slots the second spectral region 352. N and M are integers. In
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`one implementation of this embodiment, a user inputs information indicative of the N+M
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`timeslots via the user interface 109. Then software in the host DART FPGA 110 builds
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`the correct architecture for the N+M timeslots. In exemplary cases, the time slots (N+M)
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`can be (1+1), (2+2), (2+3),. . .(5+1) and any other permutation that sums to six for a
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`single host DART FPGA 110. The framework of the host DART FPGA 110 for each of
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`these permutations is the same, but different down convert filters, up convert filters, and
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`different interpolation ratios are used for the different architectures.
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`[0034] The analog-to-digital converter 140 converts the downlink radio frequency signals
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`to digital signals and outputs the digital signals to the host DART FPGA 110. The
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`digital-to-analog converter 145 receives uplink digital signals from the host DART FPGA
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`110 and converts the digital signals to radio frequency signals having frequencies in the
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`first spectral region 351 and the second spectral region 352.
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`[0035] The conditioning logic 117 receives data from the analog-to-digital converter 140.
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`The conditioning logic 117 directs the digital signals received from the analog-to-digital
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`converter 140 onto at least two separate paths. The first path includes a transmitting end
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`of the first path 130 and a receiving end of the first path 132. The second path includes a
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`transmitting end of the second path 131 and a receiving end of the second path 133. The
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`digital signals associated with a first spectral region 351 are directed by the conditioning
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`logic 117 to the transmitting end of the first path 130, and the digital signals associated
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`with the second spectral region 352 are directed by the conditioning logic 117 to the
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`transmitting end of the second path 131. Likewise, the conditioning logic 119 is
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`configured to direct the digital signals received from the receiving end of the first path
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`132 and from the receiving end of the second path 133 to the digital-to-analog converter
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`145. The terms "first path 130" and “a transmitting end of the first path 130” are used
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`interchangeably herein. The terms "second path 131" and “a transmitting end of the first
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`path 131” are used interchangeably herein.
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`[0036] A first digital down converter 125 in the first path 130 receives a first portion of
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`output (digital signals) from the conditioning logic 117 at an input data rate and converts
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`the first portion of digital signals received from the conditioning logic 117 to digital
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`baseband signals having a first data rate (1St DR). As defined herein, the first portion of
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`the digital signals are the digital signals generated from the first spectral region 351 that
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`has a first bandwidth BWl. The first data rate is a function of the first bandwidth BWl.
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`[0037] The second digital down converter 126 in the second path 131 receives a second
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`portion of output (digital signals) from the conditioning logic 117 at the input data rate
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`and converts the second portion of digital signals received from the conditioning logic
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`117 to digital baseband signals having a second data rate (2Ild DR). As defined herein, the
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`second portion of the digital signals are the digital signals generated from the second
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`spectral region 352 that has a second bandwidth BW2. The second data rate is a function
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`of the second bandwidth BW2.
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`[0038] The first digital up converter 128 in the receiving end of the first path 132
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`converts digital baseband signals having the first data rate that are received from the
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`SeRF component 135 to digital signals having an output data rate. The second digital up
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`converter in a receiving end of the second path 133 converts digital baseband signals
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`having the second data rate that are received from the SeRF component 135 to digital
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`signals having the output data rate.
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`[0039] A DART transmitter (TX) 121 is positioned to receive output (digital baseband
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`data) from the first digital down converter 125 at the first data rate and to receive output
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`(digital baseband data) from the second digital down converter 126 at the second data
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`rate. The DART transmitter 121 serializes the received input and outputs the serialized
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`data to a low-voltage digital signaling circuit 115.
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`[0040] The low-voltage digital signaling circuit 115 receives the output from the first and
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`the second digital down converters 125 and 126 and outputs two low-voltage digital
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`signaling lanes of digital baseband data via link 41 to the SeRF component 135.
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`Likewise, the low-voltage digital signaling circuit 115 receives the digital baseband data
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`output from the SeRF component 135 in two low-voltage digital signaling lanes of link
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`41. Then the low-voltage digital signaling circuit 115 sends output to the first and the
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`second digital up converters 128 and 129 via the DART receiver 123.
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`[0041] The DART receiver 123 is positioned to receive input from the low-voltage
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`digital signaling circuit 115 and to direct an output to either the first digital up converter
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`128 or the second digital up converter 129, depending on the number of time slots
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`allotted for the signals as defined by the FPGA architecture.
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`[0042] The first digital up converter 128 receives digital baseband signals at a first data
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`rate from the low-voltage digital signaling circuit 115 via the DART receiver 123 and
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`outputs digital signals at an output data rate to the conditioning logic 119. The second
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`digital up converter 129 receives digital baseband signals at a second data rate from the
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`low-voltage digital signaling circuit 115 via the DART receiver 123 and outputs digital
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`signals at an output data rate to the conditioning logic 119.
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`[0043] The discussion related to the host DART FPGA 110 and the host SeRF FPGA 135
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`is also applicable to the remote DART FPGA 210 and the remote SeRF component 235
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`(Figure 1) in the remote unit 200. The remote SeRF component is communicatively
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`coupled via the optical fiber 50 to receive the transport signals from the host SeRF
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`component 135. The remote SeRF component 235 is configured to generate digital
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`baseband data allocated to a reduced number of time slots from the transport signals. The
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`remote DART 210 in the remote antenna unit 200 is communicatively coupled to receive
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`the digital baseband data from the remote SeRF component 235. The remote DART 210
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`has a first path for processing digital signals associated with the radio frequency signals
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`in the first spectral region 351 and a second path for processing digital signals associated
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`with the radio frequency signals in the second spectral region 352. The remote antenna
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`260 is communicatively coupled to the remote DART 210 and radiates the radio
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`frequency signals having frequencies in the first spectral region 351 and the second
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`spectral region 352.
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`[0044] The remote DART FPGA 210 is provisioned based on the algorithm of N slots for
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`the respective first spectral region 351 and M slots the second spectral region 352. The
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`remote DART FPGA 210 includes conditioning logic, a first digital down converter, a
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`second digital down converter, a DART transmitter, a low-voltage digital signaling
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`circuit, a DART receiver, a first digital up converter, and a second digital up converter.
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`The analog-to-digital converter 240 converts the uplink radio frequency signals to digital
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`signals and outputs the digital signals to the remote DART FPGA 210. In this manner,
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`the remote DART FPGA 210 and the remote SeRF component 235 filnction similarly to
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`the host DART FPGA 110 and the host SeRF FPGA 135 to transceive transport signals
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`via the optical fiber 50 while using a reduced fiber bandwidth since the digital baseband
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`data generated at the remote DART 210 are allocated to the reduced number of time slots.
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`[0045] Figure 4 is a block diagram of an embodiment of a host unit 101 in accordance
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`with the present invention. The host unit 101 of Figure 4 differs from the host unit 100 of
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`Figure 3 in that there is a first host DART FPGA 112 and a second host DART FPGA
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`114 in the host unit 101, in place of the single host DART FPGA 110 in the unit 100 of
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`Figure 3. The first and second host DART FPGAs 112 and 114 are similar in structure
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`and filnction to the host DART FPGA 110 (Figure 3). A DART 113 includes the first
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`host DART FPGA 112, the analog-to-digital converter 140, and the digital-to-analog
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`converter 145. A DART 213 includes the second host DART FPGA 114, the analog-to-
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`digital converter 140, and the digital-to-analog converter 145.
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`[0046] Each of the first host DART FPGA 112 and the second host DART FPGA 114 are
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`operable to transport six (6) time slots so the host unit 101 is operable to send twelve (12)
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`time slots over the link 41 in up to four (4) LVDS lanes from the DART 113 and DART
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`213 to the SeRF FPGA 135. The link 41 is also referred to herein as a “DART link 41 ."
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`The first LVDS lane and the second LVDS lanes represented generally as LVDS lanes 42
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`are implemented to transmit data between the DART 113 and the SeRF component 135.
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`The third LVDS lane and the fourth LVDS lane represented generally as LVDS lanes 43
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`are implemented to transmit data between the DART 213 and the SeRF component 135.
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`The first, second, third, and fourth LVDS lanes are all included in the link 41, which is
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`physically a single cable. The lanes each run at 738.28 Mbps. The lanes can carry data or
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`they can be empty. One lane configured to carry 3 timeslots. Four lanes carry 12 time
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`slots. The host unit 101 has four lanes to carry up to twelve time slots. In one
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`implementation of this embodiment, the first, second, third, and fourth LVDS lanes
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`Attorney Docket No. 100.1077USPR
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`transport digital baseband data associated with the first spectral region 351 and the
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`second spectral region 352 in the complete spectral region 300. In another
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`implementation of this embodiment, the first, second, third, and fourth LVDS lanes
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`transport digital baseband data associated with more than two spectral regions.
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`[0047] Figure 5A is a block diagram of an embodiment of a complete-spectral region 300
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`in accordance with the present invention. The first spectral region 351 having a first
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`bandwidth BWl is separated from the second spectral region 352 having a second
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`bandwidth BW2 by the intervening non-relevant spectral region 350. Additionally, a
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`third spectral region 353 having a third bandwidth BW3 is separated from the second
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`spectral region 352 by an intervening non-relevant spectral region 355. A fourth spectral
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`region 354 having a fourth bandwidth BW4 is separated from the third spectral region
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`353 by an intervening non-relevant spectral region 356. It is to be understood that the
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`relative order of the spectral regions 351, 352, 352, and 353 is not necessarily as shown
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`in Figure 5A. The first spectral region 351, the second spectral region 352, the third
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`spectral region 353, and the fourth spectral region 354, and the intervening non-relevant
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`spectral regions 350, 355, and 356 together form the complete-spectral region 300.
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`[0048] Figure 5B is a block diagram of an embodiment of assigned time slots 560 in
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`accordance with the present invention. The assigned timeslots 560 include a first time
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`slot 551, a second time slot 552, a third time slot 553, a fourth time slot 554, and a fifth
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`time slot (TS5) 555. In this exemplary case, the first time slot 551 and the second time
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`slot 552 form a first set of time slots 501; the third and fourth time slots 553, 554 form a
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`second set of time slots 502; and the fifth time slot 555 forms a third set of time slots 503.
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`The digital signals associated with the third spectral region are assigned to the third set of
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`time slots. The first, second and third set of time slots 501, 502, and 503, resp