(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2002/0000576 A1
`
`Inukai
`(43) Pub. Date:
`Jan. 3, 2002
`
`US 20020000576A1
`
`(54) DISPLAY DEVICE
`
`Publication Classification
`
`(76)
`
`Inventor: Kazutaka Inukai, Kanagawa (JP)
`
`Correspondence Address:
`JOHN F. HAYDEN
`Fish & Richardson RC.
`$;5:$;::::1¥)1(:St2r33351\1(¥$
`
`(21) Appl. N0.:
`
`09/886,148
`
`(22)
`
`Filed:
`
`Jun. 22, 2001
`
`(30)
`
`Foreign Application Priority Data
`
`Jun. 22, 2000
`
`(JP) ...................................... 2000-188518
`
`Int. Cl.7 ..................................................... H01L 27/10
`(51)
`(52) us. Cl.
`.............................................................. 257/202
`
`(57)
`ABSTRACT
`An active rnatriX display device .capable of vivid color
`display hav1ng many tones 1s pr0v1ded. The display dev1ce
`is characterized in that each of a plurality of pixels com-
`prises a first TFT for switching, a second TFT for switching,
`a TFT for erasing, a TFT for EL driving, and an EL elernent,
`driving of the TFT for EL driving is controlled by the first
`TFT for switching, the second TFT for switching, and the
`TFT for erasing, and light emission by the EL element is
`controlled by the TFT for EL driving.
`
`
`
`G—CLK, G—SP
`
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`Jan. 3, 2002 Sheet 1 0f 28
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`US 2002/0000576 A1
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`
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`G-CLK, G-SP
`
`Fig. 1
`
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`Patent Application Publication
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`Jan. 3, 2002 Sheet 10 0f 28
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`US 2002/0000576 A1
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`|PR2020-01275
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`Patent Application Publication
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`Jan. 3, 2002 Sheet 19 0f 28
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`US 2002/0000576 A1
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`Fig. 19A
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`Patent Application Publication
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`Patent Application Publication
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`Jan. 3, 2002 Sheet 21 0f 28
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`US 2002/0000576 A1
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`Jan. 3, 2002
`
`DISPLAY DEVICE
`
`BACKGROUND OF THE INVENTION
`
`[0001]
`
`1. Field of the Invention
`
`[0002] The present invention relates to an electronic dis-
`play formed by forming EL (electroluminescence) elements
`on a substrate. In particular, the present invention relates to
`an EL display using semiconductor elements (elements
`using a semiconductor thin film). Further, the present inven-
`tion relates to a display device with an EL display used in its
`display portion.
`
`[0003]
`
`2. Description of the Related Art
`
`[0004] Recently, technology for forming TFTs on a sub-
`strate has greatly progressed, and its application to an active
`matrix electronic display is actively developed. In particular,
`TFTs using a polysilicon film have higher field effect mobil-
`ity (also referred to as mobility) than that of conventional
`TFTs using an amorphous silicon film, and thus, they are
`capable of high-speed operation, which makes it possible to
`control pixels with a driver circuit formed on the substrate
`having the pixels formed thereon, while, conventionally,
`such control of pixels is performed by a driver circuit
`provided outside the substrate.
`
`[0005] Since various kinds of circuits and elements are
`formed on one substrate in such an active matrix electronic
`
`display, there are various advantages such as reduction in the
`manufacturing cost, miniaturization of the electronic dis-
`play, improvement in yield, and improvement in throughput.
`
`In addition, active matrix EL displays having EL
`[0006]
`elements as light emitting elements are actively researched.
`EL displays are also referred to as organic EL displays
`(OELDs) or organic light emitting diodes (OLEDs).
`
`[0007] Different from a liquid crystal display, an EL
`display is of a light emitting type. An EL element
`is
`structured such that a layer containing an organic compound
`which causes luminescence by applying an electric field
`thereto (hereinafter referred to as an EL layer) is sandwiched
`between a pair of electrodes (an anode and a cathode).
`Normally, the EL layer has a laminated structure. A typical
`laminated structure is “a positive hole transport layer/a light
`emission layer/an electron transport
`layer” proposed by
`Tang et al. of Eastman Kodak Company. This structure has
`a very high light emission efficiency, and thus, is adopted by
`almost all EL displays under research and development at
`present.
`
`[0008] The structure may also be such that “a positive hole
`injection layer/a positive hole transport layer/a light emis-
`sion layer/an electron transport layer” or “a positive hole
`injection layer/a positive hole transport layer/a light emis-
`sion layer/an electron transport layer/an electron injection
`layer” are laminated in this order on an anode. Further, a
`fluorescent pigment or the like may be doped into the light
`emission layer.
`
`layers provided
`In the present specification, all
`[0009]
`between a cathode and an anode are collectively referred to
`as an EL layer. Therefore, all of the above-mentioned
`positive hole injection layer, positive hole transport layer,
`light emission layer, electron transport layer, and electron
`injection layer are included in the EL layer.
`
`[0010] When the pair of electrodes apply predetermined
`voltage to the EL layer structured as in the above, carriers
`recombine in the light emission layer to emit light. That an
`EL element emits light is herein referred to as “the EL
`element is driven”. It is also to be noted that a light emitting
`element formed of an anode, an EL layer, and a cathode is
`herein referred to as an EL element.
`
`[0011] Light emitted by an EL layer can be broken down
`into light emitted when a particle returns from a singlet
`excited state to a ground state (fluorescence) and light
`emitted when a particle returns from a triplet excited state to
`a ground state (phosphorescence). In the present invention,
`either one of the above two kinds of light emission may be
`used, or alternatively, both of them may be used.
`
`[0012] Methods of driving an EL display include an ana-
`log driving method (analog driving). An analog-driven EL
`display is described with reference to FIGS. 26 and 27.
`
`[0013] FIG. 26 illustrates a structure of a pixel portion
`1800 of an analog-driven EL display. Gate signal
`lines
`Gl-Gy to which a gate signal from a gate signal line driver
`circuit is inputted are connected to gate electrodes of TFTs
`1801 for switching of the respective pixels. One of a source
`region and a drain region of each of the TFTs 1801 for
`switching of each pixel is connected to a source signal line
`(also referred to as a data signal line) Sl, .
`.
`.
`, Sx to which
`an analog video signal is inputted, while the other is con-
`nected to a gate electrode of a TFT 1804 for EL driving of
`each pixel and to a capacitor 1808 of each pixel.
`
`[0014] A source region of the TFT 1804 for EL driving of
`each pixel is connected to a power supply line V1, .
`.
`.
`, Vx,
`while a drain region of the TFT 1804 for EL driving is
`connected to an EL element 1806. Electric potential of the
`power supply lines V1 to Vx is referred to as power source
`potential. Further,
`the power supply lines V1 to Vx are
`connected to capacitors 1808 of the respective pixels.
`
`[0015] The EL element 1806 has an anode, a cathode, and
`an EL layer provided between the anode and the cathode. In
`case the anode of the EL element 1806 is connected to the
`
`drain region of the TFT 1804 for EL driving, the anode of the
`EL element 1806 is a pixel electrode while its cathode is an
`opposing electrode. Conversely, in the case where the cath-
`ode of the EL element 1806 is connected to the drain region
`of the TFT 1804 for EL driving, the anode of the EL element
`1806 is an opposing electrode while its cathode is a pixel
`electrode.
`
`It is to be noted that the electric potential of an
`[0016]
`opposing electrode is herein referred to as opposing poten-
`tial, and a power source which applies the opposing potential
`to an opposing electrode is herein referred to as an opposing
`power source. The difference between the potential of a
`pixel electrode and the potential of an opposing electrode is
`voltage for EL driving, which is applied to the EL layer.
`
`[0017] FIG. 27 illustrates a timing chart in the case where
`the EL display illustrated in FIG. 26 is driven in an analog
`method. Aperiod from the time when one gate signal line is
`selected to the time when the next gate signal line is selected
`is referred to as one line period (L). Aperiod from the time
`when one image is displayed to the time when the next
`image is displayed is one frame period (F). With regard to
`the EL display illustrated in FIG. 26, since the number of the
`gate signal lines is y, y line periods (L1 to Ly) are provided
`in one frame period.
`
`|PR2020-01275
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`US 2002/0000576 A1
`
`Jan. 3, 2002
`
`In the present specification, that a gate signal line
`[0018]
`is selected means that all the thin film transistors whose gate
`electrodes are connected to the gate signal line are in the ON
`state.
`
`[0019] As the resolution becomes higher, the number of
`line periods in one frame period increases, and accordingly,
`a driver circuit has to be driven at a higher frequency.
`
`[0020] First, the power supply lines V1 to Vx are held at
`a certain power source potential. The opposing potential
`which is the potential of the opposing electrodes is also held
`at a certain potential, which has different power source
`potential such that the EL elements emit light.
`
`In a first line period (L1), the gate signal line G1 is
`[0021]
`selected according to a gate signal inputted from a gate
`signal line driver circuit to the gate signal line G1.
`
`[0022] Then, an analog video signal is sequentially input-
`ted to the source signal lines $1 to Sx. Since all the TFTs
`1801 for switching connected to the gate signal line G1 are
`in the ON state,
`the analog video signal inputted to the
`source signal lines $1 to Sx is inputted through the TFTs
`1801 for switching to the gate electrodes of the TFTs 1804
`for EL driving.
`
`[0023] The amount of electric current through channel
`forming regions of the TFTs 1804 for EL driving is con-
`trolled by the magnitude of the potential (voltage) of the
`signal inputted to the gate electrodes of the TFTs 1804 for
`EL driving. Therefore,
`the potential applied to the pixel
`electrodes of the EL elements 1806 is determined by the
`magnitude of the potential of the analog video signal input-
`ted to the gate electrodes of the TFTs 1804 for EL driving.
`The EL elements 1806 emit
`light under control of the
`potential of the analog video signal.
`
`[0024] The above-described operation is repeated. When
`the analog video signal has been inputted to all the source
`signal lines $1 to Sx, the first line period (L1) ends. It is to
`be noted that the period inputting of the analog video signal
`to the source signal lines $1 to Sx and a horizontal retrace
`line period may be one line period.
`
`[0025] Then, in a second line period (L2), the gate signal
`line G2 is selected by the gate signal. As in the case of the
`first line period (L1), an analog video signal is sequentially
`inputted to the source signal lines $1 to Sx.
`
`[0026] When the gate signal is inputted to all the gate
`signal lines G1 to Gy, all the line periods L1 to Ly end. When
`all the line periods L1 to Ly end, one frame period ends.
`During one frame period, all the pixels carry out display to
`form one image. It is to be noted that all the line periods L1
`to Ly plus a vertical retrace line period may be one frame
`period.
`
`[0027] As described above, the amount of light emitted by
`the EL elements 1806 is controlled according to the analog
`video signal. By controlling the amount of the emitted light,
`gradation display is carried out. This method is the so-called
`analog driving method, where gradation display is carried
`out by changing the potential of the analog video signal
`inputted to the source signal lines.
`
`[0028] The control of the amount of current supplied to the
`EL elements by the gate voltage of the TFTs for EL driving
`
`in the above-described analog driving method will be
`described in detail with reference to FIG. 28.
`
`[0029] FIG. 28A is a graph illustrating the transistor
`characteristics of the TFT for EL driving. Reference numeral
`2801 is referred to as IDS-VGS characteristics (or an IDS-VGS
`curve), wherein IDS is drain current and VGS is voltage
`between the gate electrode and the source region (gate
`voltage). By using this graph, the amount of current with
`regard to arbitrary gate voltage can be known.
`
`[0030] When gradation display is carried out in the analog
`driving method, a region indicated by a dotted line 2802 of
`the above-mentioned IDS-VGS characteristics is used to drive
`the EL element. FIG. 28B is an enlarged view of the region
`surrounded by the dotted line 2802.
`
`In FIG. 28B, 3 region illustrated by diagonal lines
`[0031]
`is referred to as a saturated region. More specifically, in the
`region, the gate voltage satisfies |VGS-VTH|<|VDS|, wherein
`VTH is threshold voltage. In this region, the drain current
`changes exponentially as the gate voltage changes. This
`region is used to perform current control by the gate voltage.
`
`[0032] When a TFT for switching is turned on, an analog
`video signal inputted to a pixel is gate voltage of a TFT for
`EL driving. Here, according to the IDS-VGS characteristics
`illustrated in FIG. 28A, drain current with regard to certain
`gate voltage is decided in a ratio of one to one. More
`specifically, correspondingly to the voltage of the analog
`video signal inputted to the gate electrode of the TFT for EL
`driving, the potential of the drain region is decided. Prede-
`termined drain current passes through the EL element, and
`the EL element emits light in an amount which corresponds
`to the amount of current.
`
`[0033] As described above, the amount of light emitted
`from the EL element is controlled by the video signal, and,
`by controlling the amount of light emission, gradation
`display is carried out.
`
`the above-described analog driving
`[0034] However,
`method has a defect in that it is easily affected by variation
`in the characteristics of the TFTs. Even in the case where
`
`equal gate voltage is applied to the TFTs for EL driving of
`the respective pixels, if there is variation in the IDS-VGS
`characteristics of the TFTs for EL driving, the same drain
`current can not be outputted. Further, as is clear from FIG.
`28A, since the saturated region where the drain current
`changes exponentially as the gate voltage changes is used, a
`slight shift
`in the IDS-VGS characteristics can result
`in
`considerable variation in the amount of outputted current
`even if equal gate voltage is applied. In this case, slight
`variation in the IDS-VGS characteristics results in consider-
`able difference in the amount of light emitted from the EL
`elements between adjacent pixels even if a signal of equal
`voltage is inputted thereto.
`
`In this way, analog driving is quite sensitive to
`[0035]
`variation in the characteristics of the TFTs for EL driving,
`which is an obstacle to gradation display by a conventional
`active matrix EL display.
`
`SUMMARY OF THE INVENTION
`
`[0036] The present invention is made in view of the above
`problem, and an object of the present invention is to provide
`an active matrix EL display capable of vivid color display
`
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`

`US 2002/0000576 A1
`
`Jan. 3, 2002
`
`having many tones. Another object of the present invention
`is to provide a high-performance display device (electronic
`apparatus) provided with such an active matrix EL display
`as a display.
`
`[0037] The inventor of the present invention thought that
`the problem with regard to the analog driving is attributable
`to gradation display performed by using the saturated
`region, which is easily affected by variation in the IDS-VGS
`characteristics since the drain current changes exponentially
`as the gate voltage changes.
`
`[0038] More specifically, in the case where there is varia-
`tion in the IDS-VGS characteristics, since, in the saturated
`region, the drain current changes exponentially as the gate
`voltage changes, different current (drain current) is output-
`ted even when equal gate voltage is applied. As a result,
`there is a problem that desired gradation can not be attained.
`
`[0039] Accordingly, the inventor of the present invention
`proposes a method where control of the amount of light
`emitted from EL elements is carried out not through control
`of current using the saturated region but mainly through
`control of time during which the EL elements emit light.
`According to the present invention,
`the amount of light
`emitted from the EL elements is controlled by time to carry
`out gradation display. Such a driving method where grada-
`tion display is carried out by controlling the light emission
`time of EL elements is referred to as a time-division driving
`method (hereinafter referred to as digital driving). It is to be
`noted that gradation display carried out by such a time-
`division driving method is referred to as time-division
`gradation display.
`
`[0040] By the above-mentioned structure, according to the
`present invention, even if there is variation in the IDS-VGS
`characteristics to some extent, a situation can be avoided that
`there is considerable difference in the amount of light
`emitted from the EL elements between adjacent pixels even
`if a signal of equal voltage is inputted thereto.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0041] FIG. 1 is a block diagram illustrating a circuit
`structure of an EL display according to the present invention.
`
`[0042] FIG. 2 is a circuit diagram of a pixel portion of the
`EL display according to the present invention.
`
`[0043] FIG. 3 is a circuit diagram of a pixel of the EL
`display according to the present invention.
`
`[0044] FIG. 4 illustrates a driving method of the EL
`display according to the present invention.
`
`[0045] FIG. 5 is timing charts of a selection signal in a
`driving method according to the present invention.
`
`[0046] FIG. 6 illustrates a driving method of an EL
`display according to the present invention.
`
`[0047] FIG. 7 illustrates a driving method of an EL
`display according to the present invention.
`
`[0048] FIG. 8 illustrates a driving method of an EL
`display according to the present invention.
`
`[0049] FIG. 9 is a plan view of pixels of an EL display
`according to the present invention.
`
`[0050] FIG. 10 is a block diagram illustrating the structure
`of a driver circuit of the EL display according to the present
`invention.
`
`[0051] FIG. 11 illustrates a manufacturing process of the
`EL display according to the present invention.
`
`[0052] FIG. 12 illustrates the manufacturing process of
`the EL display according to the present invention.
`
`[0053] FIG. 13 illustrates the manufacturing process of
`the EL display according to the present invention.
`
`[0054] FIG. 14 is a detailed sectional view of an EL
`display according to the present invention.
`
`[0055] FIG. 15 is a plan view and a sectional view of an
`EL display according to the present invention.
`
`[0056] FIG. 16 is a circuit diagram of a source signal line
`driver circuit of the EL display according to the present
`invention.
`
`[0057] FIG. 17 is a plan view of a latch of the source
`signal line driver circuit of the EL display according to the
`present invention.
`
`[0058] FIG. 18 is a circuit diagram of a gate signal line
`driver circuit of the EL display according to the present
`invention.
`
`[0059] FIG. 19 illustrates a structure of a connection
`between an EL element and a TFT for EL driving, and
`voltage-current characteristics of the EL element and of the
`TFT for EL driving.
`
`[0060] FIG. 20 illustrates voltage-current characteristics
`of an EL element and of a TFT for EL driving.
`
`[0061] FIG. 21 illustrates relationship between gate volt-
`age and drain current of a TFT for EL driving.
`
`[0062] FIG. 22 is a block diagram of a display according
`to the present invention.
`
`[0063] FIG. 23 is a plan view of a display with a driver
`circuit as a display according to the present invention.
`
`[0064] FIG. 24 illustrates electronic apparatus using the
`EL display according to the present invention.
`
`[0065] FIG. 25 illustrates electronic apparatus using the
`EL display according to the present invention.
`
`[0066] FIG. 26 is a circuit diagram of a pixel portion of a
`conventional EL display.
`
`[0067] FIG. 27 is a timing chart illustrating a driving
`method of the conventional EL display.
`
`[0068]
`TFT.
`
`FIG. 28 illustrates IDS-VGS characteristics of a
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`[0069] A structure and a driving method of an EL display
`according to the preset invention are described in the fol-
`lowing. Here, a case where 2n tones are displayed according
`to an n-bit digital video signal is described.
`
`[0070] FIG. 1 illustrates an exemplary block diagram of
`an EL display according to the present invention. The EL
`display illustrated in FIG. 1 has a pixel portion 101 formed
`
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`US 2002/0000576 A1
`
`Jan. 3, 2002
`
`of TFTs formed on a substrate, a source signal line driver
`circuit 102 disposed on the periphery of the pixel portion
`101, and a gate signal line driver circuit 103. It is to be noted
`that, though the EL display of the present embodiment has
`one source signal line driver circuit and one gate signal line
`driver circuit, the present invention is not limited thereto,
`and there may be two or more source signal line driver
`circuits and two or more gate signal line driver circuits.
`
`[0071] A clock signal for sources (S-CLK) and a start
`pulse signal for the sources (S-SP) are inputted to the source
`signal line driver circuit 102. The source signal line driver
`circuit 102 is driven by the clock signal for the sources
`(S-CLK) and the start pulse signal for the sources (S-SP).
`
`[0072] A clock signal for gates (G-CLK) and a start pulse
`signal for the gates (G-SP) are inputted to the gate signal line
`driver circuit 103. The gate signal line driver circuit 103 is
`driven by the clock signal for the gates (G-CLK) and the
`start pulse signal for the gates (G-SP).
`
`line
`the source signal
`invention,
`In the present
`[0073]
`driver circuit 102 and the gate signal line driver circuit 103
`may be provided on the substrate having the pixel portion
`101 provided thereon, or alternatively, may be provided on
`an IC chip and connected through an FPC or a TAB to the
`pixel portion 101.
`
`[0074] FIG. 2 is an enlarged view of the pixel portion 101.
`Source signal lines 81 to Sx, power supply lines V1 to Vx,
`and gate signal lines G0, G1 to Gy, and G(y+1) are provided
`in the pixel portion 101.
`
`[0075] A pixel 104 is a region having one of the source
`signal lines 81 to Sx, one of the power supply lines V1 to Vx,
`and one of the gate signal lines G1 to Gy. A plurality of
`pixels 104 are arranged like a matrix in the pixel portion 101.
`
`It is to be noted that, though no pixel is formed
`[0076]
`between the gate signal lines G0 and G1 in FIG. 2, the
`present invention is not limited thereto, and dummy pixels
`may be formed between the gate signal lines G0 and G1.
`
`[0077] FIG. 3 is a circuit diagram of the pixel 104.
`Reference numerals 105, 106, 107, 108, 109, and 110 denote
`a first TFT for switching, a second TFT for switching, a TFT
`for erasing, a TFT for EL driving, a capacitor, and an EL
`element, respectively. A pixel (j, i) illustrated in FIG. 3 has
`a source signal line Sj (j is an arbitrary number from 1 to x),
`a power supply line Vj, and a gate signal line Gi (i is an
`arbitrary number from 1 to y).
`
`[0078] A gate electrode of the first TFT 105 for switching
`is connected to the gate signal line Gi. A gate electrode of the
`second TFT 106 for switching is connected to a gate signal
`line G(i+1) of a pixel (j, i+1) located next to the pixel (j, i).
`It is to be noted that, though the present embodiment has the
`above-described structure, it may be that the gate electrode
`of the second TFT 106 for switching is connected to the gate
`signal line G1 and the gate electrode of the first TFT 105 for
`switching is connected to the gate signal line G(i+1) of the
`pixel (j, i+1) located next to the pixel (j, i).
`
`[0079] Asource region or drain region of the first TFT 105
`for switching and a source region or drain region of the
`second TFT 106 for switching are connected in series. The
`source region or drain region of the second TFT 106 for
`switching not connected to the source region or drain region
`of the first TFT 105 for switching is connected to the source
`
`signal line Sj. Further, the source region or drain regio