(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2004/0113873 A1
`(43) Pub. Date:
`Jun. 17, 2004
`Shirasaki et al.
`
`US 2004O113873A1
`
`(54)
`
`DISPLAY PANEL AND DISPLAY PANEL
`DRIVING METHOD
`
`(75)
`
`Inventors: Tomoyuki Shirasaki, Tokyo (JP);
`Hiroyasu Yamada, Tokyo (JP); Reiji
`Hattori, Fukuoka (JP)
`
`Correspondence Address:
`FRISHAUF, HOLTZ, GOODMAN & CHICK,
`PC
`767 THIRDAVENUE
`25TH FLOOR
`NEW YORK, NY 10017-2023 (US)
`
`Assignee: Casio Computer Co., Ltd., Tokyo 151
`8543 (JP)
`Appl. No.:
`10/472,423
`
`PCT Fed:
`
`Dec. 12, 2002
`
`PCT No.:
`
`PCT/JP02/13034
`
`
`
`(73)
`
`(21)
`(22)
`(86)
`
`(30)
`
`Foreign Application Priority Data
`
`Dec. 28, 2001 (JP)...................................... 2001-400557
`
`Publication Classification
`
`(51) Int. Cl." ....................................................... G09G 3/30
`(52) U.S. Cl. ................................................................ 345/76
`
`ABSTRACT
`(57)
`A display panel includes an optical element which has a pair
`of electrodes and exhibits an optical operation correspond
`ing to an electric current flowing between the electrodes, and
`a Switch circuit which Supplies a memory current having a
`predetermined current value to a current line during a
`Selection period, and Stops the Supply of the memory current
`to the current line during a non-Selection period. A current
`memory circuit Stores current data corresponding to the
`current value of the memory current flowing through the
`current line during the Selection period and, in accordance
`with the current data Stored during the Selection period,
`Supplies a display current having a current value Substan
`tially equal to the memory current to the optical element
`during the non-Selection period.
`
`CONTROLLER
`
`SELECTION
`SCAN
`DRIVER
`
`ERISSION
`WOLTAGE
`SCAN
`DRIVER
`
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`Patent Application Publication Jun. 17, 2004 Sheet 1 of 11
`
`US 2004/0113873 A1
`
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`Patent Application Publication Jun. 17, 2004 Sheet 2 of 11
`
`US 2004/0113873 A1
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`Patent Application Publication Jun. 17, 2004 Sheet 4 of 11
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`US 2004/0113873 A1
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`Patent Application Publication Jun. 17, 2004 Sheet 5 of 11
`
`US 2004/0113873 A1
`
`
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`Patent Application Publication Jun. 17, 2004 Sheet 6 of 11
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`US 2004/0113873 A1
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`

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`Patent Application Publication Jun. 17, 2004 Sheet 7 of 11
`
`US 2004/0113873 A1
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`Patent Application Publication Jun. 17, 2004 Sheet 8 of 11
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`US 2004/0113873 A1
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`
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`Patent Application Publication Jun. 17, 2004 Sheet 9 of 11
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`US 2004/0113873 A1
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`
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`Patent Application Publication Jun. 17, 2004 Sheet 10 of 11
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`US 2004/0113873 A1
`
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`
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`Patent Application Publication Jun. 17, 2004 Sheet 11 of 11
`
`US 2004/0113873 A1
`
`101
`
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`
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`(PRIOR ART)
`
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`US 2004/0113873 A1
`
`Jun. 17, 2004
`
`DISPLAY PANEL AND DISPLAY PANEL DRIVING
`METHOD
`
`TECHNICAL FIELD
`0001. The present invention relates to a display panel
`having an active driving type optical element and a method
`of driving the Same, and to a driving circuit and the like of,
`e.g., a light emitting element as the optical element.
`
`BACKGROUND ART
`0002. A light emitting element display is conventionally
`known in which light emitting elements Such as organic EL
`(electroluminescent) elements, inorganic EL elements, or
`light emitting diodes are arrayed in a matrix manner as
`optical elements, and the respective light emitting elements
`emit light to display an image. In particular, an active matrix
`driving type light emitting element display has advantages
`Such as high luminance, high contrast, high resolution, and
`low power consumption. Therefore, Such displays are devel
`oped in recent years, and particularly an organic EL element
`has attracted attention.
`0003. In some displays of this type, organic EL light
`emitting elements and a thin film transistor for driving this
`light emitting element by Switching are combined in one
`pixel. A plurality of Selection Scanlines parallel to each other
`are formed on a transparent Substrate. A plurality of Signal
`lines perpendicular to these Selection Scan lines are also
`formed on the Substrate. More specifically, two thin film
`transistors made of amorphous silicon (to be referred to as
`a-Si hereinafter) are formed in a region Surrounded by the
`Selection Scan lines and Signal lines, and one light emitting
`element is also formed in this region. That is, two transistors
`are formed in one pixel. The emission luminance (cd/m) of
`an organic EL element is determined by the value per unit
`area of an electric current flowing through the element.
`0004 FIG. 11 shows an equivalent circuit diagram of one
`pixel in a conventional light emitting element display. AS
`shown in FIG. 11, two transistors 103 and 104 are connected
`to a selection scan line 101 and signal line 102 per pixel. One
`and the other of the Source and drain electrodes of the
`transistor 104 are connected to an emission voltage line 106
`having a positive constant Voltage and to an anode of a light
`emitting element 105, respectively.
`0005. In this structure, when the selection scan line 101
`is selected (when the transistor 103 which is an N-channel
`transistor is turned on by applying a high-level Voltage to the
`Selection Scan line 101), a signal Voltage is applied from the
`signal line 102 to the gate electrode of the transistor 104 via
`the transistor 103. Accordingly, the transistor 104 is turned
`on, an electric current flows from the emission Voltage line
`106 to the light emitting element 105 via the transistor 104,
`and thus the light emitting element 105 emits light. When the
`Selection scan line 101 is unselected, the transistor 103 is
`turned off, and the Voltage of the gate electrode of the
`transistor 104 is held. An electric current flows from the light
`emission voltage line 106 to the light emitting element 105
`via the transistor 104, and the light emitting element 105
`emits light.
`0006. In the above structure, the magnitude of an electric
`current flowing between the drain and Source of the tran
`Sistor 104 is adjusted by adjusting the magnitude of the
`
`gate-Source Voltage of the transistor 104, i.e., the Voltage of
`the signal line 102. That is, the magnitude of the drain
`Source current of the transistor 104 is adjusted by using an
`unsaturated gate Voltage as the Voltage applied to the gate of
`the transistor 104, thereby adjusting the magnitude of the
`electric current flowing in the transistor 104 and light
`emitting element 105. Consequently, the luminance of the
`light emitting element 105 is adjusted, and tone display is
`performed. Between Selection and non-Selection after that,
`i.e., during one frame period, the gate-Source Voltage of the
`transistor 104 is substantially held constant, so the lumi
`nance of the light emitting element 105 is also held constant.
`This driving method is called a Voltage driving method by
`which the luminance tone is controlled by modulation of the
`output signal Voltage from the Signal line 102 to the tran
`Sistor 103.
`0007. The channel resistances of the transistors 103 and
`104 depend upon the ambient temperature and change after
`a long-term operation. Therefore, it is difficult to display
`images with a desired luminance tone for long time periods.
`Also, if the channel layers of the transistors 103 and 104 are
`made of polysilicon, the channel resistances depend upon
`the numbers of grain boundaries as the interfaces between
`adjacent crystal grains in these channel layers. This may
`vary the numbers of crystal grains in the channel layers of
`a plurality of transistors 103 and a plurality of transistors 104
`formed in a single panel. Especially when the grain size is
`increased to obtain high mobility, the number of grain
`boundaries in the channel layer inevitably decreases, So even
`a slight difference between the numbers of grain boundaries
`in the channel length direction has a large effect on the
`channel resistance. This varies the magnitudes of the drain
`Source currents of the transistors 104 in the individual pixels,
`resulting in variations in the display characteristics of the
`individual pixels in a Single panel. As a consequence, no
`accurate tone control can be performed. Accordingly, varia
`tions in the characteristics of the transistor 104 of each pixel
`must fall within a range required to control the tone of each
`pixel. However, as the resolution of an EL element
`increases, it becomes more difficult to make the character
`istics of the transistors 104 of the individual pixels uniform.
`0008 AS described above, in some active matrix driving
`EL elements, a plurality of transistors are combined as active
`elements formed in each pixel. In Some cases, a p-channel
`transistor and n-channel transistor are combined. When the
`characteristics of carriers are taken into consideration, a
`polysilicon transistor functions as a p-type transistor. When
`an amorphous Silicon transistor is used, however, good
`physical properties with which the transistor functions well
`cannot be obtained. This makes it impossible to apply
`amorphous Silicon transistors which can be fabricated at a
`relatively low cost.
`0009. Some of the active matrix EL display devices as
`described above are not voltage driven. In Some of these
`display devices, an active element is made up of four or
`more transistors in one pixel. If these transistors are formed
`on a Substrate, the upper Surface is made uneven by the
`thicknesses of these transistors. Therefore, an organic EL
`layer is desirably formed on a flat portion other than the
`transistor formation region. In this case, no light is emitted
`in this transistor formation region, So a non-light-emitting
`portion is inevitably formed in the pixel. When one pixel
`emits light with a predetermined tone luminance, the bright
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`US 2004/0113873 A1
`
`Jun. 17, 2004
`
`ness can be roughly set by (emission luminance per unit
`area)x(emission area of one pixel)x(emission time). How
`ever, when a large number of transistors are formed, the
`emission area of one pixel decreases. To compensate for this
`Small emission area, the emission luminance per unit area
`must be increased. Unfortunately, this shortens the light
`emission life because the organic EL layer is applied with a
`higher Voltage and current. In addition, when the number of
`transistors in one pixel increases, the fabrication yield low
`erS exponentially.
`0.010
`Also, if too many transistors are connected in series
`with an EL element in a pixel, the Voltage dividing ratio of
`these transistors rises. As a consequence, the power con
`Sumption is high.
`0011. Accordingly, one advantage of the present inven
`tion is that pixels Stably display images with desired lumi
`nance in a display panel.
`0012 Another advantage of the present invention is that
`the display area per pixel of a display panel is increased.
`
`DISCLOSURE OF INVENTION
`0013 To achieve the above advantages, a display panel
`according to one aspect of the present invention comprises:
`0014) one or more optical elements which have a
`pair of electrodes and exhibit an optical operation
`corresponding to an electric current flowing between
`the pair of electrodes;
`0015 one or more current lines;
`0016 one or more Switch circuits which supply a
`memory current having a predetermined current
`value to the current line during a Selection period,
`and Stop Supply of a current to the current line during
`a non-Selection period; and
`0017 one or more current memory circuits which
`Store current data corresponding to the current value
`of the memory current flowing through the current
`line during the Selection period and, in accordance
`with the current data Stored during the Selection
`period, Supply a display current having a current
`value Substantially equal to the memory current to
`the optical element during the non-Selection period.
`0.018. In the display panel having the above arrangement,
`the current memory circuit Stores the current data corre
`sponding to the current value of the memory current flowing
`during the Selection period. Accordingly, the display current
`having a current value Substantially equal to the memory
`current can be Supplied to the optical element. Current
`control is thus performed by the current values, not by
`Voltage values. This Suppresses the influence of variations in
`the Voltage-current characteristic of the control System and
`allows the optical element to Stably display images with
`desired luminance.
`0019. In each pixel, the current memory circuit has only
`one current control transistor connected in Series with the
`optical element. With this arrangement, the Voltage between
`the optical element and current memory circuit is divided
`only by the optical element and current control transistor.
`This achieves a low Voltage and consequently low power
`consumption driving.
`
`0020) Furthermore, each pixel can operate by using the
`three transistors, i.e., the current control transistor, current
`data write control transistor, and current path control tran
`Sistor. This decreases the number of transistors in one pixel
`and increases the area occupied by the optical element.
`Decreasing the number of transistors in one pixel also
`decreases a reduction in the fabrication yield. Additionally,
`when an EL element is used as the optical element, the ratio
`of the light emission area in the pixel can be increased, and
`the apparent brightness improves accordingly. Therefore, the
`value of an electric current flowing per unit area can be
`decreased to a relatively Small value. This Suppresses dete
`rioration of the EL element caused by an injection current.
`0021
`Even when a transistor is formed in the current
`memory circuit as described above, changes in the Voltage
`characteristic caused by deterioration of this transistor have
`no large influence Since the transistor is driven by current
`control. Consequently, a display current having an accurate
`current value can be Supplied.
`0022. A display panel driving method according to
`another aspect of the present invention comprises:
`0023 a current storage step of Supplying a memory
`current having a predetermined current value to a
`current memory circuit and Storing current data
`corresponding to the current value during a Selection
`period; and
`0024 a display step of Supplying, to an optical
`element during a non-Selection period, a display
`current having a current value Substantially equal to
`the memory current in accordance with the current
`data Stored in the current Storage Step.
`0025. In the present invention as described above, unlike
`in conventional devices, no preset Voltage value is written in
`a transistor, So no electric current having a current value
`corresponding to the Voltage value is Supplied to an optical
`element. As a consequence, a display current having an
`accurate current value can be Supplied.
`0026. Additional objects and advantages of the invention
`will be set forth in the description which follows, and in part
`will be obvious from the description, or may be learned by
`practice of the invention. The objects and advantages of the
`invention may be realized and obtained by means of the
`instrumentalities and combinations particularly pointed out
`hereinafter.
`
`BRIEF DESCRIPTION OF DRAWINGS
`0027. The accompanying drawings, which are incorpo
`rated in and constitute a part of the Specification, illustrate
`embodiments of the invention, and together with the general
`description given above and the detailed description of the
`embodiments given below, Serve to explain the principles of
`the invention.
`0028 FIG. 1 is block diagram showing a practical
`arrangement of a light emitting element display to which the
`present invention is applied;
`0029 FIG. 2 is a plan view schematically showing one
`pixel of the light emitting element display;
`0030 FIG. 3 is a sectional view showing a section taken
`along a line III-III in FIG. 2;
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`US 2004/0113873 A1
`
`Jun. 17, 2004
`
`FIG. 4 is a sectional view showing a transistor
`0.031
`surrounded by a line IV in FIG. 3;
`0.032
`FIG. 5A is an equivalent circuit diagram of the
`pixel of the light emitting element display, showing the
`driving principle in a selection period, and FIG. 5B is an
`equivalent circuit diagram of the pixel of the light emitting
`element display, showing the driving principle in a non
`Selection period;
`0.033
`FIG. 6 is a graph showing a relationship between
`an electric current flowing through an n-channel MOSFET
`connected in Series with a light emitting element of the light
`emitting element display, and a Voltage applied to this
`MOSFET;
`0034 FIG. 7 is a timing chart showing an operation of a
`driving circuit;
`0.035
`FIG. 8A is an equivalent circuit diagram of a pixel
`of another light emitting element display, showing the
`driving principle in a Selection period of the pixel of this
`light emitting element display, and FIG. 8B is an equivalent
`circuit diagram of the pixel of this light emitting element
`display, showing the driving principle in a non-Selection
`period;
`FIG. 9A is an equivalent circuit diagram of a pixel
`0.036
`of Still another light emitting element display, showing the
`driving principle in a Selection period of the pixel of this
`light emitting element display, and FIG.9B is an equivalent
`circuit diagram of the pixel of this light emitting element
`display, showing the driving principle in a non-Selection
`period;
`0037 FIG. 10A is an equivalent circuit diagram of a
`pixel of Still another light emitting element display, showing
`the driving principle in a Selection period of the pixel of this
`light emitting element display, and FIG. 10B is an equiva
`lent circuit diagram of the pixel of this light emitting element
`display, showing the driving principle in a non-Selection
`period; and
`0.038
`FIG. 11 is an equivalent circuit diagram showing
`the circuit configuration of one pixel of a conventional light
`emitting element display.
`
`BEST MODE FOR CARRYING OUT OF THE
`INVENTION
`Practical embodiments of the present invention
`0.039
`will be described below with reference to the accompanying
`drawings. However, the Scope of the invention is not limited
`to the illustrated embodiments.
`0040
`First Embodiment
`0041
`FIG. 1 is a block diagram showing a practical
`arrangement of a light emitting element display to which the
`present invention is applied. As shown in FIG. 1, the light
`emitting element display 1 includes, as its basic configura
`tion, an active matrix type light emitting panel (driver) 2 and
`a controller 6 for controlling the whole light emitting display
`1. The light emitting element display 1 is a So-called active
`matrix driving type display device. The light emitting panel
`2 includes a transparent substrate 30 (shown in FIG. 3)
`which is made of, e.g., borosilicate glass, Silica glass, and
`another glass which is resistant against temperatures during
`a transistor fabrication process (to be described later). Light
`
`emitting unit 7 is formed on the transparent Substrate 30, has
`a plurality of pixels and emits light So as to display an image
`corresponding to image data from the controller 6. A Selec
`tion Scan driver 3, emission Voltage Scan driver 4, and data
`driver 5 are formed on the transparent substrate 30 and drive
`the individual pixels of the light emitting unit 7. These
`Selection Scan driver 3, emission Voltage Scan driver 4, and
`data driver 5 are so connected as to be able to receive control
`Signals (pS, (pe, and (pd, respectively, and data from the
`controller 6. Various lines and elements are formed on the
`transparent Substrate 30 to construct the light emitting panel
`2.
`0042. In this light emitting panel 2, m selection scan lines
`X, X2, . . . , X are formed parallel to each other on the
`transparent Substrate 30. In addition, m emission Voltage
`Scan lines Z, Z, . . . , Z are formed on the transparent
`Substrate 30 So as to alternate with the selection Scan lines
`X, X2,..., X, respectively. These emission Voltage Scan
`lines Z, Z, . . . , Z are parallel to and Separated from the
`Selection Scan lines X, X2,..., X. Furthermore, current
`lines Y1, Y2,..., Y are formed on the transparent Substrate
`30 substantially perpendicularly to the selection scan lines
`X, X2,..., X and emission Voltage Scan lines Z, Z, . .
`., Z. The Selection Scan lines X1, X2, . . . , X, emission
`Voltage Scan lines Z, Z, . . . , Z, and current lines Y, Y,
`. . . , Y are made of chromium, chromium alloy, aluminum,
`aluminum alloy, titanium, titanium alloy, or a low-resistance
`material Selected from at least one of these materials. The
`Selection Scan lines X1, X2, . . . , X and emission Voltage
`Scan lines Z, Z, . . . , Z, can be formed by patterning the
`Same conductive film. The current lines Y1, Y2, ..., Y are
`formed to cross the Selection Scan lines X, X2,..., X and
`emission Voltage Scan lines Z, Z2, . . . , Z. The Selection
`Scan lines X1, X2,..., X and emission Voltage Scan lines
`Z, Z, ..., Z are insulated from the current lines Y1, Y2,
`. . . , Yby, e.g., a gate insulating film 32 or Semiconductor
`layer 33 (to be described later).
`0043 A plurality of organic EL elements ij are arrayed in
`a matrix manner on the transparent Substrate 30. One organic
`EL element is formed in each of the regions Surrounded by
`the current lines Y1, Y2, ..., Y and Selection Scan lines X,
`X,..., X. A driving circuit for Supplying a predetermined
`electric current to each organic EL element is formed around
`each organic EL element. One organic EL element and the
`driving circuit corresponding to this element form one pixel
`Pi of the light emitting unit 2. That is, one organic EL
`element is formed for each of (m X n) pixels.
`0044) Details of the light emitting unit 2 will be explained
`below. FIG. 2 is a plan view showing the major components
`of one pixel of this light emitting unit 2. FIG. 3 is a sectional
`view taken along line III in FIG. 2. FIG. 4 is a sectional
`view showing a region surrounded by a line IV in FIG. 3 in
`an enlarged scale. FIGS. 5A and 5B are equivalent circuit
`diagrams showing driving of two adjacent pixels P, and
`P. For better understanding of FIG. 2, a gate insulating
`film 32, first impurity doped layer 34, second impurity
`doped layer 35, block insulating film 36, cathode electrode
`43, and the like are at least partially omitted. In FIG. 3,
`hatching is partially omitted to make the drawing readily
`understandable.
`0045. The organic EL element E is formed in a region
`Surrounded by the selection scan line X, current line Y,
`
`IPR2020-01275
`Apple EX1004 Page 15
`
`

`

`US 2004/0113873 A1
`
`Jun. 17, 2004
`
`Selection Scan line X (i.e., a Selection Scan line positioned
`in the lower Stage of the Selection Scan line Xi, and posi
`tioned below the emission voltage Scan line Z, not shown),
`and current line Y (i.e., a signal line to the right of the
`current line Yi; not shown). Around this organic EL element
`E, a capacitor 13 and three transistors 10, 11, and 12 as
`n-channel amorphous Silicon thin film transistors are
`formed. A pixel driving circuit D, for driving the organic EL
`element E, includes the transistors 10, 11, and 12, capacitor
`13, and the like. Here, i is an integer from 1 to m, and j is
`an integer from 1 to n. That is, the “selection Scan line X,”
`means a Selection Scan line in the ith row, the "emission
`voltage Scan line Z, means an emission voltage Scan line in
`the ith row, and the “current line Y," means a signal line in
`the jth column. The “pixel driving circuit D," means a
`driving circuit of a pixel P, in the ith row and jth column,
`and the “organic EL element E" means an organic EL
`element of this pixel P. in the ith row and jth column. G, S,
`and D attached to reference numerals 10, 11, and 12 mean
`the gate, Source, and drain, respectively, of a transistor.
`0046. As shown in FIG. 4, the transistor 12 has a gate
`electrode (control terminal) 12G, a gate insulating film 32
`formed on the entire Surface of the light emitting unit 7, a
`Semiconductor layer 33 for forming a Single channel as a
`current path, a first impurity doped layer 34, a Second
`impurity doped layer 35, a block insulating film 36, a drain
`electrode 12D, a Source electrode 12S, and a protective
`insulating film 39. The gate electrode 12G is formed on the
`transparent Substrate 30. The gate electrode 12G is made of
`chromium, chromium alloy, aluminum, aluminum alloy,
`titanium, titanium alloy, or a low-resistance material
`Selected from at least one of these materials.
`0047 The gate insulating film 32 is formed on the gate
`electrode 12G and transparent substrate 30 so as to cover
`these gate electrode 12G and transparent substrate 30. The
`gate insulating film 32 is made of, e.g., Silicon nitride or
`Silicon oxide which transmits light and has insulating prop
`erties. The gate insulating film 32 also covers the gate
`electrodes of other transistors (all transistors formed on the
`transparent Substrate 30), the Selection Scan lines X, X-, ..
`.., X, and the emission Voltage Scan lines Z, Z2, . . . , Z
`0.048. The semiconductor layer 33 opposes the gate elec
`trode 12G via the part of the gate insulating film 32 (i.e., the
`semiconductor layer 33 is formed immediately above the
`gate electrode 12G). This semiconductor layer 33 is made of
`intrinsic amorphous Silicon. On this Semiconductor layer 33,
`the block insulating film 36 made of silicon nitride is
`formed. The first and second impurity doped layers 34 and
`35 are formed to be separated from each other on one and the
`other side portions of the block insulating film 36. The first
`impurity doped layer 34 covers one side portion of the
`semiconductor layer 33 and one side portion of the block
`insulating film 36. The second impurity doped layer 35
`covers the other side portion of the semiconductor layer 33
`and the other side portion of the block insulating film 36.
`These first and second doped layers 34 and 35 are made of
`amorphous Silicon doped with n-type impurity ions.
`0049. The drain electrode 12D is formed on the first
`impurity doped layer 34, and the source electrode 12S is
`formed on the second impurity doped layer 35. These drain
`electrode 12D and Source electrode 12S are made of chro
`mium, chromium alloy, aluminum, aluminum alloy, tita
`
`nium, titanium alloy, or a low-resistance material Selected
`from at least one of these materials, and have a function of
`blocking the transmission of visible light. This prevents the
`incidence of light from the outside or from the organic EL
`element E onto the semiconductor layer 33 and first and
`second impurity doped layers 34 and 35.
`0050. The source electrode 12S and drain electrode 12D
`are electrically insulated from each other. The Source elec
`trode 12S is electrically connected to an anode electrode 41
`(to be described later) of the EL element. The protective
`insulating film 39 covers the transistors 10, 11, and 12,
`capacitor 13, Selection Scan lines X1, X2, . . . , X, current
`lines Y, Y, . . . , Y, and emission voltage Scan lines Z,
`Z,..., Z, and exposes the anode electrode 41. That is, the
`protective insulating film 39 is so formed as to cover the
`Surroundings of the anode electrode 41 in a matrix manner.
`0051) The transistor 12 constructed as above is an MOS
`field-effect transistor having the semiconductor layer 33 as
`a channel region. Since the transistors 10 and 11 have
`Substantially the Same Structure as the transistor 12, a
`detailed description thereof will be omitted. One electrode of
`the capacitor 13 is the gate electrode 12G of the transistor
`12, and the other electrode of the capacitor 13 is the source
`electrode 12S of the transistor 12. Since the gate insulating
`film 32 formed between the two electrodes of the capacitor
`13 is made of a dielectric material, this capacitor 13 func
`tions as a capacitor in which current data corresponding to
`the value of an electric current flowing between the Source
`and drain of the transistor 12 is written. That is, the capacitor
`13 functions as a parasitic capacitance in the gate-to-Source
`path of the transistor 12 and Stores the written current data.
`The source 10S of the transistor 10 and the gate 12G of the
`transistor 12 are connected via a plurality of openings 47
`formed in the gate insulating film 32. The drain 12D of the
`transistor 12 is connected to one of the emission Voltage Scan
`lines Z, Z, . . . , Zvia a plurality of openings 48 formed
`in the gate insulating film 32.
`0052 To form the transistors 10, 11, and 12, capacitor 13,
`Selection Scan lines X1,X2,..., X, emission Voltage Scan
`lines Z, Z2, . . . , Z, and current lines Y1, Y2, . . . , Y a
`metal film deposited on the transparent substrate 30 is first
`patterned to form the gate electrodes of the transistors 10, 11,
`and 12, the Selection Scan lines X, X2,..., X, and the
`emission Voltage Scan lines Z, Z, . . . , Z in the Same Step.
`Subsequently, a gate insulating film 32 of the transistors 10,
`11, and 12 is formed on the entire Surface, and a Semicon
`ductor layer 33, block insulating film 36, and impurity doped
`layers 34 and 35 are formed in accordance with their
`respective shapes. After that, a metal film deposited on top
`of these components is patterned to form a Source electrode
`10S and drain electrode 10D of the transistor 10, a source
`electrode 11S and drain electrode 11D of the transistor 11, a
`Source electrode 12S and drain electrode 12D of the tran
`Sistor 12, and current lines Y1, Y2, ..., Y in the same Step.
`At the interSections of the current lines Y, Y-, ..., Y and
`Selection Scan lines X, X2,..., X and the intersections of
`the current lines Y1, Y2, . . . , Y and emission Voltage Scan
`lines Z, Z, .
`.
`. , Z, the block insulating film 36 is
`interposed in addition to the gate insulating film 32. After
`that, a protective insulating film 39 is formed by patterning.
`In this embodiment, a channel width W or channel length L
`of the semiconductor layer 33 of each of the three transistors
`
`IPR2020-01275
`Apple EX1004 Page 16
`
`

`

`US 2004/0113873 A1
`
`Jun. 17, 2004
`
`10, 11, and 12 is appropriately Set in accordance with the
`transistor characteristics of that transistor.
`0053) The protective insulating film 39 is covered with an
`insulating partition wall 46 made of, e.g., Silicon nitride
`(FIG. 3). The partition wall 46 has o