(12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY(PCT)
`
`(19) World Intellectual Property Organization
`International Bureau
`
`(43) International Publication Date
`25 September 2003 (25.09.2003)
`
`
`
`PCT
`
`(10) International Publication Number
`WO 03/079441 Al
`
`(51) International Patent Classification’:
`GO02F 1/1362
`
`HO1L 27/00,
`
`(NL). YOUNG, Nigel, D. [GB/NL]; Prof.
`NL-5656 AA Eindhoven (NL).
`
`Ilolstlaan 6,
`
`(74)
`Agent: WHITE, Andrew,G.; Internationaal Octrooibu-
`(21) International Application Number:=PCT/IB03/00699
`reau B.V., Prof. Holstlaan 6, NL-5656 AA Eindhoven
`(NL).
`
`(22) International Filing Date: 21 February 2003 (21.02.2003)
`
`(25) Filing Language:
`
`English
`
`(81)
`
`(26) Publication Language:
`
`English
`
`(30) Priority Data:
`0206551.4
`0209560.2
`0216057.0
`
`20 March 2002 (20.03.2002)
`26 April 2002 (26.04.2002)
`11 July 2002 (11.07.2002)
`
`GB
`GB
`GB
`
`(71) Applicant(for all designated States except US): KONIN-
`KLUKE PHILIPS ELECTRONICS N.V.
`[NL/NL];
`Groenewoudseweg 1, NL-5621 BA Eindhoven (NL).
`
`(84)
`
`(72) Inventors; and
`(75) Inventors/Applicants (for US only): CHILDS, Mark,
`J. [GB/NL]; Prof. Holstlaan 6, NL-5656 AA Eindhoven
`(NL). FISH, David, A. [GB/NL]; Prof. Holstlaan 6,
`NL-5656 AA Eindhoven (NL). HECTOR, Jason, R.
`[GB/NL]; Prof. Holstlaan 6, NL-5656 AA Eindhoven
`
`Designated States (national): AE, AG, AL, AM,AT, AU,
`AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU,
`CZ, DE, DK, DM, DZ, EC, EE, ES, FI, GB, GD, GE, GH,
`GM, HR, HU,ID,IL, IN,IS, JP, KE, KG, KP, KR, KZ, LC,
`LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW,
`MX, MZ, NO, NZ, OM,PH, PL, PT, RO, RU, SC, SD, SE,
`SG, SK, SL, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ,
`VC, VN, YU, ZA, ZM, ZW.
`
`Designated States (regional): ARIPO patent (GH, GM,
`KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW),
`Eurasian patent (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM),
`European patent (AT, BE, BG, CH, CY, CZ, DE, DK, LE,
`ES, FI, FR, GB, GR, HU,IE, IT, LU, MC, NL, PT, SE, SI,
`SK, TR), OAPI patent (BF, BJ, CF, CG, CI, CM, GA, GN,
`GQ, GW, ML, MR, NE, SN, TD, TG).
`
`Published:
`
`with international search report
`
`[Continued on next page]
`
`(54) Title: ACTIVE MATRIX DISPLAY DEVICES, AND THEIR MANUFACTURE
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`210
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`240
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`40
`
`+ 7 S95 (LED)
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`
`
`
`3/079441Al
`
`4512
`
` 140,160
`Tm
`
`(57) Abstract: Physical barriers (210) are present between neighbouring pixels (200) on a circuit substrate (100) ofan active-matrix
`display device, such as an clectroluminescent display formed with LEDs (25) of organic semiconductor materials. The invention
`formsat least parts of the barriers (210) with metal or other electrically-conductive material (240) that is insulated (40) from the
`LEDsbut connectedto the circuitry (4, 5, 6, 9, 140, 150, 160, T1, T2, Tm, Tg, Ch etc.) within the substrate (100). This conductive
`barrier material (240) may back up or replace, for example, matrix addressing lines (150) and/or form an additional componenteither
`within the pixel array or outside. The additional component comprising the conductive barrier material (240) is advantageously a
`capacitor (Ch), or an inductor (L) or transformer (W), or even an aerial.
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`__INITINMITUNITAIAT TTAATAA
`
`bor two-letter codes and other abbreviations, refer to the "Guid-
`ance Notes on Codes andAbbreviations" appearing at the begin-
`ning ofeach regular issue ofthe PCT Gazette.
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`DESCRIPTION
`
`ACTIVE MATRIX DISPLAY DEVICES, AND THEIR MANUFACTURE.
`
`This invention relates to active-matrix display devices, particularly but
`
`not exclusively electroluminescent displays using light-emitting diodes of
`
`semiconducting conjugated polymeror other organic semiconductor materials.
`
`The invention also relates to methods of manufacturing such devices.
`
`10
`
`Such active-matrix electroluminescent display devices are known,
`comprising an array of pixels present on a circuit substrate, wherein each pixel
`comprises an electroluminescent element, typically of organic semiconductor
`material. The electroluminescent elements are connected to circuitry in the
`
`substrate, for example drive circuitry that includes supply lines and matrix
`
`addressing circuitry that includes addressing (row) and signal (column)lines.
`
`These lines are generally formed bythin-film conductor layers in the substrate.
`
`The circuit substrate also includes addressing and drive elements (typically
`
`thin-film transistors, hereafter termed "TFT"s) for each pixel.
`
`In many such arrays, physical barriers of insulating material are present
`
`20
`
`between neighbouring pixels in at least one direction of the array. Examples
`
`of such barriers are given in published United Kingdom patent application
`
`GB-A-2 347017,
`
`published
`
`PCT patent
`
`application WO-A1-99/43031,
`
`published European patent applications EP-A-0 895 219, EP-A-1 096 568, and
`
`EP-A-1 102 317, the whole contents of which are hereby incorporated herein
`
`25
`
`‘as reference material.
`
`non
`Such barriers are sometimes termed "walls",
`
`"partitions", "banks", "ribs",
`
`"separators", or "dams",
`
`for example. As can be seen from the cited
`
`references,
`
`they may serve several
`
`functions.
`
`They may be used in
`
`30
`
`manufacture to define electroluminescent layers and/or electrode layers of the
`individual pixels and/or of columns of pixels. Thus, for example, the barriers
`prevent pixel overflow of conjugate polymer materials that may be ink-jet
`printed for red, green and blue pixels of a colour display or spin-coated for a
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`monochromedisplay. The barriers in the manufactured device can provide a
`
`well-defined optical separation of pixels. They may also carry or comprise
`
`the
`of
`electrode material
`upper
`as
`(such
`conductive material
`electroluminescent element), as auxiliary wiring for reducing the resistance of
`(and hence the voltage drops across) the common upperelectrode of the
`
`electroluminescent elements.
`
`Active-matrix liquid-crystal displays (AMLCDs) similarly comprise a
`
`circuit substrate on which an array of pixels is present.
`
`In the AMLCD case,
`
`upstanding spacers(pillars, for example) are present on the circuit substrate
`between at least some of the neighbouring pixels. These spacers support the
`
`overlying opposite plate of the display over the active-matrix circuit substrate to
`define the cell spacing in which the liquid crystal material is accommodated.
`
`the
`invention when applied to AMLCDs,
`the present
`For the purpose of
`spacers/pillars between pixels of an AMLCDwill be compared with the barriers
`between pixels of an active-matrix electroluminescent display (AMELD) and
`will be termed "barriers".
`
`10
`
`15
`
`It is an aim of the’ present invention to exploit, develop, adapt and/or
`
`extend particular features of active-mairix display devices, so as to permit
`
`20
`
`improvement and/or enhancement of the performance and/or capabilities of
`
`the device in a mannerthat is compatible with the basic device structure,its
`
`layout andits electronics.
`
`According to one aspect of the present invention, there is provided an
`active-matrix display device (for example an AMELD or an AMLCD)having the
`
`25
`
`features set out in Claim 1.
`
`In accordance with the invention, the physical barriers between pixels
`
`are used to provide connections into and/or out of the circuit substrate, and
`
`may provide additional components of the device.
`
`Thus, these pixel barriers are partly (possibly even predominantly) of
`
`30
`
`electrically-conductive material,
`
`typically metal.
`
`This conductive barrier
`
`material is connected with a circuit element within the circuit substrate, while
`
`also being insulated at least at the sides of the barriers adjacent to the pixel
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`3
`
`display elements. The said circuit element in the circuit substrate may take a
`variety of forms, depending on the particular improvement or enhancementor
`
`adaptation being made. Typically, it may be one or morethin-film elements of
`
`the group comprising: a conductor layer; an electrode connection; a supply
`
`line; an addressing line; a signal line; a thin-film transistor; a thin-film capacitor.
`
`Muchversatility is possible in accordance with the invention. Various
`
`structural features can be adopted for the pixel barriers. Thus, the conductive
`
`barrier material may extend as, for example, a line across the array, or it may
`
`be localised to, for example,
`
`individual pixels or groups of pixels or to other
`
`10
`
`device areas.
`
`Where the conductive barrier material
`
`is used to form an additional
`
`component, that component may be formedinside or outside the pixel array.
`
`As compared with connecting an external component, the integration of this
`additional component with pixel barrier technology can be used to enhance
`device performance at reduced cost and in compact areas within the display
`
`15
`
`device.
`
`At least some lengths of the conductive barrier material may simply
`
`serve as a back-up or even as a replacemeni for at least part of a thin-film
`
`conductorline of the circuit substrate, for example an address (row)line, a
`
`20
`
`signal (column)line or a supply line. Thus, the conductive barrier material may
`
`provide (or at least back up) the addressing lines (row conductors) over most
`
`of their length to reduce voliage drops along the addressing lines.
`
`In acase
`
`such as this,
`
`the barriers may be predominantly of conductive material
`
`(typically metal), or they may be predominantly of insulating material with a
`
`25
`
`conductive coating.
`
`Barrier structures used in accordance with the invention may be
`
`constructed with a metal core. This metal core can be usedin various ways.
`
`The metal core mayitself provide the conductive barrier material thatis
`
`30
`
`connected with the circuit element in the substrate.
`coating on atleast its sides.
`A metal coating can be provided on an insulating coating on the metal
`
`It may have an insulating
`
`core. This metal coating may be connected to anothercircuit element.
`
`In one
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`particularly useful form, the metal core, insulating coating and metal coating
`
`may together form a capacitor, for example an individual holding capacitor for
`
`each respective pixel.
`
`Thus,
`
`the pixel barriers may comprise separately
`
`insulated lengths, one or more of which may provide a capacitor having this
`
`metal-insulator coated barrier structure.
`
`However, the metal core does not need to be connected to a circuit
`
`element in the substrate. Thus, for example, when the barrier comprises a
`
`metal coating on an insulating coating on a metal core of the barrier, the metal
`
`coating may provide the conductive barrier material that is connected with the
`
`10
`
`circuit element in the substrate. The metal core may be, for example, a
`
`ferromagnetic core of an inductor or transformer that
`
`is integrated in this
`
`mannerinto the display device.
`
`Thus, the barriers may comprise separately insulated portions, one or
`
`more of which provide a capacitor, an inductor or a transformer having these
`
`15
`
`coated barrier structures. This separate capacitor or inductor or transformer
`
`length may be located within the pixel array, or it may be located outside the
`
`pixel array but still formed on the circuit substrate in the same process steps
`
`as the pixel barriers.
`Other separately insulated conductive portions of the barriers may serve
`different functions. They may be used, for example, to back-up or to replace
`
`20
`
`conductor lines of the circuit substrate and/or to form interconnections.
`
`Instead of using a metal core, a metal coating of the barrier may be
`
`used to provide the conductive barrier material that is connected with the
`
`circuit elementin the substrate.
`
`25
`
`According to another aspect of the present invention, there are also
`
`provided advantageous methods of manufacturing such an active-matrix
`
`display device.
`
`
`
`Various and_feature-combinations—inadvantageous features
`
`
`
`
`
`30
`
`accordance with the present invention are set out in the appended Claims.
`
`These and others areillustrated in embodiments of the invention that are now
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`described, by way of example, with reference to the accompanying
`
`diagrammatic drawings, in which:
`
`Figure 1
`
`is a circuit diagram for four pixel areas of an active-matrix
`
`electroluminescent display device which can be provided with conductive
`
`barrier material in accordance with the invention;
`
`Figure 2 is a cross-sectional view of part of the pixel array and circuit
`substrate of one embodiment of such a device, showing one example of a
`conductive barrier construction connected to a TFT source or drain line in
`
`accordancewith the invention;
`
`10
`
`Figure 3 is a cross-sectional view of part of the pixel array and circuit
`
`substrate of a similar embodiment of such a device, showing another example
`
`of a conductive barrier construction connected to a TFT gate line in
`
`accordancewith the invention;
`
`15
`
`20
`
`25
`
`Figure 4 is a circuit diagram, similar to that of Figure 1, but showing the
`use of pixel barriers with conductive barrier material to replace most of the
`addressing lines;
`.
`Figure 5 is a cross-sectional view through side-by-side barriers, each
`with conductive barrier material for a particular embodiment of a device in
`
`accordancewith the invention,
`
`Figure 6 is a plan view of four pixel areas showing a specific example of
`layout features for a particular embodiment of a device in accordance with the
`invention, with side-by-side conductive barriers,
`for example, with the
`cross-sectional view of Figure 5 taken on theline V-V of Figure 6;
`Figure 7 is a plan view of another example of layout features for a
`particular embodiment of a device in accordance with the invention, with
`
`transverse conductive barriers;
`Figure 8 is a sectional view of a device part with yet another example of
`
`a conductive barrier construction using a metal coating in accordance with the
`
`invention;
`
`30
`
`Figure 9 is a cross-sectional view of a conductive barrier construction
`that additionally includes a metal coating to form a capacitor embodimentin
`
`accordance with the invention;
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`6
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`Figure 10 is a plan view of transverse barrier layout features suitable for
`a device having such a capacitor embodiment
`in accordance with the
`
`invention;
`
`Figure 11 is a cross-sectional view of a conductive barrier construction
`in an inductor embodimentin accordance with the invention;
`
`Figure 12 is a plan view of layout features suitable for such an inductor
`
`embodiment;
`
`Figure 13 is a plan view of layout features suitable for a transformer
`
`embodiment, having a cross-section similar to that of Figure 12;
`
`10
`
`Figures 14 to 16 are sectional views of a device part such as that of
`
`Figure 2 or Figure 3 at stages in its manufacture with one particular
`
`embodimentin accordance with the invention; and
`Figure 17 is a sectional view a device part at the Figure 16 stage,
`illustrating a modification in the insulation of the conductive barrier material
`
`15
`
`that is also in accordance with the present invention.
`
`It should be noted that all the Figures are diagrammatic. Relative
`
`dimensions and proportions of parts of these Figures have been shown
`exaggerated or reducedin size, for the sake of clarity and conveniencein the
`
`drawings.
`
`The same reference signs are generally used to refer
`
`to
`
`20
`
`corresponding orsimilar features in modified and different embodiments.
`
`Embodiments of Figures 1 to 3
`
`The active-matrix electroluminescent display (AMELD)device of each of
`
`the Figures 1 to 3 embodiments comprises an array of pixels 200 onacircuit
`
`25
`
`substrate 100 with matrix addressing circuitry.
`
`Physical barriers 210 are
`
`present between at least some of the neighbouring pixels in at least one
`
`direction of the array. At least someof these barriers 210 are constructed with
`
`conductive barrier material 240 that
`
`is used as an interconnection in
`
`accordance with the present invention. Apart from this special construction
`
`30
`
`and use of the barriers 210 in accordance with the present invention, the
`
`display may be constructed using known device technologies and circuit
`
`technologies, for example as in the background referencescited hereinbefore.
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`The matrix addressing circuitry comprises transverse sets of addressing
`
`(row) and signal (column) lines 150 and 160, respectively, as illustrated in
`
`Figure 1. An addressing element T2 (typically a thin-film transistor, hereafter
`
`termed "TFT") is incorporated at each interception of these lines 150 and 160.
`
`Figure 1 depicts, by way of example, one specific pixel circuit configuration.
`Other pixel circuit configurations are known for active matrix display devices,
`
`and it should readily be understood that the present invention may be applied
`
`to the pixel barriers of such a device regardless of the specific pixel circuit
`
`configuration of the device.
`
`10
`
`Each pixel 200 comprises a current-driven electroluminescent display
`
`element 25 (21,22,23),
`
`typically a light-emitting diode (LED) of organic
`
`semiconductor material. The LED 25 is connected in series with a drive
`
`element T1 (typically a TFT) between two voltage supply lines 140 and 230 of
`
`the array. These two supply lines are typically a power supply line 140 (with
`
`voltage Vdd) and a groundline 230 (also termed "return line"). Light emission
`
`from the LED 25 is controlled by the current flow through the LED 25, as
`altered byits respective drive TFT 11.
`Eachrow of pixels is addressed in turn in a frame period by meansof a
`
`selection signal that is applied to the relevant row conductor 150 (and henceto
`
`20
`
`the gate of the addressing TFTs T2 of the pixels of that row). This signal turns
`
`on the addressing TFT T2, so loading the pixels of that row with respective
`
`data signals from the column conductors 160. These data signals are applied
`
`25
`
`to the gate of the individual drive TFT T1 of the respective pixel.
`In order to
`hold the resulting conductive state of the drive TFT 11, this data signal is
`maintained onits gate 5 by a holding capacitor Ch that is coupled betweenthis
`gate 5 and thedrive line 140,240. Thus, the drive current through the LED 25
`of each pixel 200 is controlled by the driving TFT T1 based onadrive signal
`applied during the preceding address period and stored as a voltage on the
`associated capacitor Ch.
`In the specific example of Figure 1, T1 is shown as a
`
`30
`
`P-channel TFT, whereas T2 is shown as an N-channel TFT.
`
`This circuitry can be constructed with known thin-film technology. The
`
`subsirate 100 may have aninsulating glass base 10 on which an insulating
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`surface-buffer layer 11, for example, of silicon dioxide is deposited. The
`
`thin-film circuitry is built up on the layer 11 in known manner
`
`Figures 2 and 3 show TFT examples Tm and Tg, each comprising: an
`
`active semiconductor layer 1 (typically of polysilicon); a gate dielectric layer 2
`
`(typically of silicon dioxide); a gate electrode 5 (typically of aluminium or
`
`polysilicon); and metal electrodes 3 and 4 (typically of aluminium) which
`
`contact doped source and drain regions of the semiconductor layer 1 through
`windows(vias) in the over-lying insulating layer(s) 2 and 8. Extensions of the
`
`electrodes 3, 4 and 5 mayform, for example, interconnections between the
`
`10
`
`elements T1, T2, Ch and LED 25, and/or at least part of the conductorlines
`
`140, 150 and 160, depending onthe circuit function provided by the particular
`
`TFT (for example, the drive element T1 or the addressing element T2 or
`
`another TFT of the circuit substrate). The holding capacitor Ch may be formed
`similarly, in known manner, asathin-film structure inside the circuit substrate
`100.
`
`The LED 25 typically comprises a light-emitting organic semiconductor
`
`material 22 between a lower electrode 21 and an upper electrode 23.
`
`Ina
`
`preferred particular embodiment, semiconducting conjugated polymers may be
`used for the electroluminescent material 22. For a LED that emitsits light 250
`through the substrate 100, the lower electrode 21 may be an anode of indium
`
`20
`
`tin oxide (ITO), and the upper electrode 23 may be a cathode comprising, for
`example, calcium and aluminium.
`Figures 2 and 3 illustrate a LED
`
`consiruction in which the lower electrode 21 is formed as a thin film in the
`
`circuit substrate 100. The subsequently-deposited organic semiconductor
`
`25
`
`material 22 contacts this thin-film electrode layer 21at a window 12a in a
`
`planarinsulating layer 12 (for example ofsilicon nitride) that extends over the
`thin-film structure of the substrate 100.
`
`As in known devices, the devices of Figures 1
`to 4 in accordance with
`the present invention include physical barriers 210, between at least someof
`the neighbouring pixels in at least one direction of the array. These barriers
`210 may also be termed "walls", "partitions", "banks", "ribs", "separators", or
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`"dams", for example. Depending on the particular device embodimentandits
`
`manufacture, they may be used in known manner,for example:
`
`e
`
`to separate and prevent overflow of a polymer solution between the
`
`respective areasofthe individual pixels 200 and/or columnsof pixels
`200, during the provision of semiconducting polymerlayers 22;
`to provide a self-patterning ability on the substrate surface in the
`
`e
`
`definition of the semiconducting polymer or other electroluminescent
`
`layers 22 for the individual pixels 200 and/or for columns of pixels
`
`200 (and possibly even a self-separation of individual electrodes for
`
`10
`
`the pixels,
`
`for example an individual bottom layer of the upper
`
`electrodes 23);
`
`e
`
`to act as a spacer for a mask over the substrate surface during the
`
`deposition of at least an organic semiconductor material 22 and/or
`
`electrode material;
`
`15
`
`e
`
`to form opaquebarriers 210 for a well-defined optical separation of
`
`the pixels 200 in the array, whenlight 250 is emitted through the top
`
`(instead of, or as well as, the bottom substrate 100).
`least some
`Whatever their specific use in these known ways, at
`insulated lengths of the physical barriers 210 in embodiments of the present
`
`20
`
`invention are constructed and used in a special manner. Thus, the pixel
`
`barriers 210 of Figures 2 to 4 comprise metal 240 (or other elecirically-
`
`conductive material 240) that is insulated at their sides adjacent the LEDs 25
`
`and that are connected to and/or from one or morecircuit elements of the
`
`circuit substrate 100.
`
`This circuit element may take a variety of forms,
`
`25
`
`depending on the particular improvement or enhancement or adaptation being
`
`made. Typically,
`
`it may be one or more thin-film elements of the group
`
`comprising: a conductor layer and/or an electrode connection 4, 5, 6; a supply
`
`line 140; an addressing line 150; a signal line 160; a thin-film transistor T1, T2,
`
`Tm, Tg; a thin-film capacitor Ch.
`
`30
`
`In the embodiment of Figure 2, the circuit element connected to the
`
`conductive barrier material 240 is an extension of the source and/or drain
`
`electrode of TFT Tm.
`
`It may form a signal (column)line 160, for example, of
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`PCT/IB03/00699
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`10
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`In
`the substrate circuitry when Tm is T2, or a drive line 140 when Tmis T1.
`the embodiment of Figure 3, the circuit element connected to the conductive
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`barrier material 240 is an extension of the gate electrode 5 of TFT Tg.
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`It may
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`form an addressing (row) line 150, for example, of the substrate circuitry when
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`Tg is T2.
`The pixel barriers 210 in the embodiments of Figures 2 to 4 are
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`predominantly of electrically-conductive material 240, 240x, preferably metal
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`for very low resistivity (for example aluminium or copper or nickel or silver).
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`The barriers 210 of Figures 2 and 3 comprise a bulk or core of the conductive
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`material that has an insulating coating 40 onits sides and onits top.
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`As shownin Figures 2 and 3, the bottom connections of the conductive
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`barrier material 240 to the circuit element 4,5 occur at connection windows 12b
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`in the intermediate insulating layer 12. However, it should be understood that
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`these windows 12b may often not be in the same plane as the TFT Tm, Tg.
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`In
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`particular, there is generally insufficient space between the source and drain
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`electrodes 3 and 4 of TFT Tg to accommodate a window 12b. Thus, the
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`window 12b is depicted in broken outline in Figure 3 to indicate its location
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`outside the plane of the drawing paper.
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`20
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`Addressing Line Barrier Embodiment of Figure 4
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`The conductive barrier material 240 connected to a TFT gateline (asin
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`Figure 3, for example) may provide at least part of the addressing (row)lines
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`150. One such embodimentisillustrated in Figure 4, wherein mostofthe line
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`150 is formed by the conductive barrier material 240.
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`25
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`Line resistance can be significantly reduced by using the conductive
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`barrier material 240 to replace or to back up the conduciorline 150 of the
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`circuit substrate 10. Thus, along the line 240(150), the conductive barrier
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`material 240 has a cross-sectional area that is at least twice (possibly even an
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`30
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`order of magnitude)
`larger than that of the conductor layer that
`typically
`provides a gate line 5(150) of TFT Tg in the circuit substrate 100. Typically,
`the conductive barrier material 240 may have a thicknessZ that is a factor of
`two or more (for example at least five times) larger than the thickness z of this
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`11
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`In a specific example Z
`conductor layer 5(150) in the circuit substrate 100.
`may be between 2um and 5yum as compared with 0.5ym or less for z.
`Typically, the conductive barrier material 240 may havealine width Y thatis
`the same width (or even at least twice as large) as the line width y of the
`conductorlayer 140.
`In a specific example Y may be 20um as compared with
`10m for y. Furthermore, the gate line 5(150) is typically of doped polysilicon,
`whereas the conductive barrier material 240 is typically metal having a much
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`higher conductivity.
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`Multi-conductor Barrier Embodiments of Figures 5 and 6
`Figure 5 illustrates a composite of two side-by-side barriers 210 and
`210x, each comprising a metal core 240, 240x insulated with a respective
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`coating 40, 40x. This side-by-side multi-conductor barrier structure 210,21x
`can be designed and usedin a variety of ways.
`In one form, for example, the
`metal cores 240 and 240x may form (or back up) parallel addressing and
`supply lines 150 and 140 respectively.
`In another form, for example,' one of
`the barriers 210 may be divided into insulated portions that provide an
`additional component,
`for example a capacitor as described below with
`reference to Figure 9 and 10. Figure 6 gives one example of a suitable pixel
`layout,
`in which the matrix thin-film circuit area of
`the substrate 100 is
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`designated as 120.
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`Modified Multi-conductor Barrier Layout Embodiment of Figure 7
`In the modified layout of Figure 7, the two barriers 210 and 210x (each
`comprising a metal core 240, 240x insulated with a respective coating 40, 40x)
`are arranged transverse to each other.
`In this case, barrier 210x (with
`connections to substrate TFT Tm as T2) may be used to back up or replace
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`the column lines 160. The barrier 210 (with connections to substrate TFT Tg
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`as T2) may be usedto back up or replace the row lines 150. Alternatively, the
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`20
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`25
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`30
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`barrier 210 (with connections to substrate TFT Tm as T1) may be used to back
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`up or replace the supply lines 140.
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`12
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`Alternative Conductive Barrier Embodiment of Figure 8
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`In the embodiments of Figures 2, 3, and Figure 5, barriers 210 and 210x
`are shown as being predominantly of conductive material 240 and 240x.
`Figure 8 shows a modified embodiment wherein the barrier 210 is
`predominantly of insulating material 244.
`In this case, vias 244b are etched or —
`milled through the insulating material 244 to the circuit element 4, 5 in the
`circuit substrate 100. A metal coating 240 provides the conductive barrier
`material that extends on top of the insulating barrier 210 andin the vias 244b
`therethrough.
`This alternative conductive barrier construction is particularly
`suitable for embodiments in which the conductive barrier material 240 backs
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`up or replacesthin-film conductorlines (such aslines 140, 150 and 160) of the
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`circuit substrate 100.
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`The metal coating 240 of this barrier 210 may be formed simultaneously
`with a main part 23a of the upper electrode 23 of the LED 25, in a self-aligned
`manner. Thus, a layer of metal may be deposited simultaneously for the metal
`coating 240 and electrode 23 which are separated by a shadow-masking effect
`of an overhang shapein the side of the barrier 210, asillustrated in Figure 12.
`This is one possible process embodiment for forming barrier interconnects
`210, 240 in accordance with the present invention. Figures 15 to 17 illustrate
`other process embodiments for barrier
`interconnects 210, 240 that are
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`predominantly of metal.
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`Capacitor and other multi-conductor barrier embodiments of Figures 9 and 10
`The Figure 9 embodimentis similar to those of Figures 2, 3, and 5, in
`having insulated lengths of the barrier 210 that comprise a metal core 240 as
`the main conductive barrier material. This metal core 240 is connected with
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`the circuit element 4 or 5 etc.
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`in the substrate 100 and has aninsulating
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`coating 40 on thereon.
`However the embodiment of Figure 9 additionally comprises a metal
`coating 240c that is present on the insulating coating 40, over the top and
`sides of the core 240. This metal coating 240c is connected to another circuit
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`15
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`20
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`25
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`30
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`13
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`element of, for example,
`another TFT.
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`the substrate 100 such as element 5,4, etc. of
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`This structure of Figure 9 is more versatile than that of Figures 2, 3 and
`It permits the metal core 240 and metal coating 240c to be used for
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`5.
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`different purposes, for example, to back-up or even replace the lines 140, 150
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`or 160, so reducingtheir line resistance. The metal coating 240c may serve as
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`a co-axial shield for the signal on the core line 240. Alternatively, the metal
`coating 240c maybelocalised to specific locations along the barrier 210 where
`particular connections or components are required, for example at individual
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`10
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`pixels or sub-pixels.
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`Instead of shielding,
`this multi-conductor structure 240, 240c for the
`barrier 210c might be used to overlap twolines; for example, a back-up or
`replacement barrier
`line 140 (including core 240) with a back-up or
`replacement barrier line 150 (including coating 240c).
`In this case, however,
`the thickness anddielectric properties of the insulating coating 40 need to be
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`chosen to reduce parasitic capacitance and coupling between these lines 140
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`and 150.
`Of particular importance is an embodimentin which the multi-conductor
`structure 240, 240c of Figure 9 is designed to form a capacitor C with a
`capacitor dielectric 40. Thus, separate and/or insulated lengths of the metal
`core 240, insulating coating 40 and metal coating 240c may together form a
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`20
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`capacitor C connected between the substrate circuit elements 4, 5, etc.
`Such a capacitor may be, for example, the individual holding capacitor
`Ch for each respective pixel 200 which is connected betweenthe supply line
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`25
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`140 (main electrode line 4 of TFT T1, Tm) and the gate line 5 of TFT T2, Tg
`(and main electrode line 3 of TFT T1, Tm).
`Figure 10 illustrates a suitable
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`pixel layout with this holding capacitor barrier 210c, Ch.
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`Inductor and other multi-metal barrier embodiments of Figures 11 to 13
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`30
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`Figures 11 to 13 illustrate barrier embodiments 210d with a metal core
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`240m that is not electrically connected to a circuit element of the device.
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`In
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`this case the conductive barrier material 240 connected to the thin-film
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`WO 03/079