`FOR THE WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`W-20-CV-00562-ADA
`
`§§
`
`
`§
`§
`§
`§
`§
`
`PARKERVISION, INC.,
`Plaintiff
`
`-v-
`INTEL CORPORATION,
`Defendant
`
`CLAIM CONSTRUCTION ORDER
`
`The Court held a Markman hearing on June 24, 2021 and July 22, 2021 . During those
`
`hearings, the Court provided its final constructions. The Court now enters those claim
`
`constructions.
`
`SIGNED this 22nd day of July, 2021.
`
`ALAN D ALBRIGHT
`UNITED STATES DISTRICT JUDGE
`
`Intel v. ParkerVision
`IPR2020-01265
`Intel 1038
`
`Page 1 of 16
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`
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`independent control input”
`a circuit as dictated by an
`device for opening and closing
`meaning is “an electronic
`wherein the plain-and-ordinary
`Plain-and-ordinary meaning
`
`
`
`driving a low impedance load”
`electromagnetic signal for
`energy from an input
`non-negligible amounts of
`transfer system that stores
`“a module of an energy
`
`
`
`the input signal”
`equal to twice the frequency of
`or “sampling at less than or
`“sampling at an aliasing rate”
`
`
`
`Court’s Final Construction
`
`opening and closing a circuit”
`“an electronic device for
`
`
`
`time in duration”
`widths) that tend towards zero
`negligible apertures (i.e., pulse
`the input signal using
`equal to twice the frequency of
`“sample[s/ing] at less than or
`
`Defendants’ Proposed
`
`Construction
`
`
`
`(EM) signal”
`from an input electromagnetic
`negligible amount of energy
`“a module that stores a non-
`
`
`
`driving a low impedance load”
`electromagnetic signal for
`energy from an input
`non-negligible amounts of
`transfer system that stores
`“a module of an energy
`
`control input”
`as dictated by an independent
`opening and closing a circuit
`“an electronic device for
`
`
`
`
`
`the input signal”
`equal to twice the frequency of
`or “sampling at less than or
`“sampling at an aliasing rate”
`
`Plaintiff’s Proposed
`
`Construction
`
`
`
`175, 186; ’108 patent, claim 1
`’706 patent, claims 105, 164,
`
`
`
`“switch”
`
`
`
`164, 175, 179, 186, 190
`’706 patent, claims 105, 114,
`
`
`
`
`
`7, 28, 34
`’706 patent, claims 1, 6,
`
`sampling”
`“undersamples” / “under-
`“under-sample” /
`
`
`
`Term
`
`
`
`“storage module”
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`Page 2 of 16
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`
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`Plain-and-ordinary meaning.
`Not subject to § 112, ¶ 6.
`
`
`
`Plain-and-ordinary meaning.
`Not subject to § 112, ¶ 6.
`
`Court’s Final Construction
`
`and equivalents thereof
`the capacitors 2652 and 2656;
`switches 2650 and 2654, and
`and 28:2041, that includes the
`26 and described at 26:1-27:21
`and delay module 2624 in Fig.
`Structure: the down convert
`
`sample
`signal, and to delay said input
`converted image of said input
`input sample of a down-
`control signal to produce an
`input signal according to a
`Function: under-sample an
`
`Defendants’ Proposed
`
`Construction
`
`
`
`
`
`and equivalents thereof.
`the capacitors 2652 and 2656;
`switches 2650 and 2654, and
`and 28:2041, that includes the
`26 and described at 26:1-27:21
`and delay module 2624 in Fig.
`Structure: the down convert
`
`
`
`
`
`said sample
`control signal, and to delay
`an input signal according to a
`of a down-converted image of
`Function: produce a sample
`
`Plain and ordinary meaning
`
`
`
`Plain and ordinary meaning
`
`Plaintiff’s Proposed
`
`Construction
`
`
`
`sample”
`signal, and to delay said
`converted image of an input
`produce a sample of a down-
`“a frequency translator to
`
`’706 patent, claim 34
`
`
`
`
`
`sample”
`signal, and to delay said input
`converted image of said input
`input sample of a down-
`input signal to produce an
`module to under-sample an
`“a down-convert and delay
`
`’706 patent, claims 1, 7
`
`
`
`
`
`Term
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`Page 3 of 16
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`
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`Plain-and-ordinary meaning.
`Not subject to § 112, ¶ 6.
`
`
`
`Plain-and-ordinary meaning
`
`
`
`Court’s Final Construction
`
`samples
`and downconverted input
`one or more of said delayed
`an output signal / further delay
`Function: delay instances of
`
`
`
`equivalents thereof.
`described at 35:19-27; or
`inductors and/or resistors
`combination of capacitors,
`an analog delay line having a
`described at 32:44-33:19; or
`4501 and 4503 in Fig. 45 and
`the sample and hold circuit
`32 and described at 35:1-18;
`module 3204” shown in Fig.
`shown in Fig 26, “delay
`“second delay module 2630”
`“first delay module 2628,”
`Structure: structure including
`
`
`
`has been down-converted”
`“the sample of the image that
`
`Defendants’ Proposed
`
`Construction
`
`
`
`Plain and ordinary meaning
`
`
`
`Plain and ordinary meaning
`
`Plaintiff’s Proposed
`
`Construction
`
`
`
`input samples”
`delayed and down-converted
`delay one or more of said
`“delay modules to further
`instances of an output signal”,
`“delay module to delay
`
`140
`’706 patent, claims 1, 7, 34,
`
`
`
`
`
`’706 patent, claims 1, 6, 7, 34
`
`sample”
`“said input sample”, “said
`
`
`
`
`
`Term
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`Page 4 of 16
`
`
`
`ordinary meaning.
`Not indefinite. Plain-and-
`
`as the first harmonic”
`the fundamental frequency
`waveform and including
`frequency of the periodic
`of the fundamental
`that is an integer multiple
`wave that has a frequency
`component of a periodic
`(cid:120) Harmonic: “A sinusoidal
`Plain-and-ordinary meanings:
`
`(cid:120) Harmonics: “A frequency
`
`harmonic”
`frequency as the first
`including the fundamental
`integer multiple of it and
`frequency or tone, is an
`fundamental or reference
`compared to its
`or tone that, when
`
`Court’s Final Construction
`
`
`
`
`
`Indefinite
`
`
`
`transfer
`negligible apertures for energy
`or Pulse widths that use non-
`Plain and ordinary meaning,
`
`
`
`transfer”
`established to improve energy
`“pulse widths that are
`
`’706 patent, claim 2
`
`
`
`
`
`wave”
`frequency of the periodic
`multiple of the fundamental
`frequency that is an integer
`each of which have a
`components of a periodic wave
`Harmonics: “Sinusoidal
`
`periodic wave”
`fundamental frequency of the
`integer multiple of the
`that has a frequency that is an
`component of a periodic wave
`Harmonic: “A sinusoidal
`
`Defendants’ Proposed
`
`Construction
`
`
`
`first harmonic”
`fundamental frequency as the
`multiple of it and including the
`frequency or tone, is an integer
`its fundamental or reference
`tone that, when compared to
`Harmonics: “A frequency or
`
`harmonic”
`frequency as the first
`including the fundamental
`periodic waveform and
`fundamental frequency of the
`integer multiple of the
`that has a frequency that is an
`component of a periodic wave
`Harmonic: “A sinusoidal
`
`Plaintiff’s Proposed
`
`Construction
`
`
`
`
`
`34; ’508 patent, claim 1
`’706 patent, claims 1, 6, 7, 28,
`
`“harmonic”, “harmonics”
`
`
`
`
`
`Term
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`Page 5 of 16
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`
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`26.
`capacitor 2656 shown in Fig.
`Structure: switch 2654 and
`
`
`
`sample
`Function: delaying said input
`
`
`
`
`
`Subject to § 112, ¶ 6.
`
`thereof.
`53A/53A-1, and equivalents
`capacitor 5310 in Figs.
`26 the switch 5308 and
`and the capacitor 2652 in Fig.
`Structure: the switch 2650
`
`
`
`control signal
`input signal according to a
`signal and under-sampling the
`converted image of said input
`input sample of a down-
`input signal to produce an
`Function: under-sampling an
`
`Subject to § 112, ¶ 6.
`
`
`
`Court’s Final Construction
`
`
`
`equivalents thereof.
`described at 28:52-56 and
`5310 in Fig. 53A-1 and
`switch 5308 and capacitor
`described at 28:46-47; the
`capacitor 5310 in Fig. 53A and
`28; the switch 5308 and
`27:21, 28:20-28, and 39:25-
`26 and described at 26:1-
`and the capacitor 2652 in Fig.
`Structure: the switch 2650
`
`control signal
`input signal according to a
`signal and under-sampling the
`converted image of said input
`input sample of a down-
`input signal to produce an
`Function: under-sampling an
`
`Defendants’ Proposed
`
`Construction
`
`
`
`
`
`sample
`Function: delaying said input
`
`equivalents thereof.
`27:21 and 28:2028; and
`Fig. 26 and described at 25:57-
`and capacitor 2656 shown in
`Structure: the switch 2654
`
`
`
`
`
`equivalents thereof
`Figs. 53A/53A1; and
`Fig. 26 or capacitor 5310 in
`Structure: capacitor 2656 in
`
`image of said input signal
`sample of a down-converted
`Function: delaying the input
`
`
`
`
`
`control signal
`input signal according to a
`signal and under-sampling the
`converted image of the input
`input sample of a down-
`input signal to produce an
`Function: under-sampling an
`
`Plaintiff’s Proposed
`
`Construction
`
`thereof
`53A/53A-1; and equivalents
`Fig. 26; switch 5308 in Figs.
`Structure: switch 2650 in
`
`
`
`
`
`delaying said input sample”
`“first delaying means for
`
`’706 patent, claim 6
`
`
`
`
`
`signal”
`converted image of said input
`input sample of a down-
`input signal to produce an
`“means for under-sampling an
`
`’706 patent, claim 6
`
`
`
`
`
`Term
`
`Page 6 of 16
`
`
`
`equivalents thereof
`inductors, and/or resistors; and
`combination of capacitors,
`shown in Fig. 34 having a
`Fig. 45; analog delay line 3404
`circuits 4501, 4503 shown in
`Fig. 32; sample and hold
`delay module 3204 shown in
`delay module 2630 in Fig. 26;
`delay module 2628, second
`2316, 2318 in Fig. 23; first
`1914 in Fig. 19; delay modules
`FIG. 17; delay modules 1912,
`1722A, 1722B, 1722C, etc. in
`Structure: delay modules
`
`
`
`an output signal
`Function: delaying instances of
`
`Subject to § 112, ¶ 6.
`
`Court’s Final Construction
`
`
`
`
`
`equivalents thereof.
`described at 35:19-27; and
`inductors and/or resistors
`combination of capacitors,
`analog delay line having a
`described at 32:44-64; or an
`and 4503 in Fig. 45 and
`sample and hold circuits 4501
`described at 35:1-18; the
`3204” shown in Fig. 32 and
`at 32:27-55, “delay module
`shown in Fig 26 and described
`“second delay module 2630”
`“first delay module 2628,”
`Structure: structure including
`
`
`
`of an output signal
`Function: delaying instances
`
`Defendants’ Proposed
`
`Construction
`
`
`
`thereof
`resistors; and equivalents
`capacitors, inductors, and/or
`having a combination of
`line 3404 shown in Fig. 34
`shown in Fig. 45; analog delay
`hold circuits 4501, 4503
`shown in Fig. 32; sample and
`Fig. 26; delay module 3204
`second delay module 2630 in
`23; first delay module 2628,
`modules 2316, 2318 in Fig.
`1914 in Fig. 19; delay
`FIG. 17; delay modules 1912,
`1722A, 1722B, 1722C, etc. in
`Structure: delay modules
`
`of an output signal
`Function: delaying instances
`
`Plaintiff’s Proposed
`
`Construction
`
`
`
`
`
`signal”
`delaying instances of an output
`“second delaying means for
`
`’706 patent, claim 6
`
`
`
`
`
`Term
`
`Page 7 of 16
`
`
`
`frequency translator.”
`unified input filter and
`meaning is “a circuit having a
`wherein the plain-and-ordinary
`Plain-and-ordinary meaning
`Not subject to § 112, ¶ 6.
`
`
`
`and described at 32:44-64, or
`4501 or 4503 shown in Fig. 45
`18, the sample and hold circuit
`Fig. 32 and described at 35:1-
`delay module 3204 shown in
`2630 shown in Fig. 26, the
`including the delay module
`(3)
`described at 35:19-27;
`inductors and/or resistors
`combination of capacitors,
`the analog delay line having a
`and described at 32:44-64, or
`4501 or 4503 shown in Fig. 45
`18, the sample and hold circuit
`Fig. 32 and described at 35:1-
`delay module 3204 shown in
`2628 shown in Fig. 26, the
`including the delay module
`a first delay module,
`(2)
`and delay module 2624;
`1108 having the down convert
`the frequency translator
`(1)
`includes:
`(UDF) Module 2622 that
`Downconvert and Filter
`Structure: the Unified
`
`a second delay module
`
`signal
`signal according to a control
`and to undersample said input
`downconvert an input signal
`Function: to filter and
`
`
`
`translator”
`input filter and frequency
`“a circuit having a unified
`
`
`
`downconvert an input signal”
`translator to filter and
`“integral filter/frequency
`
`
`
`’706 patent, claim 28
`
`
`
`Page 8 of 16
`
`
`
`adder 2522 in Fig. 25, the
`adder 1720 in Fig. 17, the
`the adder 2625 in Fig. 26,
`(6)
`67;
`Fig. 37 and described at 35:60-
`transistors, or FETs shown in
`operational amplifiers,
`implemented using the
`amplifier/attenuator 3704
`described at 35:44-55, or the
`3602 shown in Fig. 36 and
`Fig. 26, the resistor attenuator
`scaling module 2634 shown in
`module, including the second
`(5)
`35:60-67;
`Fig. 37 and described at
`transistors, or FETs shown in
`operational amplifiers,
`implemented using
`amplifier/attenuator 3704
`described at 35:44-55, or the
`3602 shown in Fig. 36 and
`26, the resistor attenuator
`module 2632 shown in Fig.
`including the first scaling
`a first scaling module,
`described at 35:19-27;
`inductors and/or resistors
`combination of capacitors,
`the analog delay line having a
`
`a first adder including,
`
`a second scaling
`
`Page 9 of 16
`
`
`
`baseband signal”
`has been modulated by a
`at least one characteristic that
`transmission frequency having
`“an electromagnetic signal at a
`
`
`
`Court’s Final Construction
`
`thereof.
`in Fig. 41; and equivalents
`Fig. 39, and the summer 4102
`in Fig. 25, the summer 3902 in
`1720 in Fig. 17, the adder 2522
`adder 2626 in Fig. 26, adder
`a second adder, including the
`summer 4102 in Fig. 41; and
`summer 3902 in Fig. 39, or the
`
`Defendants’ Proposed
`
`Construction
`
`
`
`information”
`represent the transmitted
`characteristics varied to
`“a signal with physical
`
`
`
`baseband signal”
`has been modulated by a
`at least one characteristic that
`transmission frequency having
`“an electromagnetic signal at a
`
`
`
`’706 patent, claim 127
`
`“modulated signal”
`
`
`
`
`
`Plaintiff’s Proposed
`
`Construction
`
`Term
`
`Page 10 of 16
`
`
`
`equivalents thereof.
`3704 in Fig. 37; and
`including amplifier/attenuator
`35, 36; scaling module 3702
`attenuator 3504, 3602 in Figs.
`module 3502 including resistor
`2634 in Fig. 26; scaling
`Fig. 23; scaling module 2632,
`modules 2312, 2320, 2322 in
`1918 in Fig. 19; scaling
`19; scaling modules 1916,
`scaling module 1909 in Fig.
`1724B, 1724C in Fig. 17; input
`1716A, 1716B, 1716C, 1724A,
`Structure: scaling modules
`
`filter parameters
`Function: tuning one or more
`
`Subject to § 112, ¶ 6.
`
`
`
`
`
`
`
`thereof.
`and 42:2732) and equivalents
`etc.) (described at 36:63-37:5
`resistors, capacitors, inductors,
`components (such as tunable
`4210 using tunable
`aperture optimizing module
`tunable oscillator 4204 and an
`42:27-32) implemented with a
`described at 36:44-62 and
`(shown in Fig. 42 and
`control signal generator 4202
`equivalents thereof; OR the
`described at 42:33-36); and
`capacitors, or inductors (as
`having tunable resistors,
`amplifier/attenuator 3704
`attenuator 3602 and the
`67), each of the resistor
`Fig. 37 and described at 35:60-
`transistors, or FETS (shown in
`operational amplifiers,
`3704 implemented using
`or the amplifier/attenuator
`36 and described at 35:44-55)
`attenuator 3602 (shown in Fig.
`including the resistor
`Structure: scaling modules
`
`filter parameters
`Function: tuning one or more
`
`
`
`
`
`
`
`equivalents thereof
`generator 4202 in Fig. 42; and
`Fig. 37; control signal
`amplifier/attenuator 3704 in
`3702 including
`in Figs. 35, 36; scaling module
`resistor attenuator 3504, 3602
`scaling module 3502 including
`module 2632, 2634 in Fig. 26;
`2320, 2322 in Fig. 23; scaling
`Fig. 19; scaling modules 2312,
`scaling modules 1916, 1918 in
`module 1909 in Fig. 19;
`in Fig. 17; input scaling
`control signal generator 1790
`1724B, 1724C in Fig. 17;
`1716A, 1716B, 1716C, 1724A,
`Structure: scaling modules
`
`filter parameters
`Function: tuning one or more
`
`
`
`
`
`one or more filter parameters”
`“filter tuning means for tuning
`
`’706 patent, claim 134
`
`
`
`
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`Page 11 of 16
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`
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`26; and equivalents thereof.
`Fig. 43 and described at 49:6-
`circuit element 4104 shown in
`at 49:6-26, which incorporates
`shown in Fig. 41 and described
`the pulse shaping circuit 4100
`described at 48:40-49:5, and
`shown in Fig. 40A and
`pulse shaping circuit 4000
`and described at 48:8-39, the
`circuit 3900 shown in Fig. 39A
`Structure: the pulse shaping
`
`pulses from a reference signal
`Function: shaping a string of
`
`Subject to § 112, ¶ 6.
`
`
`
`
`
`Court’s Final Construction
`
`26; and equivalents thereof.
`Fig. 43 and described at 49:6-
`circuit element 4104 shown in
`at 49:6-26, which incorporates
`shown in Fig. 41 and described
`the pulse shaping circuit 4100
`described at 48:40-49:5, and
`shown in Fig. 40A and
`pulse shaping circuit 4000
`and described at 48:8-39, the
`circuit 3900 shown in Fig. 39A
`Structure: the pulse shaping
`
`pulses from a reference signal
`Function: shaping a string of
`
`Defendants’ Proposed
`
`Construction
`
`
`
`
`
`and equivalents thereof
`pulse shaper 7812 in Fig. 78;
`pulse shaper 6216 in Fig. 62;
`circuit 5722 in Fig. 57A-C,
`in Fig. 56; pulse shaping
`in Fig. 55; pulse shaper 5632
`in Fig. 54A; pulse shaper 5438
`in Fig. 53; pulse shaper 5438
`Fig. 51B-C; pulse shaper 5310
`enhancement module 5124 in
`Fig. 50; harmonic
`Fig. 46; signal shaper 5010 in
`enhancement module 4602 in
`4100 in Fig. 41; harmonic
`Fig. 40A; pulse shaping circuit
`circuit/pulse shaper 4000 in
`in Fig. 39A; pulse shaping
`Structure: pulse shaper 3900
`
`
`
`pulses from a reference signal
`Function: shaping a string of
`
`Plaintiff’s Proposed
`
`Construction
`
`
`
`a reference signal”
`shaping a string of pulses from
`“pulse shaping means for
`
`’508 patent, claim 1
`
`
`
`
`
`Term
`
`Page 12 of 16
`
`
`
`string of pulses
`of multiple pulses from said
`Function: generating a string
`
`Subject to § 112, ¶ 6.
`
`
`
`
`
`equivalents thereof.
`shown in Fig. 79; and
`generation module 7806
`Structure: the aperture
`
`
`
`Plain and ordinary meaning
`
`
`
`Court’s Final Construction
`
`as said string of pulses”
`multiple the number of pulses
`“generating a signal with
`
`thereof.
`at 49:54-50:5; and equivalents
`shown in Fig. 79 and described
`generation module 7806
`Structure: the aperture
`
`string of pulses
`of multiple pulses from said
`Function: generating a string
`
`Defendants’ Proposed
`
`Construction
`
`
`
`
`
`equivalents thereof
`shown in Fig. 79; and
`aperture generation module
`gate(s) and delay(s) such as the
`module 7806 in Fig. 78 having
`Structure: aperture generation
`
`Plain and ordinary meaning
`
`
`
`
`
`string of pulses
`of multiple pulses from said
`Function: generating a string
`
`Plaintiff’s Proposed
`
`Construction
`
`
`
`pulses”
`pulses from said string of
`“generating a string of multiple
`
`’508 patent, claim 1
`
`
`
`
`
`string of pulses”
`multiple pulses from said
`for generating a string of
`“aperture generation means …
`
`’508 patent, claim 1
`
`
`
`
`
`Term
`
`Page 13 of 16
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`
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`frequency
`one of which is at a desired
`plurality of harmonics at least
`periodic signal having a
`of multiple pulses to generate a
`under the control of said string
`Function: gating a bias signal
`
`Subject to § 112, ¶ 6.
`
`
`
`33A, and equivalents thereof.
`shown in 29A, 30A, 32A, and
`55, 56, 57A-C; the GaAsFETs
`in Figs. 28A, 31A, 53, 54A,
`Structure: the switches shown
`
`
`
`
`
`Court’s Final Construction
`
`55; and equivalents thereof.
`57A-B and described at 65:49-
`switch 5724 shown in Figs.
`and described at 60:1-22;
`switch 5420 shown in Fig. 54A
`and described at 60:66-61:10;
`switch 5636 shown in Fig. 56
`described at 58:63-59:13,
`5312 shown in Fig. 53 and
`described at 36:25-50; switch
`shown in Fig. 30A and
`50; GaAsFETs 3002 and 3004
`29A and described at 36:25-
`GaAsFET 2901 shown in Fig.
`35:1436:24 and 45:47-46:37;
`in Fig. 28A and described at
`Structure: switch 2816 shown
`
`
`
`frequency
`one of which is at a desired
`plurality of harmonics at least
`periodic signal having a
`of multiple pulses to generate a
`under the control of said string
`Function: gating a bias signal
`
`Defendants’ Proposed
`
`Construction
`
`
`
`equivalents thereof
`57A-C; and
`32A, 33A, 53, 54A, 55, 56,
`Fig. 28A, 29A, 30A, 31A,
`in
`Structure: the switches shown
`
`
`
`frequency
`one of which is at a desired
`plurality of harmonics at least
`periodic signal having a
`of multiple pulses to generate a
`under the control of said string
`Function: gating a bias signal
`
`Plaintiff’s Proposed
`
`Construction
`
`
`
`desired frequency”
`at least one of which is at a
`having a plurality of harmonics
`generate a periodic signal
`string of multiple pulses to
`signal under the control of said
`“gating means for gating a bias
`
`’508 patent, claim 1
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`
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`Term
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`Page 14 of 16
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`input”
`by an independent control
`and closing a circuit as dictated
`electronic device for opening
`and-ordinary meaning is “an
`meaning wherein the plain-
`“Switch”: Plain-and-ordinary
`
`
`
`string of pulses”
`oscillating signal to generate a
`“circuitry that shapes an
`
`Plain and ordinary meaning
`
`
`
`signal”
`on an independent control
`pass through the device based
`allowing the input signal to
`meaning is “preventing or
`wherein the plain-and-ordinary
`Plain-and-ordinary meaning
`
`voltage or fixed current”
`“a signal having a fixed
`
`
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`Court’s Final Construction
`
`voltage or fixed current”
`“a signal having a fixed
`
`
`
`to selectively output a signal”
`“opening and closing a device
`
`Defendants’ Proposed
`
`Construction
`
`
`
`shaping an oscillating signal”
`enhance a desired harmonic by
`“a circuit configured to
`
`
`
`string of pulses”
`oscillating signal to generate a
`“circuitry that shapes an
`
`
`
`’108 patent, claims 6, 8
`
`“pulse shaper”
`
`
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`
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`desired output frequency”
`harmonic of and lower than the
`frequency that is a sub-
`controls the first switch with a
`“an oscillating signal that
`
`
`
`signal”
`the antenna transmits said
`“a switch controlling whether
`
`
`
`Court in Case No. 6:20-cv-108
`“switch” as construed by the
`Plain and ordinary meaning, or
`
`
`
`Plain and ordinary meaning
`
`
`
`modulating baseband signal”
`predetermined level; or 2) the
`“1) a signal having a steady,
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`
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`control input”
`as dictated by an independent
`and closed states of a switch,
`“changing between the open
`
`Plaintiff’s Proposed
`
`Construction
`
`
`
`’108 patent, claim 1
`
`“third switch”
`
`
`
`
`
`patent, claim 1
`’508 patent, claim 1; ’108
`
`“bias signal”
`
`
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`
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`’108 patent, claim 1
`
`
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`“control signal”
`
`’508 patent, claim 1
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`“gating”
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`Term
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`Page 15 of 16
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`Page160f16
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`Page 16 of 16
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