UNITED STATES DISTRICT COURT
`WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`CASE NO. 6:19-CV-00236-ADA
`
`JURY TRIAL DEMANDED
`
`SOLAS OLED LTD., an Irish corporation,
`
`Plaintiff,
`
`v.
`
`LG DISPLAY CO., LTD., a Korean
`corporation; LG ELECTRONICS INC., a
`Korean corporation; LG DISPLAY
`AMERICA, INC., a California corporation;
`LG ELECTRONICS USA, INC., a Delaware
`corporation; SONY CORPORATION, a
`Japanese corporation; and SONY
`ELECTRONICS INC., a Delaware
`Corporation,
`
`Defendants.
`
`CORRECTED EXPERT REPORT OF DOUGLAS R. HOLBERG REGARDING
`INVALIDITY OF U.S. PATENT NOS. 7,432,891, 7,573,068, AND 7,907,137
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`LG DISPLAY V. SOLAS
`IPR2020-01238
`Exhibit 2018
`Page 1
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`
`
`CONTENTS
`
`I.
`
`II.
`
`III.
`
`IV.
`
`Introduction ..........................................................................................................................5
`
`Qualifications and Compensation ........................................................................................5
`
`Scope of Expert Report and Materials Considered ..............................................................7
`
`Understanding Of Legal Principles ......................................................................................8
`
`A.
`B.
`C.
`D.
`E.
`F.
`G.
`H.
`
`American Invents Act (“AIA”) ................................................................................8
`Presumption of Validity and Burden of Proof .........................................................8
`Person of Ordinary Skill in the Art ..........................................................................8
`Invalidity Framework – Anticipation and Obviousness ..........................................9
`What Constitutes Prior Art .....................................................................................12
`35 U.S.C. § 102: Invalidity by Anticipation ..........................................................12
`35 U.S.C. § 103: Invalidity by Obviousness ..........................................................14
`35 U.S.C. § 112(1): Written Description and Enablement ....................................17
`
`V.
`
`Technology Background ....................................................................................................18
`
`A.
`B.
`C.
`D.
`E.
`F.
`G.
`
`Current and voltage ................................................................................................19
`OLEDs ...................................................................................................................21
`Active Matrix & Passive Matrix OLED displays ..................................................23
`Thin Film Transistors .............................................................................................24
`Circuit Diagrams and Symbols ..............................................................................28
`Drive Circuits in Active Matrix Displays ..............................................................30
`Manufacturing of Active Matrix OLED Displays .................................................33
`
`VI.
`
`Invalidity of U.S. Patent No. 7,432,891 .............................................................................37
`
`A.
`B.
`C.
`D.
`
`E.
`
`F.
`
`Overview of the ’891 Patent ..................................................................................37
`Prosecution History and Patent Office Proceedings ..............................................40
`Asserted Claims of the ’891 Patent ........................................................................41
`Prior Art Overview ................................................................................................42
`1.
`Kim, Korean Patent Application No. 2002-0027957 .................................42
`2.
`Shimoda, U.S. Patent No. 6,809,706 .........................................................48
`3.
`Tang, U.S. Patent No. 5,550,066 ...............................................................49
`4.
`Tang-678, U.S. Patent No. 5,552,678 ........................................................51
`5.
`Noguchi, U.S. Patent App. Publ. No. 2003/0103022 ................................51
`Evidence and discussions relating to the invalidity of the ’891 patent in
`view of the prior art................................................................................................52
`Anticipation and Obviousness ...............................................................................53
`1.
`Kim anticipates claims 1 and 3 of the ’891 patent .....................................53
`2.
`Kim renders obvious claims 1 and 3 of the ’891 patent ............................53
`
`
`
`2
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`3.
`
`4.
`
`5.
`
`Kim in combination with Tang renders obvious claims 1 and 3 of
`the ’891 patent ............................................................................................56
`Kim in combination with Tang and Tang-678 and/or Noguchi
`renders obvious claims 1 and 3 of the ’891 patent .....................................60
`Shimoda in combination with Kim renders obvious claims 1 and 3
`of the ’891 patent .......................................................................................62
`G. Written Description and Enablement .....................................................................67
`1.
`“Current measuring- and voltage regulating circuit” .................................67
`
`VII.
`
`Invalidity of U.S. Patent No. 7,573,068 .............................................................................73
`
`A.
`B.
`C.
`D.
`
`E.
`
`F.
`
`6.
`
`Overview of the ’068 Patent ..................................................................................73
`Prosecution History ................................................................................................78
`Asserted Claims .....................................................................................................78
`Prior Art Overview ................................................................................................80
`1.
`Shin, International Publication WO 2004/090853 .....................................80
`2.
`Komiya, United States Patent No. 6,724,149 ............................................98
`3.
`Hector, International Publication WO 2003/079442 ...............................101
`4.
`Childs, International Publication No. WO 03/079441 .............................109
`5.
`Yamazaki, United States Patent Application Publication No.
`2002/0079503 ..........................................................................................116
`Shirasaki, United States Patent Application Publication No.
`2004/0113873 ..........................................................................................118
`Evidence and discussions relating to the invalidity of the ’068 patent in
`view of the prior art..............................................................................................121
`Anticipation and Obviousness .............................................................................122
`1.
`Shin anticipates claims 1, 5, 10, and 13 of the ’068 patent,
`including under Solas’s alleged infringement theories with respect
`to “gate insulating film” in its Final Infringement Contentions ..............122
`Shin renders obvious claims 1, 5, 10 and 13 of the ’068 patent,
`including under Solas’s alleged infringement theories with respect
`to “gate insulating film” in its Final Infringement Contentions ..............123
`Komiya anticipates claims 1, 5, and 13 of the ’068 patent, and
`renders obvious claim 10, under Solas’s alleged infringement
`theories for “patterned to fit together” in its Final Infringement
`Contentions ..............................................................................................126
`Komiya in combination with one of Shin, Hector, or Childs, or
`Shin in combination with one of Hector or Childs, renders obvious
`claims 1, 5, 10 and 13 of the ’068 patent .................................................128
`Yamazaki renders obvious claims 1, 5, and 13 of the ’068 patent
`under Solas’s alleged infringement theories with respect to “gate
`insulating film” ........................................................................................136
`Yamazaki in view of one of Hector or Childs renders obvious
`claims 1, 5, 10 and 13 of the ’068 patent under Solas’s alleged
`infringement theories with respect to “gate insulating film” in its
`Final Infringement Contentions ...............................................................138
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`
`
`3
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`7.
`
`Shirasaki in view of one of Hector or Childs renders obvious
`claims 1, 5, 10 and 13 of the ’068 patent .................................................141
`Claims 1, 5, 10 and 13 are invalid for lack of written description .......................145
`
`G.
`
`VIII.
`
`Invalidity of U.S. Patent No. 7,907,137 ...........................................................................147
`
`A.
`B.
`C.
`D.
`
`E.
`
`F.
`
`3.
`
`Overview of the ’137 Patent ................................................................................147
`Prosecution History of the ’137 patent ................................................................152
`Asserted Claims of the ’137 Patent ......................................................................155
`Prior Art Overview ..............................................................................................157
`1.
`Miyazawa, U.S. Patent Publication No. 2005/0116902...........................157
`2.
`Kasai-412, U.S. Patent Publication No. 2005/0099412 ...........................163
`3.
`Childs-267, International Publication No. WO 2005/069267A1.............168
`4.
`Kageyama, U.S. Patent No. 7,012,586 ....................................................172
`5.
`Kasai-837, U.S. Patent Publication No. 2005/0156837 ...........................174
`Evidence and discussions relating to the invalidity of the ’137 patent in
`view of the prior art..............................................................................................179
`Anticipation and Obviousness .............................................................................180
`1.
`Miyazawa anticipates Claims 10, 11, 36, and 37 of the ’137 patent .......181
`2.
`Miyazawa renders obvious Claims 10, 11, 36 and 37 of the ’137
`patent ........................................................................................................181
`The combination of Miyazawa and one of Childs-267 or
`Kageyama renders obvious Claims 10, 11, 36, and 37 of the ’137
`patent ........................................................................................................183
`The combination of Kasai-412 and one of Miyazawa, Childs-267
`or Kageyama renders obvious Claims 10, 11, 36, and 37 of the
`’137 patent ...............................................................................................189
`Claims 15 and 39 would have been rendered obvious in view of
`Kasai-837 and the references or combination of references
`discussed above ........................................................................................193
`
`4.
`
`5.
`
`IX.
`
`Secondary Considerations Of Non Obviousness .............................................................196
`
`A.
`B.
`C.
`D.
`E.
`F.
`G.
`H.
`
`Commercial Success ............................................................................................197
`Long-Felt But Unsolved Need .............................................................................199
`Failure of Others ..................................................................................................200
`Skepticism by Experts..........................................................................................201
`Praise by Others ...................................................................................................202
`Teaching Away by Others ...................................................................................203
`Recognition of a Problem Which the Claimed Invention Addresses ..................203
`Unexpected Results ..............................................................................................204
`
`X.
`
`Final Comments ...............................................................................................................205
`
`
`
`
`
`
`4
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`I.
`
`INTRODUCTION
`
`1.
`
`I am more than eighteen years of age, and I am a citizen of the United States,
`
`currently residing in Texas.
`
`2.
`
`I have been retained by counsel for Defendants to provide my opinions as to the
`
`invalidity of asserted claims 10, 11, 15, 36, 37, and 39 of U.S. Patent No. 7,907,137 (the “’137
`
`patent”), claims 1 and 3 of U.S. Patent No. 7,432,891 (the “’891 patent”), and claims 1, 5, 10, and
`
`13 of U.S. Patent No. 7,573,068 (the “’068 patent”) (collectively, the “Asserted Claims” of the
`
`“Asserted Patents”), asserted by Solas OLED Ltd. (“Solas”) in this action. Based on my analysis
`
`and investigation, I have reached certain conclusions and developed certain opinions on the issues
`
`that I discuss in this report.
`
`3.
`
`My opinions expressed herein are based on review and analysis of certain
`
`information obtained in connection with my work on this matter, together with my training,
`
`education, and experience. The opinions expressed herein are my own.
`
`4.
`
`In my analysis, I considered the Asserted Patents and their file histories, the prior
`
`art, my experience in the relevant field and industry, as well as other documentation discussed
`
`below.
`
`II.
`
`QUALIFICATIONS AND COMPENSATION
`
`5.
`
`In formulating my opinions, I have relied upon my knowledge, training, and
`
`experience in the relevant art. My qualifications are stated more fully in my curriculum vitae,
`
`which has been provided as Exhibit A. Here, I provide a brief summary of my qualifications.
`
`6.
`
`My education includes a B.S. in Electrical Engineering from Texas A&M
`
`University in 1977, followed by a M.S. in Electrical Engineering from the University of Texas in
`
`1989. I earned a Ph.D. in Electrical Engineering from the University of Texas in 1992.
`
`
`
`5
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`to anticipation and obviousness in Section VII.F below. This was done to streamline my analysis,
`
`and should not be interpreted as an admission that any limitation that is not discussed in any of
`
`Appendices B-1 to B-6 is missing or would not have been obvious in view of those prior art
`
`references. Indeed, other limitations of the asserted claims, to the extent not addressed in
`
`Appendices B-1 to B-6, may be disclosed by Shin, Komiya, Hector, Childs, Yamazaki, and
`
`Shirasaki, particularly under the interpretations of the asserted claims set forth in Solas’s
`
`infringement contentions.
`
`F.
`
`Anticipation and Obviousness
`1.
`
`Shin anticipates claims 1, 5, 10, and 13 of the ’068 patent, including under
`Solas’s alleged infringement theories with respect to “gate insulating film”
`in its Final Infringement Contentions
`
`224.
`
`It is my opinion that claims 1, 5, 10 and 13 of the ’068 patent are anticipated by the
`
`disclosures in Shin, for example by the embodiment discussed in Figures 18-24. Furthermore, it
`
`is my opinion that claims 1, 5, 10, and 13 of the ’068 patent are anticipated by, for example, Shin’s
`
`embodiment discussed in Figures 7-17 under Solas’s alleged infringement theories with respect to
`
`“gate insulating film” in its Final Infringement Contentions.
`
`225.
`
`I have provided exemplary disclosures of Shin applied to the limitations of those
`
`claims in Appendix B-1. As I discuss in Appendix B-1, for example in the embodiment depicted
`
`in Figures 18-24, Shin discloses a plurality of driving transistors, signal lines, supply lines, and
`
`feed interconnections along said plurality of supply lines arranged as they are in the asserted
`
`claims. Because Shin discloses each and every limitation of claims 1, 5, 10 and 13 of the ’068
`
`patent arranged in the same way as they are in the asserted claims, those asserted claims are
`
`anticipated by Shin.
`
`226. Additionally, I have provided exemplary disclosures of Shin applied to the
`
`limitations of those claims in Appendix B-1 under Solas’s infringement theories with respect to
`
`
`
`122
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`“gate insulating film” in its Final Infringement Contentions. As I discuss in Appendix B-1, for
`
`example in the embodiment depicted in Figures 7-17, Shin discloses a plurality of driving
`
`transistors, signal lines, supply lines, and feed interconnections along said plurality of supply lines
`
`arranged as they are in the asserted claims in the embodiment. Because Shin discloses each and
`
`every limitation of claims 1, 5, 10 and 13 of the ’068 patent arranged in the same way as they are
`
`in the asserted claims, those asserted claims are anticipated by Shin under Solas’s infringement
`
`theories.
`
`2.
`
`Shin renders obvious claims 1, 5, 10 and 13 of the ’068 patent, including
`under Solas’s alleged infringement theories with respect to “gate
`insulating film” in its Final Infringement Contentions
`
`227. To the extent Solas alleges, or the Judge or Jury finds, that any limitation of claims
`
`1, 5, 10, and 13 are not disclosed by Shin (see evidence and discussions regarding Shin in Appendix
`
`B-1), it is my opinion that Shin renders obvious claims 1, 5, 10 and 13 of the ’068 patent.
`
`228. For example, if Solas alleges that Shin’s Figures 18-24 are directed to multiple
`
`embodiments, rather than a single embodiment, it would have been obvious to combine the
`
`teachings relating to Figures 18-24 because they each describe a circuit having an identical
`
`structure. For example, Shin’s description refers to Figure 18 as “another exemplary embodiment
`
`of the present invention,” Figures 19-20 as “another exemplary embodiment of the present
`
`invention,” and Figures 21-24 as “another exemplary embodiment of the present invention.” Shin,
`
`24:17-19, 25:24-27, 26:11-13. As discussed in the Shin overview above, a POSA would have
`
`understood “another exemplary embodiment” to refer to the same unit pixel embodiment with
`
`different descriptions of its structure, including its circuit diagram, plan view, and manufacturing
`
`method. Alternatively, a POSA would have, at a minimum, found it obvious that “another
`
`exemplary embodiment” in this context to refer to different descriptions of the same unit pixel
`
`embodiment (i.e., circuit diagram, plan view, manufacturing method). A POSA would have been
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`motivated to do so because Figures 18-24 all describe the same circuit, are immediately adjacent
`
`in the patent, and clearly describe the same unit pixel structure based on NMOS amorphous silicon
`
`transistors. Likewise, a POSA would have understood that Shin’s overall display structure, such
`
`as with reference to Figures 3-6 and their corresponding description, are applicable to the
`
`embodiment of a unit pixel in Figures 18-24. If Solas contends otherwise, it would have been
`
`obvious to combine Figures 18-24 and its associated description with Figures 3-6 and their
`
`corresponding structure. A POSA would have been motivated to do so because Figures 18-24
`
`describe only a single pixel, and Figures 3-6 teach how a unit pixel can be used to design a display.
`
`229. As another example, as discussed above and in Appendix B-1, Shin’s embodiment
`
`depicted in Figures 7-17 discloses asserted claims 1, 5, 10, and 13 under Solas’s alleged
`
`infringement theories with respect to “gate insulating film” and “crossing via the gate insulating
`
`film” limitations. If Solas alleges that Shin’s Figures 7-17 are directed to multiple embodiments,
`
`rather than a single embodiment, it would have been obvious to combine the teachings relating to
`
`Figures 7-17 because they each describe a circuit having an identical structure. For example,
`
`Shin’s description refers to Figure 7 as “an exemplary embodiment of the present invention,”
`
`Figures 8-9 as “an exemplary embodiment of the present invention,” and Figures 10-17 as “an
`
`exemplary embodiment of the present invention.” Shin, 5:23-6:5, 15:8-10, 17:8-10, 21:24-26. As
`
`discussed in the Shin overview above, a POSA would have understood “an exemplary
`
`embodiment” to refer to the same unit pixel embodiment with different descriptions of its structure,
`
`including its circuit diagram, plan view, and manufacturing method. Alternatively, a POSA would
`
`have, at a minimum, found it obvious that “an exemplary embodiment” in this context to refer to
`
`different descriptions of the same unit pixel embodiment (i.e., circuit diagram, plan view,
`
`manufacturing method). A POSA would have been motivated to do so because Figures 7-17 all
`
`
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`describe the same circuit, are immediately adjacent in the patent, and clearly describe the same
`
`two adjacent unit pixels. Likewise, a POSA would have understood that Shin’s overall display
`
`structure, such as with reference to Figures 3-6 and their corresponding description, are applicable
`
`to the embodiment of a unit pixel in Figures 7-17. If Solas contends otherwise, it would have been
`
`obvious to combine Figures 7-17 and its associated description with Figures 3-6 and their
`
`corresponding structure. A POSA would have been motivated to do so because Figures 7-17
`
`describe only two adjacent unit pixels, and Figures 3-6 teach how a unit pixel can be used to design
`
`a display.
`
`230. Furthermore, to the extent Solas contends that limitation [13g] requires there to be
`
`a “plurality of light emitting layers” on each of the plurality of pixel electrodes, then feature [13g]
`
`would have been obvious in view of Shin. For example, in Figures 18-24, Shin describes a
`
`plurality of pixel electrodes and a plurality of light emitting layers formed thereon. In other
`
`embodiments, such as for example the embodiment depicted in Figures 7-17, Shin discloses that
`
`to “improve luminance,” an “organic electro luminescent layer” may be formed as a plurality of
`
`layers on a pixel electrode, such as “[t]he organic electro luminescent layer 180 [may] include[] a
`
`hole injection film formed on the pixel electrode layer 170, a hole transporting film formed on the
`
`hole injection film, a light emitting film formed on the hole transporting film and an electron
`
`transporting film formed on the light emitting film.” Id., 20:9-12. As another example, Shin
`
`teaches “the organic electro luminescent layer 180 may include a hole transporting film formed on
`
`the pixel electrode layer 170, the light emitting film formed on the hole transporting film and the
`
`electron transporting film formed on the light emitting film.” Id., 20:13-16. And Shin teaches the
`
`“organic electro luminescent layer 180 may also include the hole injection film formed on the pixel
`
`electrode layer 170, the hole transporting film formed on the hole injection film, the light emitting
`
`
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`film formed on the hole transporting film, the electron transporting film formed on the light
`
`emitting film and an electron injection film formed on the electron transporting film.” Id., 20:16-
`
`20; see also id., 39:14-26 (same disclosures with respect to “organic electro luminescent layer
`
`370”). A POSA would have been motivated to use such a multi-layer structure in Shin’s Figure
`
`18-24 embodiment to improve luminance, as Shin teaches, and improved luminance was a typical
`
`goal for POSAs when designing an OLED display panel. Shin, 20:8-9; see also id., 1:16-23
`
`(describing that a benefit of using OLEDs as a light emitting element in a panel is their “higher
`
`luminance”).
`
`231. Furthermore, Shin teaches that forming organic electro luminescent layers as a
`
`single layer or as multiple layers was a design choice, and would be formed in substantially the
`
`same way. See, e.g., Shin, 20:4-7 (describing formation of OEL layer 180), 28:10-14 (same with
`
`respect to OEL layer N60), 39:6-13 (same with respect to OEL layer 370). First, the pixel electrode
`
`would be formed, then the light emitting layer or layers in a “light emitting region” defined by a
`
`“partition wall,” and then the “counter electrode” is formed on the light emitting layers. Id., 20:4-
`
`7, 28:10-14, 39:6-13.
`
`3.
`
`Komiya anticipates claims 1, 5, and 13 of the ’068 patent, and renders
`obvious claim 10, under Solas’s alleged infringement theories for
`“patterned to fit together” in its Final Infringement Contentions
`
`232.
`
`It is my opinion that claims 1, 5, and 13 of the ’068 patent are anticipated by
`
`Komiya only under Solas’s alleged infringement theories of “patterned together,” i.e., “patterned
`
`to fit together,” in Solas’s Final Infringement Contentions. Specifically, Komiya discloses each
`
`of the limitations of claims 1, 5 and 13, arranged as they are in the claim, except that Komiya’s
`
`“supply lines” are patterned in the same layer, and therefore patterned to fit with, the drains of the
`
`driving transistor, but the sources of the driving transistor are formed with a separate ITO layer
`
`forming the pixel electrode of the OLED. Thus, Komiya’s supply lines are not “patterned together
`126
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