c12) United States Patent
`Nakamura et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,115,956 B2
`Oct. 3, 2006
`
`I 1111111111111111 11111 1111111111 11111 11111 111111111111111 lll111111111111111
`US007115956B2
`
`(54) CONDUCTIVE FILM AS THE CONNECTOR
`FOR THIN FILM DISPLAY DEVICE
`
`(75)
`
`Inventors: Osamu Nakamura, Kanagawa (JP);
`Hideaki Kuwahara, Kanagawa (JP);
`Noriko Shibata, Kanagawa (JP)
`
`(73) Assignee: Semiconductor Energy Laboratory
`Co., Ltd., Atsugi (JP)
`
`( *) Notice:
`
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`U.S.C. 154(b) by O days.
`
`(21) Appl. No.: 10/430,443
`
`(22) Filed:
`
`May 7, 2003
`
`(65)
`
`Prior Publication Data
`
`US 2003/0214006 Al Nov. 20, 2003
`
`(30)
`
`Foreign Application Priority Data
`
`May 15, 2002
`
`(JP)
`
`(51)
`
`Int. Cl.
`HOJL 29176
`
`(2006.01)
`
`2002-140743
`
`(52) U.S. Cl. ....................... 257/382; 257/637; 257/641;
`257/773; 257/774
`(58) Field of Classification Search ......... 257/381-382,
`257/637-641, 773-774
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,576,858 A
`5,643,826 A
`5,663,589 A
`5,701,167 A
`5,748,165 A
`5,889,291 A
`5,923,962 A
`5,990,555 A
`5,990,998 A
`
`ll/ 1996 Ukai et al.
`7 / 1997 Ohtani et al.
`9/ 1997 Saitoh et al.
`12/1997 Yamazaki
`5/ 1998 Kubota et al.
`3/1999 Koyama et al.
`7 / 1999 Ohtani et al.
`* ll/ 1999 Ohori et al.
`ll/ 1999 Park et al.
`
`................ 257 /7 50
`
`6,031,290 A
`6,067,062 A
`6,078,366 A
`6,084,461 A
`6,107,983 A
`6,169,391 Bl
`6,191,408 Bl
`6,208,395 Bl
`6,225,966 Bl
`6,372,558 Bl
`6,456,350 Bl
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`6,465,806 Bl
`6,489,222 Bl
`
`2/2000 Miyazaki et al.
`5/2000 Takasu et al.
`6/2000 Dohjo et al.
`7/2000 Colbeth et al.
`8/2000 Masuda et al.
`1/2001 Lei
`2/2001 Shinotsuka et al.
`3/2001 Kanoh et al.
`5/2001 Ohtani et al.
`4/2002 Yamanaka et al.
`9/2002 Ashizawa et al.
`10/2002 Kitakado et al.
`10/2002 Kubota et al.
`12/2002 Yoshimoto
`(Continued)
`FOREIGN PATENT DOCUMENTS
`
`EP
`1 128 430 A2
`8/2001
`JP
`06-148685
`5/1994
`JP
`06-281957
`10/1994
`JP
`07-235680
`9/1995
`JP
`08-274336
`10/1996
`JP
`10-048640
`2/1998
`JP
`2001-313397
`11/2001
`Primary Examiner----George Fourson
`Assistant Examiner-Thanh V Pham
`(74) Attorney, Agent, or Firm-Fish & Richardson P.C.
`ABSTRACT
`(57)
`
`In the manufacture of a semiconductor device, there are
`provided a method that enables reduction in the number of
`manufacturing steps thereof and a structure for realizing the
`method, to thereby realize improvement in yield and reduc(cid:173)
`tion in manufacturing cost. Wirings (source wiring, drain
`wiring, and the like), which are respectively formed in a row
`direction and a column direction on an element substrate, are
`formed of the same conductive film. In this case, one of the
`respective wirings in the row direction and the column
`direction is discontinuously formed at a portion where the
`wirings intersect with each other, and an insulating film is
`formed on the wirings. Thereafter, a connection wiring for
`connecting discontinuous wirings is formed of the same film
`as that for forming an electrode provided on the insulating
`film. As a result, a continuous wiring is formed.
`
`24 Claims, 17 Drawing Sheets
`
`.~ .
`
`LG Display Co., Ltd.
`Exhibit 1016
`Page 001
`
`

`

`US 7,115,956 B2
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`6,498,596 Bl
`6,524,877 Bl
`6,670,225 Bl
`6,677,221 Bl
`6,690,033 Bl
`2001/0017372 Al
`
`12/2002 Nakamura et al.
`2/2003 Nakazawa et al.
`12/2003 Ohnuma
`1/2004 Kawasaki et al.
`2/2004 Yamazaki et al.
`8/2001 Koyama
`
`2001/0025959 Al
`2001/0030322 Al
`2002/0110941 Al
`2002/0158288 Al
`2003/0214006 Al
`
`10/2001
`10/2001
`8/2002
`10/2002
`11/2003
`
`Yamazaki et al.
`Yamazaki et al.
`Yamazaki et al.
`Yamazaki et al.
`Nakamura et al.
`
`* cited by examiner
`
`LG Display Co., Ltd.
`Exhibit 1016
`Page 002
`
`

`

`U.S. Patent
`
`Oct. 3, 2006
`
`Sheet 1 of 17
`
`US 7,115,956 B2
`
`209
`
`204 212
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`203
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`
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`
`207
`
`FIG. 1C
`
`LG Display Co., Ltd.
`Exhibit 1016
`Page 003
`
`

`

`U.S. Patent
`
`Oct. 3, 2006
`
`Sheet 2 of 17
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`US 7,115,956 B2
`
`Fig. 2A
`
`309
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`
`LG Display Co., Ltd.
`Exhibit 1016
`Page 004
`
`

`

`U.S. Patent
`
`Oct. 3, 2006
`
`Sheet 3 of 17
`
`us 7,115,956 B2
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`114
`
`Fig. 3
`
`LG Display Co., Ltd.
`Exhibit 1016
`Page 005
`
`

`

`U.S. Patent
`
`Oct. 3, 2006
`
`Sheet 4 of 17
`
`US 7,115,956 B2
`
`Fig. 4A
`
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`LG Display Co., Ltd.
`Exhibit 1016
`Page 006
`
`

`

`U.S. Patent
`
`Oct. 3, 2006
`
`Sheet 5 of 17
`
`US 7,115,956 B2
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`LG Display Co., Ltd.
`Exhibit 1016
`Page 007
`
`

`

`U.S. Patent
`
`Oct. 3, 2006
`
`Sheet 6 of 17
`
`US 7,115,956 B2
`
`109
`
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`
`LG Display Co., Ltd.
`Exhibit 1016
`Page 008
`
`

`

`U.S. Patent
`
`Oct. 3, 2006
`
`Sheet 7 of 17
`
`US 7,115,956 B2
`
`Fig. 7
`
`LG Display Co., Ltd.
`Exhibit 1016
`Page 009
`
`

`

`U.S. Patent
`
`Oct. 3, 2006
`
`Sheet 8 of 17
`
`US 7,115,956 B2
`
`Fig. 8
`
`LG Display Co., Ltd.
`Exhibit 1016
`Page 010
`
`

`

`U.S. Patent
`
`Oct. 3, 2006
`
`Sheet 9 of 17
`
`US 7,115,956 B2
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`LG Display Co., Ltd.
`Exhibit 1016
`Page 011
`
`

`

`U.S. Patent
`
`Oct. 3, 2006
`
`Sheet 10 of 17
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`US 7,115,956 B2
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`LG Display Co., Ltd.
`Exhibit 1016
`Page 012
`
`

`

`U.S. Patent
`
`Oct. 3, 2006
`
`Sheet 11 of 17
`
`US 7,115,956 B2
`
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`
`LG Display Co., Ltd.
`Exhibit 1016
`Page 013
`
`

`

`U.S. Patent
`
`Oct. 3, 2006
`
`Sheet 12 of 17
`
`US 7,115,956 B2
`
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`LG Display Co., Ltd.
`Exhibit 1016
`Page 014
`
`

`

`U.S. Patent
`
`Oct. 3, 2006
`
`Sheet 13 of 17
`
`us 7,115,956 B2
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`
`LG Display Co., Ltd.
`Exhibit 1016
`Page 015
`
`

`

`U.S. Patent
`
`Oct. 3, 2006
`
`Sheet 14 of 17
`
`US 7,115,956 B2
`
`Fig. 14
`
`LG Display Co., Ltd.
`Exhibit 1016
`Page 016
`
`

`

`U.S. Patent
`
`Oct. 3, 2006
`
`Sheet 15 of 17
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`US 7,115,956 B2
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`LG Display Co., Ltd.
`Exhibit 1016
`Page 017
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`

`

`U.S. Patent
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`Oct. 3, 2006
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`Exhibit 1016
`Page 018
`
`

`

`U.S. Patent
`
`Oct. 3, 2006
`
`Sheet 17 of 17
`
`US 7,115,956 B2
`
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`LG Display Co., Ltd.
`Exhibit 1016
`Page 019
`
`

`

`US 7,115,956 B2
`
`1
`CONDUCTIVE FILM AS THE CONNECTOR
`FOR THIN FILM DISPLAY DEVICE
`
`BACKGROUND OF THE INVENTION
`
`2
`film. That is, there is provided such a structure in which the
`insulating film is formed between one of the source wiring
`and the gate wiring, which is formed of a first conductive
`film, and the other of the source wiring and the gate wiring,
`5 which is formed of a second conductive film.
`On the other hand, in a pixel structure in a light emitting
`device, three of a gate wiring (scanning line), a source
`wiring (signal line), and a current supply line each are
`patterned into a line shape. In this case, one of the source
`10 wiring and current supply line and the gate wiring is
`arranged in a row direction while the other is arranged in a
`column direction, and plural pixels are formed in a region
`surrounded by the source wiring, the current supply line and
`the gate wiring. Further, in order that both the wirings may
`15 not contact with each other at a portion where the wirings
`intersect with each other, the gate wiring and the source
`wiring and current supply line are respectively comprised of
`conductive films formed at different layers through an
`insulating film. That is, there is provided such a structure in
`20 which the insulating film is formed between one of the
`source wiring and current supply line and the gate wiring,
`which is formed of a first conductive film, and the other of
`the source wiring and current supply line and the gate
`wiring, which is formed of a second conductive film.
`However, application of such active matrix display
`devices (typically, liquid crystal display device and light
`emitting device) has been expanding, and the needs for high
`fineness, a high aperture ratio, and high reliability have been
`growing along with an increase in surface area of a screen.
`30 As a result, the needs for improvement in productivity and
`reduction in cost also have been growing.
`
`1. Field of the Invention
`The present invention relates to a semiconductor device
`having a circuit composed of a thin film transistor
`(hereinafter referred to as TFT) and a manufacturing method
`thereof. More specifically, electro-optical devices typified
`by liquid crystal display devices and light emitting devices
`having light emitting elements and also, electrical equip(cid:173)
`ment in which such devices are mounted as parts will be
`included in this category.
`2. Description of the Related Art
`In recent years, techniques of forming thin film transistors
`(TFTs) by using semiconductor films ( of about several to
`several hundreds of nm in thickness) formed on a substrate
`having an insulating surface have been attracting attention.
`Thin film transistors are widely applied to electronic devices
`such as ICs and electro-optical devices, and especially, the
`development thereof as switching elements for display
`devices is being hastened.
`Note that as display devices, liquid crystal display 25
`devices, light emitting devices and the like are known. In
`such display devices, driving methods such as passive
`matrix driving (simple matrix type) and active matrix driv(cid:173)
`ing (active matrix type) can be used. However, in the case
`where the pixel density is increased, the active matrix type
`in which a switch is provided for each pixel (or one dot) is
`SUMMARY OF THE INVENTION
`considered to be advantageous in that a low voltage driving
`can be conducted.
`The present invention has been made in view of the
`35 above, and therefore has an object to provide, in the manu(cid:173)
`In an active matrix liquid crystal display device, a display
`facture of a semiconductor device, a method that enables
`pattern is formed on a screen by driving pixel electrodes
`reduction in the number of manufacturing steps thereof and
`arranged in matrix. To be specific, a voltage is applied
`between a selected pixel electrode and an opposing electrode
`a structure for realizing the method, to thereby realize
`thereof, whereby optical modulation of a liquid crystal layer
`improvement in yield and reduction in manufacturing cost.
`arranged between the pixel electrode and the opposing 40
`In order to attain the above object, the present invention
`electrode is performed. Thus, the optical modulation is
`is characterized in that wirings, which are formed of two
`recognized as the display pattern by an observer.
`types of conductive films in the prior art, are formed of only
`one type of conductive film, thereby reducing the number of
`Further, an active matrix light emitting device that uses
`steps in the manufacture of a semiconductor device.
`organic electroluminescence has, in each pixel thereof, at
`least a TFT that functions as a switching element and a TFT 45
`Specifically, in the manufacture of a semiconductor
`that supplies a current to a light emitting element formed by
`device, wirings (source wiring, drain wiring, and the like),
`sandwiching an organic compound layer between a pair of
`which are respectively formed in a row direction and a
`electrodes, and utilizes light emission obtained through
`column direction on an element substrate, are formed of the
`recombination of carriers in the organic compound layer.
`same conductive film. In this case, one of the respective
`Note that the light emitting device is expected to be applied 50 wirings in the row direction and the colunm direction is
`discontinuously formed at a portion where the wirings
`to next-generation flat panel displays because of its features
`intersect with each other, and an insulating film is formed on
`such as thinness and lightness, high-speed responsibility,
`the wirings. Thereafter, a connection wiring for connecting
`and direct low-voltage drive. In particular, the light emitting
`the discontinuous wirings is formed of the same film as that
`device is considered to hold its superiority in a point that the
`device has a wider angle of view and excellent visibility
`55 for an electrode (hereinafter also referred to as first
`compared with a conventional liquid crystal display device.
`electrode) formed on the insulating film and through an
`opening portion ( contact hole) formed in the insulating film.
`In a pixel structure in a liquid crystal display device, three
`As a result, a continuous wiring can be obtained.
`of a gate wiring (scanning line), a source wiring (signal line),
`In this way, all the wirings can be formed by using only
`and a capacitor wiring each are patterned into a line shape.
`60 one type of conductive film. Thus, compared with the case
`In this case, one of the source wiring and the gate wiring is
`where the wirings are formed by using two types of con(cid:173)
`arranged in a row direction while the other is arranged in a
`ductive films laminated through an insulating film, the
`colunm direction, and plural pixels are formed in a region
`number of film deposition steps of a conductive film can be
`surrounded by both the wirings. Further, in order that both
`reduced, and in addition, the number of photolithography
`the wirings may not contact with each other at a portion
`65 steps in patterning can be reduced.
`where the wirings intersect with each other, the gate wiring
`and the source wiring are respectively comprised of con(cid:173)
`Further, the connection wiring for connecting discontinu(cid:173)
`ductive films formed at different layers through an insulating
`ously formed wirings can be formed of the same conductive
`
`LG Display Co., Ltd.
`Exhibit 1016
`Page 020
`
`

`

`US 7,115,956 B2
`
`15
`
`3
`film as that for forming the electrode through the same
`patterning step. Therefore, the connection wiring can be
`formed without an increase in the number of steps.
`According to the present invention, the source wiring is a
`wiring for inputting an image signal from a source side 5
`driver circuit to a source (source region) of a TFT formed in
`a pixel portion. The gate wiring is a wiring for inputting a
`signal, which is for selecting the TFT formed in the pixel
`portion, to a gate electrode from a gate side driver circuit.
`Further, the present invention is characterized in that the 10
`source wiring and the gate wiring are formed of the same
`material on the same surface at one time. In addition, as the
`occasion demands, a capacitor wiring and the like can be
`formed simultaneously with the source wiring and the gate
`wiring.
`Further, among the above wirings, the connection wiring
`for connecting discontinuously formed wirings is formed
`simultaneously with the electrode electrically connected
`with the TFT. That is, the TFT, all the wirings, and the
`electrode are formed without increasing the conventional
`number of steps.
`According to a structure of the present invention manu(cid:173)
`factured as described above, a semiconductor device is
`characterized by including: a semiconductor layer which has
`a source (source region), a drain (drain region), and a
`channel region ( channel formation region) as parts thereof;
`a gate insulating film formed on the semiconductor layer; a
`source wiring formed on the gate insulating film; a gate
`electrode which is provided on the gate insulating film and
`formed at a position where the gate electrode overlaps the
`channel region; an insulating film formed on the source
`wiring and the gate electrode; and a connection wiring and
`an electrode which are formed on the insulating film, in
`which: the connection wiring is formed in opening portions
`formed in the insulating film and in the gate insulating film,
`and establishes electrical connection between the source
`wiring and the source; and the connection wiring and the
`electrode are formed of the same material on the same film
`deposition surface.
`Further, according to another structure of the present
`invention, a semiconductor device is characterized by
`including: a semiconductor layer which has a source, a
`drain, and a channel region as parts thereof; a gate insulating
`film formed on the semiconductor layer; a source wiring
`formed on the gate insulating film; a gate electrode which is
`provided on the gate insulating film and formed at a position
`where the gate electrode overlaps the channel region; an
`insulating film formed on the source wiring and the gate
`electrode; and a connection wiring and an electrode which
`are formed on the insulating film, in which: the connection
`wiring is formed in opening portions formed in the insulat(cid:173)
`ing film and in the gate insulating film, and establish
`electrical connection between the source wiring and the
`source; the electrode is electrically connected with the drain;
`and the connection wiring and the electrode are formed of
`the same material on the same film deposition surface.
`Further, according to the present invention, in the case
`where plural island-like conductive films (gate lines), which
`are discontinuously formed, are to be formed into a con(cid:173)
`tinuous wiring, the island-like conductive films (gate lines)
`are electrically connected with the connection wiring, 60
`thereby forming the gate wiring.
`On the other hand, in the case where plural island-like
`conductive films (source lines), which are discontinuously
`formed, are to be formed into a continuous wiring, the
`island-like conductive films ( source lines) are electrically 65
`connected with the connection wiring, thereby forming the
`source wiring.
`
`4
`Further, in each of the above structures, examples of
`materials for forming the first electrode may include: ITO
`and IZO, which are transparent conductive films; elements
`such as gold (Au), platinum(Pt), nickel (Ni), tungsten (W),
`chromium (Cr), iron (Fe), aluminum (Al), tantalum (Ta), and
`titanium (Ti); and compounds of the above elements.
`Moreover, in each of the above structures, the electrode
`formed on the same surface as that for the connection wiring
`serves as the first electrode, an organic compound layer is
`formed on the first electrode, and further, a second electrode
`is formed on the organic compound layer. As a result, there
`can be formed a light emitting element including the elec(cid:173)
`trodes as a part thereof.
`That is, according to another structure of the present
`invention, a semiconductor device is characterized by
`including: first and second semiconductor layers each of
`which has a source, a drain, and a channel region as parts
`thereof; a gate insulating film formed on the first and second
`semiconductor layers; a source wiring and a current supply
`line which are formed on the gate insulating film; first and
`20 second gate electrodes which are provided on the gate
`insulating film and respectively formed at positions where
`the first and second gate electrodes overlap the channel
`regions of the respective first and second semiconductor
`layers; an insulating film formed on the source wiring, the
`25 current supply line, the first gate electrode, and the second
`gate electrode; plural connection wirings and a first elec(cid:173)
`trode which are formed on the insulating film; an organic
`compound layer formed on the first electrode; and a second
`electrode formed on the organic compound layer, and the
`30 semiconductor device in which: the plural connection wir(cid:173)
`ings are formed in opening portions formed in the insulating
`film and in the gate insulating film, and establish electrical
`connections between the source wiring and the source of the
`first semiconductor layer, between the drain of the first
`35 semiconductor layer and the second gate electrode, and
`between the current supply line and the source of the second
`semiconductor layer; the first electrode is electrically con(cid:173)
`nected with the drain of the second semiconductor layer; and
`the connection wirings and the first electrode are formed of
`40 the same material on the same film deposition surface.
`Further, according to the present invention, particularly in
`the case where the transparent conductive film such as ITO
`or IZO is used, it is preferable that wet etching is used as a
`method of patterning the connection wiring and the first
`45 electrode. This is because the characteristics of the TFT,
`which is previously formed, are not influenced by plasma
`damage in the case of using dry etching. Note that it is
`particularly effective that wet etching is adopted in the case
`where the insulating film, which is formed between the TFT
`50 and the connection wiring and first electrode, is formed of an
`organic insulating material.
`Further, according to the present invention, there is pro(cid:173)
`vided a method of manufacturing a semiconductor device
`having the above structures, characterized by including:
`55 forming a semiconductor layer on an insulating surface;
`forming a gate insulating film on the semiconductor layer;
`forming a source wiring on the gate insulating film; forming
`a gate electrode on the gate insulating film and at a position
`where the gate electrode overlaps a part of the semiconduc(cid:173)
`tor layer; forming a source and a drain through doping of
`impurities into the semiconductor layer with the gate elec-
`trode serving as a mask; forming an insulating film to cover
`the gate electrode and the source wiring; forming a connec(cid:173)
`tion wiring and an electrode, which are formed of the same
`material and on the same film deposition surface, on the
`insulating film; and electrically connecting the source wiring
`with the source through the connection wiring.
`
`LG Display Co., Ltd.
`Exhibit 1016
`Page 021
`
`

`

`US 7,115,956 B2
`
`5
`
`5
`Further, according to another structure of the present
`invention, a method of manufacturing a semiconductor
`device is characterized by including: forming a semicon(cid:173)
`ductor layer on an insulating surface; forming a gate insu(cid:173)
`lating film on the semiconductor layer; forming a source
`wiring on the gate insulating film; forming a gate electrode
`on the gate insulating film and at a position where the gate
`electrode overlaps a part of the semiconductor layer; form(cid:173)
`ing a source and a drain through doping of impurities into
`the semiconductor layer with the gate electrode serving as a
`mask; forming an insulating film to cover the gate electrode
`and the source wiring; forming a connection wiring and an
`electrode, which are formed of the same material and on the
`same film deposition surface, on the insulating film; elec(cid:173)
`trically connecting the source wiring with the source through 15
`the connection wiring; and electrically connecting the elec(cid:173)
`trode with the drain.
`Further, in each of the above structures, it is characterized
`in that the connection wiring and the electrode are formed by
`wet etching.
`
`60
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`Embodiment modes of a semiconductor device of the
`present invention will be described below.
`
`30
`
`6
`Semiconductor devices according to the present invention
`include liquid crystal display devices and light emitting
`devices, and in any case, an element substrate is formed with
`a structure in which plural thin film transistors and elec-
`trodes are provided on a substrate. In the case of the liquid
`crystal display device, an opposing substrate is bonded to the
`element substrate with a predetermined gap therebetween
`and an electro-optical substance (liquid crystal material,
`etc.) is provided in the gap, whereby a liquid crystal panel
`10 is formed. In the case of the light emitting device, a light
`emitting element is formed by laminating an organic com(cid:173)
`pound layer and a second electrode on an electrode (first
`electrode) of the element substrate, whereby a light emitting
`panel is obtained.
`According to the present invention, a connection structure
`of wirings can be formed which is as shown in FIGS. lA to
`lC or FIGS. 2A to 2C.
`FIGS. lA to lC show a structure that includes a TFT, a
`source wiring, a gate wiring (including a gate electrode), and
`20 a first electrode electrically connected with the TFT, which
`are formed on a substrate. The present invention is charac(cid:173)
`terized in that the above structural elements are formed of
`only two types of conductive films and connected with one
`another. Note that FIG. lB is a sectional view taken along a
`broken line X-X' in a top view of FIG. lA, and FIG. lC is
`a sectional view taken along a broken line Y - Y' in the top
`view of FIG. lA.
`As shown in FIG. lB, a semiconductor layer 204, which
`forms a source 202 and a drain 203 of the TFT, is formed on
`a substrate 201. Then, on the semiconductor layer 204, a
`source wiring 206 and a gate line 207, which are formed of
`a first conductive film, are formed on a gate insulating film
`205 by performing patterning. Note that the source wiring
`206 is formed in line so as to be electrically connected with
`all the pixels formed in a colunm direction in a pixel portion
`of the element substrate although this is not shown in the
`figure. On the other hand, the gate line 207 is formed to have
`an island shape and independently for each pixel. Further,
`the portion which is a part of the gate line 207 and which
`overlaps the semiconductor layer 204 corresponds to a gate
`electrode 212 of a TFT 214.
`Further, connection wirings 209 and 210 and a first
`electrode 211, which are formed of a second conductive
`film, are formed on the source wiring 206 and the gate line
`207 through an insulating film 208 by performing pattern-
`ing.
`The connection wiring 209 electrically connects the
`source wiring 206 with the source 202 through contact holes
`50 (not shown in the figure) formed in the insulating film 208
`as shown in FIG. lB, and also, the connection wiring 210
`establishes electrical connection with respect to the gate
`lines 207, which are formed into plural island shapes,
`through contact holes as shown in FIG. lC. Thus, electrical
`55 connection of the island-like gate lines 207 is established
`with the connection wiring 210, whereby a gate wiring 213
`is formed. Further, the gate wiring 213 is electrically con(cid:173)
`nected with all the pixels formed in the colurmi direction in
`the pixel portion of the element substrate.
`Further, FIGS. 2A to 2C show a case where source lines,
`which are formed of a first conductive film and are formed
`in island shapes, are in contact with connection wirings
`formed of a second conductive film, differently from the
`case of FIGS. lA to lC. Note that FIG. 2B is a sectional
`65 view taken along a broken line X-X' in a top view of FIG.
`2A, and FIG. 2C is a sectional view taken along a broken
`line Y-Y' in the top view of FIG. 2A.
`
`BRIEF DESCRIPTION OF THE DRAWING
`In the accompanying drawings:
`FIGS. lA to lC are views for explaining a connection
`relationship among wirings according to the present inven- 25
`tion;
`FIGS. 2A to 2C are views for explaining a connection
`relationship among wirings according to the present inven(cid:173)
`tion;
`FIG. 3 is a view for explaining an element substrate that
`is manufactured according to the present invention;
`FIGS. 4A to 4C are sectional views for explaining manu(cid:173)
`facturing steps of the element substrate;
`FIG. 5 is a top view for explaining a manufacturing step
`of the element substrate;
`FIG. 6 is a top view for explaining a manufacturing step
`of the element substrate;
`FIG. 7 is a top view for explaining a manufacturing step
`of the element substrate;
`FIG. 8 is a view for explaining an element substrate that
`is manufactured according to the present invention;
`FIGS. 9A to 9D are sectional views for explaining manu(cid:173)
`facturing steps of the element substrate;
`FIG. 10 is a top view for explaining a manufacturing step
`of the element substrate;
`FIG. 11 is a top view for explaining a manufacturing step
`of the element substrate;
`FIG. 12 is a top view for explaining a manufacturing step
`of the element substrate;
`FIG. 13 is a view for explaining an element substrate that
`is manufactured according to the present invention;
`FIG. 14 is a view for explaining an element substrate that
`is manufactured according to the present invention;
`FIG. 15 is a view for explaining a liquid crystal display
`device that is manufactured according to the present inven(cid:173)
`tion;
`FIGS. 16A and 16B are views for explaining a light
`emitting device that is manufactured according to the
`present invention; and
`FIGS. 17A to 17H are diagrams showing examples of
`electric equipment.
`
`35
`
`40
`
`45
`
`LG Display Co., Ltd.
`Exhibit 1016
`Page 022
`
`

`

`US 7,115,956 B2
`
`8
`cally connected with the capacitor wmng 116 with an
`insulating film (gate insulating film), which covers the
`semiconductor layer 105, serving as a dielectric.
`According to the present invention, there can be set as
`equal to five the number of masks necessary for forming the
`element substrate that includes the pixel portion having the
`pixel structure shown in FIG. 3 and the driver circuit. That
`is, the first mask is for patterning the semiconductor layer
`105; the second mask is for patterning the source wiring 109,
`the capacitor electrode 108, and the island-like gate line 118;
`the third mask is for covering the n-channel TFT in doping
`of impurities imparting p-type conductivity for the forma(cid:173)
`tion of the p-channel TFT of the driver circuit; the fourth
`mask is for forming contact holes that respectively reach the
`15 semiconductor layer 105, the island-like gate line 118, and
`the source wiring 109; and the fifth mask is for patterning the
`first electrode 113, the connection wirings 114 and 115, and
`the capacitor wiring 116.
`As described above, the element substrate can be formed
`20 with a small number of masks in the case of the pixel
`structure shown in FIG. 3.
`
`Embodiment Mode 2
`
`7
`Similarly, a semiconductor layer 304, which forms a
`source 302 and a drain 303 of a TFT, is formed on a substrate
`301. Then, on the semiconductor layer 304, a source line 306
`and a gate wiring 307, which are formed of the first
`conductive film, are formed through a gate insulating film 5
`305 by performing patterning. Further, the portion which is
`a part of the gate wiring 307 and which overlaps the
`semiconductor layer 304 corresponds to a gate electrode 312
`of a TFT 314. Note that the gate wiring 307 is formed in line
`so as to be electrically connected with all the pixels formed 10
`in a row direction in a pixel portion of the element substrate
`although this is not shown in the figure. On the other hand,
`the source line 306 is formed to have an island shape and
`independently for each pixel.
`Further, connection wirings 309 and 310 and a first
`electrode 311, which are formed of a second conductive
`film, are formed on the source line 306 and the gate wiring
`307 through an insulating film 308 by performing pattern-
`ing.
`The connection wiring 309 electrically connects the
`source line 306 with the source 302 through contact holes
`(not shown in the figure) formed in the insulating film 308
`as shown in FIG. 2B, and also