`
`THIN FILM TRANSISTORS
`
`MATERIALS AND PROCESSES
`
`VOLUME 2: POLYCRYSTALLINE SILICON
`THIN FILMTRANSISTORS
`
`edited by
`
`YUE KUO
`
`LG Display Co., Ltd.
`LG Display Co., Ltd.
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`
`

`

`
`
`LG Display Co., Ltd.
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`

`

`
`
`THIN FILM TRANSISTORS
`
`Materials and Processes
`
`Volume 2
`Polycrystalline Silicon Thin Film
`Transistors
`
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`

`

`
`
`THIN FILM TRANSISTORS
`
`Materials and Processes
`
`Volume 2
`Polycrystalline Silicon Thin Film
`Transistors
`
`edited by
`
`Yue Kuo
`Texas A&M University, U.S.A.
`
`we
`
`KLUWER ACADEMIC PUBLISHERS
`Boston / Dordrecht / New York / London
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`a i
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`Thin Film Transistors — Materials and Processes
`Volume 1 — Polycrystalline Silicon Thin Film Transistors
`Edited by Yue Kuo
`ISBN — Vol 2 — 1 4020 7506 5
`ISBN — 2 —vol Set 1 4020 7504 9
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`

`

`TER FOURa TFT Structures
`
`ryoicht Ishihara
`
`1.
`
`INTRODUCTION
`
`This chapter focuses onstructuresof poly-Si TFTs, which have been
`widely used for active matrix display and static random access memory
`(SRAM). First, basic structures of poly-Si TFTs will be addressed. This
`includes the fundamental configuration of semiconductors,
`insulators, and
`electrodes in the TFTs. A wide variety of poly-Si TFT structures have been
`studied so far. Depending on the process (low- or high-temperature) and
`application (large or small area flat panel display, or SRAM), a suitable TFT
`structure differs. For each structure, basic advantages and disadvantages,
`process flow, and cost issue will be described.
`Secondly, various
`structures controlling an electric field near
`drain/channel junction will be reviewed. The off-current of poly-Si o
`referred to as leakage current, is generally higher than thatof a-Si aia .
`to field emission via grain boundary traps in the drain depletion re Soke
`high conductivity ofthe channel. In orderto apply the poly-Si ae apike
`matrix circuits, suppression of the high leakage current by re ts pe dit
`Clectric field in the drain region is very important. Thea ression of
`lield is also effective in improving the circuit reliability Seine a
`impact ionization of carriers in the saturation regime. Prpo
`‘it electrical characteristics will be introduced.
`‘
`estigators
`Finally, novel TFT structures will be reviewed. Nt
`Sj TFT
`.
`poly
`:
`ing
`have reported innovative structures aimed at
`improving
`
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`146
`
`Poly-Si
`
`TFT,
`
`erformance. Advanced process technologies, such as re Mechanica
`: lishing (CMP), silicidation, and pulsed-laser crystallization, enable th,
`fabrication of new TFT structures. Their unique electrical characteristic, hy
`technical constraints will be discussed.
`
`2.
`
`BASIC TFT STRUCTURES
`
`2.1
`
`TFT Components
`
`2.1.1
`
`Basic Arrangment of TFT Components
`
`The most important feature of TFTs is that they can be formed on
`insulating materials, which include glass substrates and insulating layers
`isolated from the existing devices below. This feature allows high optical
`transparency of the device, use of a larger sized substrate than thosepossible
`with Si wafers,
`and 3D integration of semiconductor devices. The
`conventional TFTsconsist of three electrodes of source, drain and gate, gate
`insulator, and thin semiconductor layer. These elements can be arrangedin
`many ways.
`Thefirst major structural distinction in the TFTsis the arrangementof
`the electrodes:
`
`1, Coplanar: The source and drain electrodes are located at the same
`side as the gate electrode.
`2. Staggered: The source anddrain electrodesare locatedat the opposite
`side to the gate electrode separated with the semiconductor layer.
`ésa second major distinction of the TFT is the level of the gate
`.oe The gate electrode is located above the semiconductor
`2. Bottom t *
`‘
`ties Sate: The gate electrode is located below the semiconducto”
`four iu‘ = distinctions, the basic TFT structures are divided ™"°
`ys TFTs andbulk MOSFETsarefabricated, as follow’:
`
`|
`
`LG Display Co., Ltd.
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`Exhibit 1007
`Exhibit 1007
`Page 007
`Page 007
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`1,
`
`Wi
`
`Be
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`

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`;
`
`poly! ee
`
`ctures
`
`147
`
`Planar (d)
`
`Figure 1. Basic poly-Si TFT structures are shown of(a) top gate, planar; (b) top gate,
`staggered; (c) bottom gate, planar and (d) bottom gate, staggered. The TFTsare n-channel.
`
`2.1.2 Device Isolation
`
`Unlike the bulk MOSFETs, TFTsareelectrically isolated from each
`other by forming the island,
`i.e., by completely etching off the thin
`semiconductor layer from the device-nonactive area. This yields a complete
`electrical isolation of the device and increases in the non-TFT area, which is
`limited for most applications.
`
`21.3
`
`Source and Drain Regions
`
`Poly-Si TFTs need the drain and source regionsof a heavily doped
`poly-Si for their unipolar operation. For n-channel TFTs, when the positive
`gate bias is applied to the gate, electrons accumulate at the interface andform
`the channel from the source to drain. When the negative gate biasis applied to
`the gate, holes accumulate at the interface to form field-induced pn junctions
`between the channel edge and both drain and source regions. The depletion
`regions at source and drain prevent carriers flowing from both sides of the
`channel and the source and drain. In this way, the source and drain regions
`
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`=
`
`148
`
`Poly-§j TFT,
`select the carriers. The drain and source regions needto be heavily q
`form ohmic contacts betweenthe electrode andtheSj layer.
`
`"Ped to
`
`2.1.4
`
`Formation of Drain and Source Region
`‘The drain and source regions can be fabricated in two ways:(|)
`deposition of doped Silayer or (2) introduction into the poly-Si layer,
`The first approach,
`the deposition of the doped Si
`layer, has the
`advantage of doping a large doped area in a simple step. This is the same as
`the fabrication of a-Si TFTs in LCDs, which involves the deposition of
`heavily doped a-Si layers' for the source and drain regions (called ohmic.
`layer). If the doped Si layer is used, the source and drain regions cannot be
`formed just beside the channel. Instead, they are formed atop or below the
`channel region, as shown in Figure 4. For the staggeredstructure, this means
`that
`the carriers must first cross the channel
`layer vertically,
`then flow
`laterally through the channel, andfinally cross vertically through the channel
`layer to the contact region. Since the channel is undoped, and thus, has high
`resistance,
`the vertical current-paths create an extra parasitic resistance.
`Therefore, an advantageofthe planar structure over the staggeredis thatthere
`is no such parasitic resistance. The doped poly-Si layer can be formed byan
`in-situ doping process in which dopants are introduced during the deposition
`of the poly-Si. The process, however, may require a high temperature, of
`which glass substrates cannot be tolerant. Recrystallization of the heavily
`doped a-Si
`layer, e.g., by excimer-laser crystallization, can lower the
`formation temperature. It is difficult to fabricate CMOS configuration with
`the method of depositing the dopedlayer, since local deposition ofthe heavily
`doped regionsis very difficult.
`In the latter approach,i.e., doping impurity into undoped poly-Si, the
`, source and drain contacts can be formed just beside the channel region. As in
`the bulk Si MOSFET, by doping local area, CMOSconfiguration can also z
`easily obtained. The classical thermal diffusion of impurity atoms with =
`furnace drive-in generally requires a high temperature and thus, restricts ne
`application to the high temperature substrate. Pulsed-laser irradiation a :
`either a solid” or gaseous’ diffusion source can preventthe thermal decree
`the substrate because of the short pulse duration and hence short hie
`diffusion length. The doping can also be done by eeeae :
`technique, however, mightbedifficult over a large area due to the =e a
`small beam size and hencethe low throughput. The dopant mennnes ee
`a high temperature, which can be lowered, however, by e F —isplay
`
`LG Display Co., Ltd.
`Co.,
`Ltd.
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`Poly-Si TFT
`-Si
`
`Stru
`
`Structures
`
`149
`
`irradiation’ or rapid thermal annealing (RTA). Recently, the development of
`non-mass separated ion-shower doping technique* (hereafter referred to as
`ion-doping) can overcome the problem of ion-implantation. The technique
`uses a large beam size and henceis proper for doping a large area. Also,
`the
`ion-doping lowers the activation temperature of impurity atoms. Detailed
`discussions of the performance process and related issues are included in
`other chapters of this book.
`
`2.1.5 Top- vs. Bottom-Gate
`
`A fundamental difference in the fabrication process between these
`two structuresis that, for the bottom gate structure, a semiconductor layer and
`gate insulator layer can be formed continuously without breaking vacuum.For
`the top gated structure,
`the continuous formation is not possible, since
`semiconductor islands should be patterned before the gate oxide formation
`because the islands have to be electrically isolated from the gates by oxide
`sidewall formation. The bottom gate structure can easily form a clean and
`stable Si/gate insulator interface, while the top gate needs extra care when
`cleaning the semiconductor surface. This unique feature of the bottom gate
`structure madeit very attractive, especially for a-Si TFTs, as it is generally
`difficult to obtain a clean a-Si/gate insulator (SiN,) interface. The advantageis
`applicable to poly-Si TFTs, as well.
`
`2.1.6 Gate-Drain Self-Alignment
`
`The edges ofthe gate electrode and the edges of the drain and source
`regions are preferably aligned. If these are separated far from each other, a
`high parasitic resistance will be formedin thesilicon between these lines. The
`_parasitic resistance lowers the output current. If these regions are overlapped,
`the extra capacitance associated with the overlap will be created. The
`capacitance will deleteriously affect circuit performance in high-speed
`operation due to the increase in RC delay. In contrast, the self-alignment
`allows oneto align automatically the gate edge to the drain and source; hence,
`no parasitic resistance or capacitance is found. This self-alignmentstructure
`also reduces the devicesize.
`
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`150
`
`2.2.
`
`Top Gate TFTs
`
`Poly-Si TET,
`
`.
`
`7
`
`y
`
`.
`
`Historically, the first FET proposed by Oscar Heil in 1935° alreag
`had,in fact, the top gate TFT structure with the tellurium semiconductor film
`Trial and error with experiments of the FETsled to the invention ofbipolar
`transistors in 1945. FETs remained an oddity until the invention ofthe Si
`planar process (MOS) in 1960. When the materials and quality of MOSFET,
`were improved, there were intensive studies on TFTs. Manyresearchers haye
`developed various poly-Si formation techniques, such as direct deposition by
`LPCVD,’ solid phase crystallization (SPC)° and grapho-epitaxy,” that have
`been used to fabricate poly-Si TFTs.'*'" At
`that period,
`the top gate
`structure was the most popular structure. This was because the fabrication
`technologies for bulk MOSFETs,
`such as thermal oxidation and ion-
`implantation, could be used. The first production of active-matrix addressed
`LCDsfor pocket TV, which appeared in 1984,'’ used not the a-Si TFTs but
`the top gate poly-Si TFTs with the high temperature process. Sincethelate
`1980s, low temperature poly-Si crystallization methods, such as excimer-laser
`crystallization'* or metal
`induced crystallization,'*'® have been developed
`which made poly-Si TFTson large glass substrate feasible. Based on the low-
`temperature process, large sized, driver-integrated LCDs have been in mass
`production using the top gate poly-Si TFTs.'’ Detailed discussions on the low
`temperature poly-Si formation processes can be found in Chapters 5, 6, 10,
`and 12 of this book.
`
`2.2.1 Coplanar (Self-Aligned)
`
`The top-gate, coplanar TFT structure is most commonly used among
`the poly-Si TFTs. As shown in Figure 2,first, the poly-Si layer is formed on
`top of the substrate and then is patternedinto islands by photolithography and
`‘etching steps. Then, gate oxide and metal
`layers are deposited. After
`patterning the metal into the gate (in some cases, the gate oxide on top of the
`source and drain regions is also removed), impurity ions are doped by non
`mass separated ion-shower doping or ion-implantation. Here, the gate can be
`used as a mask during doping so that the source and drain regions are seli-
`aligned with respect to the channel edge. Theself-alignment capability 's the
`most importantfeature ofthis structure. The TFT is complete after passivation
`oxide deposition, contact hole opening and gate metal deposition/pattern!ne:
`A possible drawback of the TFT structure is that the Si surface must be
`carefully
`cleaned
`before
`the
`formation of
`the
`gate
`oxide,
`since
`photolithography and etching steps mustbe used to form the Si islands.
`LG Display Co., Ltd.
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`Page 011
`Page 011
`
`

`

`poly-Si TFT S
`
`tructures
`
`151
`
`foramen|ee
`
`CLL ST]
`
`
`
`
` aa)
`ia
`fee)iteee
`pSaeoT
`
`
`
`
`
` i
`
`Figure 2. Fabrication process flow for top gate, coplanar poly-Si TFTs.
`
`2.2.2. Channel-Etched Coplanar (NonSelf-Aligned)
`
`The main feature of this type of coplanar TFT,'*’’ schematically
`shown in Figure 3, is the deposited ohmic-layer, instead of the ion-implanted
`region, which acts as the source and drain regions in the coplanar structure.
`First, the undoped a-Si and doped a-Si layer are deposited by PECVD. The
`doped-a-Si on the channel region is then removed. Successively, both the
`undoped- and doped-a-Si are crystallized into the poly-Si at the same time,
`e.g., by excimer-laser crystallization. Then, islands for undoped-poly-Si and,
`at the same time, the source and drain regions are patterned. The gate oxide
`deposition, contact opening, electrodes formation follow afterwards.
`An advantageof this kind ofstructure is that the ohmic-layer can be
`easily deposited over the large area substrate. One ofthe disadvantages, apart
`from the difficulties in the fabrication of CMOSconfiguration and the non
`self-aligned structure,
`is the difficulty in obtaining a high etch selectivity
`between the doped andintrinsic silicon films. Although the created damageat
`the channel surface can be removed after the crystallization process,
`the
`thickness variation of the active channelstill remains. Furthermore, the thick
`doped-Si/undoped-Si region will not be fully crystallized because the energy
`density of excimer-laser is determined for the thin undoped-Si. This energy
`LG Display Co., Ltd.
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`152
`
`Poly-Si TFTs
`
`ick doped-Si/undopedSi stack
`’
`timum and too low for the thic
`idope
`acked
`j
`ty
`cen eieeiie small grain size of the doped-poly-Si region will be
`ESEee
`gh series resistance.
`expected, and hence, create a hi
`:
`It should be added that the source and drain region can also be formed
`oS
`ly-Si or solid-phase crystallizat;
`direct deposition of doped poly
`ie
`“her
`by
`cae ofthe doped a-Si film2° A high process temperature, however,restricts
`the application.
`
`Tes
`
`3 |pre
`
`.
`
`Figure 3. Schematic cross-section of top gate, coplanar poly-Si TFTs with channeletch.(After
`Kuriyama etal., Ref. 18. © 1991 IEEE.) Staggered (Non Self-Aligned)
`Top gate, staggered TFT structure is depicted in Figure 4.7" In this
`TFT process, first, a high-temperature resistant metal (such as WSifilm) and
`a doped Si layer are deposited and patterned into source and drain regions.
`Then, the a-Si layer is deposited by PECVD andcrystallized by excimer-laser
`into poly-Si. The poly-Si layer is then patterned into islands. The TFT is
`complete after gate oxide deposition, contact hole opening, gate metal
`deposition and patterning. The structure provides low leakage currentsinceit
`has a vertical offset where the channel and drain overlap; thereby, the drain
`electric field is reduced. One drawbackofthis structure, apart from the non-
`eee configuration,is that the bottom metal may be damaged during
`crystallization, since the metalwill be heated to a very high temperature.
`cee the damage, the laser irradiation condition should be carefully
`
`
`
`Figure 4. Schematic cro
`21. © 1989 IEEE)
`
`;
`‘
`Ss-section oftop gate, staggered poly-Si TFTs. (After Seraet al., Ref.
`
`LG Display Co., Ltd.
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`Poly-Si TFT Structures
`
`153
`
`2.2.3
`
`Semi-Staggered (Non Self-Aligned)
`
`In this structure,””” as shown in Figure 5, a heavily dopeda-Siisfirst
`formed and patterned. An intrinsic a-Si is then deposited and recrystallized
`e.g., by excimer laser. Here,
`impurities in the heavily doped a-Si
`film
`incorporate throughout the entire undoped Si aboveit, since both undoped-
`and doped-a-Si are conventionally thin (~50 nm). Thereby, the n*-region can
`be formed adjacent to the channel edge, hence the name, “semi-staggered.”
`This feature lowers the series resistance. Before the poly-Si island formation,
`the gate oxide is deposited without breaking vacuum. Then, both poly-Si and
`gate oxide are patterned intothe island. To protect the shortage betweenpoly-
`Si and the gate, an additional gate oxide needs to be deposited. The process is
`complete after gate metal formation, contact opening, and source and drain
`metal formation. In this TFT structure,the poly-Si/gate oxide interface can be
`formed without breaking the vacuum, and hence, a clean interface can be
`obtained. A possible drawback, apart from the non self-alignment structure
`and the requirement of two gate oxides, is that there might be contamination
`and defect formation between the two gate oxides, which will deteriorate the
`devicestability.
`
`aa
`
`Substrate
`
`es—_ rain
`
`Figure 5. Schematic cross-section of top gate, semi-staggered poly-Si TFTs. (After Sekiyaet
`al., Ref. 22. © 1994 IEEE., after Kohnoetal., Ref. 23. © 1995 IEEE.)
`
`‘2.3.
`
`Bottom Gate TFTs
`
`The bottom gate TFT structure is the most common configuration for
`a-Si TFTs. It is often referred to as the inverted-staggered structure. This is
`because the a-Si film can be deposited immediately after SiN, deposition
`without breaking vacuum.If SiN, film is deposited after the a-Si film, such as
`in the top gate structure, the SiN, process deposition deteriorates the interface,
`since it generally requires a higher deposition temperature and a high plasma
`power. The bottom gate TFT contains a clean a-Si/SiN,
`interface and
`
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`

`154
`
`Poly-Si TFTs
`
`adva
`
`larger electron mobility than the
`top
`;
`se
`il
`top gate TFT. Th
`shinsthebotnet TFT structure widely accepted in a-Si TFT-
`LCDdesign, despite the unusual upside-down structure.
`e of the development of the low-temperature poly-S;
`TFTs ieoe also widely studiedbecause the excimer-laser
`crystallization was taken as an additional process step to the a-Si TFTs. In this
`sense, the bottom gate poly-Si TFTsare attractive because the a-Si TFT pixels
`and poly-Si TFT drivers can be prepared in a few simple Steps. Moreover,
`with the bottom gate poly-Si TFTs, the existing production infrastructure and
`the expertise for a-Si TFTs can beutilized. Indeed, the first production of the
`poly-Si TFT driver integrated LCDs with the excimer-laser crystallization
`method wasbased on the bottom gate TFT structure.
`
`The bottom gate structure is used also for integrated circuit, mainly by
`SRAM,” for a number of reasons. The structure allows sharing the gate
`between the bottom MOSFETsand top TFTs. This increases the integration
`density, improves the topography, reduces the number oflevels, and thereby
`simplifies fabrication in the sub-micrometer regime. Thestructure will be also
`indispensable in 3D integration because of interconnection restraint. Detailed
`discussions on the poly-Si TFT applications in VLSI can be found in chapter
`13 of this book.
`
`Inverted-Staggered with Channel Etching (NonSelf-Aligned)
`2.3.1
`The “channel etching”typeofthe inverted-staggered poly-Si TFTsis
`ch
`:eat te 6. First, a metal
`layer,
`typically Molybdenum (Mo) or
`faerie! ( oe can stand subsequent process steps, is deposited and
`ela a = Bate electrode. After the metaletching step, the gate oxide
`sretnrintallines “sposited without breaking the vacuum. Then,
`the a-Si
`is
`opened. Then‘%e ploe patterned into islands. The contact to gate is
`source and drain deatredes film and metal are deposited and patterned into
`
`the channelis thin (less than ~100 nm),
`and thus, introduces instability inei will cause carrier trapping;
`vely etching the doped|
`Operation. Due to the difficulty in
`layer is recuiredfe eae the two Si layers, a relatively thick
`
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`_Sj TFT Structures
`Poly-S!
`
`155
`
`the thermal and mechanical
`is anticipated that
`it
`Furthermore,
`damages could be generated in the bottom metal
`layer during laser
`crystallization. The metal can be heated up to a very high temperature
`pecause the gate oxideis typically thinner than the heat diffusion length (~250
`nm)’’ of the excimer-laser crystallization process.
`The metal layer also induces a fast heat transfer from Si and thus
`influences
`the
`crystallization
`characteristics.
`In
`the
`excimer-laser
`crystallization process, there exists an optimum energy density range where
`silicon crystallizes with the largest grain size. The optimum energy density
`range for the silicon above the gate metal is higher than the surroundings due
`to the fast heat transfer towards the metal. On the other hand, a higher energy
`density will results in a small grain size in the surroundings. Furthermore,
`even with the optimum energy density range, the fast heat transfer towards the
`gate metal results in the fast grain growth, and hence, deterioration of crystal
`quality. With such conditions, the grain size and grain quality across the poly-
`Si will be non-uniform.In order to obtain a uniform distribution, one must use
`a lowered energy density, with which only the mediumsize of grains can be
`obtained. Consequently, the field effect mobility of the bottom gate poly-Si
`TFT is generally smaller than that of the top-gate structure.
`
`
`
`Figure 6. Schematic cross-section of the inverted staggered poly-Si TFT structure with channel
`etch process.
`
`2.3.2
`
`Imverted-Staggered with Channel Protective Film (Non Self-
`Aligned)
`
`the over etching of the
`In thistype of inverted staggered TFTs,
`channelpoly-Siis prevented by a protective film (“etch-stopper”) onit.2? This
`TFT structureis often referred to as tri-layer type inverted staggered. The
`process flow is shown in Figure 7. First, the gate electrode is formed by a
`metal, typically Mo or Ta, which can stand the subsequent process steps.
`
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`156
`
`Poly-Si TFTs
`
`re deposited by
`FEC
`by
`the excime
`;
`PECVD-without breaking
`depos!
`ide and a-Si layers are
`oly-Si, e.g.,
`by
`the
`T-
`Then, gate owa-Si is then recrystallized ne ie is then deposited and
`the aisa method. Either peteogi ahanviel region. The channe|
`hich define
`. 30
`:
`en
`laser crys
`patterned ae on sitsynatively be a highly eee . alate ce
`;
`lands, w
`-Si.” Also,
`these
`es aefilms can be formed before the Sifilmis deposited over
`chan reg the
`gate is then opened. A doped = se
`:
`The source and
`eeed iscrystallized Ey exertenero mask. The
`ree foetied also by ion-implantation using ae e The n* layer and
`eee aie lete after the metal deposition and etc ms.
`the
`same mask
`
`theintrinsicpoly-Sicanbe simultaneously etched using. the Pea
`
`the intrinsic poly-Si can
`1
`protection layer,
`the last n*
`an
`Because of the presence of the channel p
`do Therefore:
`thickiise: af
`intrinsic poly-Si
`laye
`value for the poly-Si TFTs.
`ate
`i layer can be extensively over-etched.
`os
`the active Si layer can beset as an optimum
`
`
`
`
`
`an os =
`
`
`Beetsshame) epee og Sourceancdrain
`
`
`eens tepyee Poly-Siisiand
`
`Figure 7. Fabricat
`ion process flow for inverted, Staggered poly-Si TFTs with channel protective
`film. (After Gosa
`in et al., Ref. 29.@ 1994 JSAP.)
`Inverted-Stagseredwith ChannelProtective Film (Self-Aligned)
`2.3.3
`The bottom gate TFT struc
`Self-aligned, However, Self-align
`tures mentioned so far are obviously not
`Protective film, as follows, The channel protective film is followed by a
`ment can be achieved by a self-aligned
`Positive photoresist Coating, which is irradiated with UV light from the
`backside ofthe glass substrate, using the
`gate pattern can be transcribedto the phot
`Bate electrode as a mask,*’ Here, the
`totheprotective filmafteretching, Then, doped Si layer can be deposited.In
`Oresist after development andfinally
`
`LG Display Co., Ltd.
`LG Display Co., Ltd.
`Exhibit 1007
`Exhibit 1007
`Page 017
`Page 017
`
`

`

`_Si TFT Structures
`
`Poly
`
`157
`
`this way, the source and drain can be formed with a self-aligned manner,?2
`The self-aligned protective film can be used as a mask for ion doping,” In this
`case, even lightly doped source and drain (LDD)regionscan be automatically
`formed adjacent to the channel where the dopant density per unit area is
`lowered by the sloped surface with respect to the ion beam, as shown in
`Figure 8.
`It should be noted that
`the back illumination requires a UV
`transparent glass wafer and an opaque metal. The selection of glass and
`masking metal will be limited by their material properties. The proximity
`effect in performing the backside lithography throughathick substrate also
`limits the accuracy of the pattern transfer from the gate pattern.
`
`
`
`Figure 8. Schematic cross-section of the inverted, staggered poly-Si TFT with self-aligned
`LDD.(After Hayashiet al., Ref. 33. © 1995 IEEE.)
`
`2.3.4
`
`Inverted-Staggered with CMP (Self-Aligned)
`Another self-aligned inverted-stagger structure is shown in Figure 9.”
`After gate metal
`formation and gate insulator deposition, a-Si
`film is
`deposited. The a-Si layer is heavily doped by boron ion implantation. At this
`time, lightly doped regions are formed adjacentto the gate because the surface
`of the a-Si layer is tilted there. The wafer is then chemical mechanical
`polished (CMP) down to the gate insulator, which acts as a stopper. Thina-Si
`is subsequently deposited and recrystallized by methods, such as the nickel
`(Ni)
`induced crystallization method. The metal-induced crystallization
`Process can be found in Chapter 6 of this book. Finally, the fabrication is
`complete after several processes, such as contact opening and metallization.
`With this structure, the self-aligned lightly doped drain region Is achieved.
`There are a number ofissues to be solved in this structure. The use of CMP
`restricts the application to small size substrate. The TFT has a rather large
`subthreshold swing of 1.1 V/dec, which is probably attributed to damages at
`the Si/SiO, interface due to CMP. Additionally, contamination at the interface
`from the CMP processis also anticipated.
`
`LG Display Co., Ltd.
`LG Display Co., Ltd.
`Exhibit 1007
`Exhibit 1007
`Page 018
`Page 018
`
`

`

`158
`
`Foly-Si TFTs
`
`
`
`Figure 9. Process flow of inverted, staggered poly-Si TFTs with self-aligned drain and source
`using the CMP method.(After Zhangetal., Ref. 34. © 1996 IEEE.)
`
`3.
`
`DRAIN ENGINEERING
`Electrical characteristics of the poly-Si TFTs have specific concerns:
`high leakage current, kink effects, and hotcarrier effects. Detailed discussions
`of these topics can be foundin Chapter 3 of this book.
`The leakage currentof a poly-
`Si TFT is generally higher than that of
`an a-Si TFT.In orderto apply the poly
`-Si TFTsinto active matrix circuits, the
`anomalousleakage current must be re
`duced. This is because the pixel should
`maintain the charge when the line is not selected,i.e., the TFTsare atoff-state.
`The reduction ofthe
`is also important for SRAM application
`of poly-Si TFTs in terms of the low power consumption during the waiting
`ume. The leakage Current mechanism is explained to be field emission via
`pletion region,*> Grain boundary between
`energy levels inside the energy gap ofthe crystalline
`When it is reverse biased and depleted,i.<.,
`field in the drain dep!si ee cout eis oe ee
`amountof the trap states. The trap
`method does
`Ogenation.** However
`the
`hydrogenation
`net completely remove th
`teen
`the electric fi
`
`ain depleti _-S:Onthe other hand, decrease in
`the high lea
`prewion Tegion is very effective in suppressing
`Kage current,
`
`LG Display Co., Ltd.
`LG Display Co., Ltd.
`Exhibit 1007
`Exhibit 1007
`Page 019
`Page 019
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`

`

`poly-Si TFT Structures
`
`Kink effect is the saturation Current increase d
`electron-hole pairs induced by the high elect;
`contact region.’ The highelectric fieldenki io
`kinetic energy and thermal energy until impactionization ce itaoe
`raise parasitic bipolar action (PBA).*® The impact ionization easie
`are injected into the floating body (base) forcing further electron ine oo
`from the source (emitter) and collected by the drain (collector) This ded
`drain current enhances the impact
`ionization
`,
`sien
`.
`and causes a premature
`breakdown. This effect
`increases the current, which increases the output
`conductance, and hence, powerdissipation in digital circuits. It also reduces
`gain in analogue circuit.
`The impact ionization generated hot-carriers can be injected into the
`gate oxide. This phenomenon produces
`the device degradation. The
`predominant mechanism for device degradation induced by the hot carrier
`injection is formation of interfacestates near the drain.*” The formation ofthe
`interface traps is related to sequential trapping of holes followed by electron
`captures. Prolonged drain bias stress degrades the transfer characteristics. The
`electrical instability is a serious issue for long-term reliability of the circuit.
`Since these effects are induced by the presenceof the intense electric field at
`channel/drain region, many structures engineered at the drain electric field
`have been reported. They are discussed in the following sections.
`
`3.1 Multiple Gates
`The first approach to decrease the drain electric field was the
`introduction of multiple gates in the TFTs,'*“ as shown in Figure 10. By
`dividing the channel into several heavily doped regions connected in series,
`the voltage and field between the source and drain will simply be divided,
`thereby the drain field for each TFT becomes moderate. It has been reported
`that by having two gates, the leakage current can be suppressed by one oe
`of magnitude while the on-current is reduced by a factor of two a to
`the single gate TFT. This is because linear partition of the total potentia gives
`an exponential decrease in the leakage current, which exponentially apie
`with the drain field. A drawback of the multiple gates is that the channe
`width must be increased in order to compensate by the limit on the minimum
`feature size. This increases the TFT’s area, and thus, decreases the aperture
`ratio of the LCDs. The trade-off between the leakage current and TFT area
`often results in selecting of the gate numberof two.
`
`LG Display Co., Ltd.
`LG Display Co., Ltd.
`Exhibit 1007
`Exhibit 1007
`Page 020
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`

`160
`
`Poly-Si TFTs
`
`=eI
`
`
`
`Figure 10. Schematic cross-section of top gate, coplanar poly-Si TFT with multiple gates
`(After Morozumiet al., Ref. 13.