___‘
`
`THIN FILM TRANSISTORS
`
`MATERIALS AND PROCESSES
`
`VOLUME 2: POLYCRYSTALLINE SILICON
`
`THIN EILMMTRIANSISTORS
`
`edited by
`
`YUE KUO
`
`LG Display Co., Ltd.
`Exhibit 1007
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`
`
`
`

`

`
`
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`

`

`
`THIN FILM TRANSISTORS
`
`Materials and Processes
`
`Volume 2
`Polycrystalline Silicon Thin Film
`Transistors
`
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`
`

`

`
`
`THIN FILM TRANSISTORS
`
`Materials and Processes
`
`Volume 2
`
`Polycrystalline Silicon Thin Film
`Transistors
`
`edited by
`
`Yue Kuo
`
`Texas A&M University, USA.
`
`it
`
`KLUWER ACADEMIC PUBLISHERS
`Boston I Dordrecht I New York I London
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`

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`Thin Film Transistors — Materials and Processes
`
`Volume 1 — Polycrystalline Silicon Thin Film Transistors
`Edited by Yue Kuo
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`ISBN — 2 —vol Set 1 402.0 7504 9
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`

`

`CHAPTER FOUR
`Poly—Si TFT Structures
`
`Ryoichi Ishihara
`
`1,
`
`INTRODUCTION
`
`This chapter focuses on structures of poly-Si TPTs which have b
`widely used for active matrix display and static random access merri:en
`(SRAM). First, basic structures of poly—Si TFTs will be addressed. This,
`includes the fundamental configuration of semiconductors,
`insulators, and
`electrodes in the TFI‘s. A wide variety of poly-Si TFT structures have been
`studied so far. Depending on the process (Iow- or high-temperance) and
`application (large or small area flat panel display, or SRAM), a suitable TFT
`structure differs. For each structure, basic advantages and disadvantages,
`process flow, and cost issue will be described.
`
`structures controlling an electric field near
`Secondly, various
`drain/channel junction will be reviewed. The off-current of poly-Si TFTS.
`refined to as leakage current, is generally higher than that of a-Si TFl's due
`letion region and the
`.
`grain oun ary
`S 1
`he d” 1‘ dep
`.
`‘
`to field emission via
`' b
`d
`trap '1”
`i
`tiv
`the poly-Si I‘FI's to ac
`e
`h,
`c
`.
`.
`1
`811 0nductiv1ty of the channel. In order to app y
`by reduction of the
`ma -
`t
`.
`.
`.
`-
`trix Circu1ts, suppressmn of the high leakage cunen auction of the drain
`flame field in the drain region is very important The. F" b
`u
`,,,,,on of
`_Ie1d 18 also effective in improving the circuit reliability y 5 PP
`.
`.
`ctures and
`Sin?“ 10Ilizatiori ofcarriers in the saturation regime- PrOposed SW
`611' electrical characteristics will be introduced-
`_
`estigatflfS
`be reviewed. Many 1""
`-Si TFT
`d at
`improvmg POIY
`
`Finally, novel TFT structures will
`3% I‘e130116“!
`innovative structures aime
`
`h
`
`LG Display Co., Ltd.
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`Exhibit 1007
`Exhibit 1007
`Page 006
`Page 006
`
`

`

`146
`
`P°1y~Si
`
`Mg
`
`rman
`perfo
`'
`'
`
`ess technologies, 511011 as Chemical mecha .
`ce. Advanced proc
`and pulsed-laser crystallization, enablemtc]:
`CMP , silicidation,
`.
`.
`.
`|
`
`technical constraints will be discussed.
`
`2.
`
`BASIC TFT STRUCTURES
`
`2.1
`
`TFT Components
`
`2.1.1
`
`Basic Arrangment of TFT Components
`
`The most important feature of TFTs is that they can be formed on
`insulating materials, which include glass substrates and insulating layers
`isolated from the existing devices below. This feature allows high Optical
`transparency of the device, use of a larger sized substrate than those possible
`with Si wafers,
`and 3D integration of semiconductor devices. The
`conventional TFl‘s consist of three electrodes of source, drain and gate, gate
`insulator, and thin semiconductor layer. These elements can be arranged in
`many ways.
`
`The first major structural distinction in the TFTs is the arrangement of
`the electrodes:
`
`1. Coplanar: The source and drain electrodes are located at the same
`side as the gate electrode.
`
`2' Staggered; The source and drain electrodes are located at the opposite
`“13 to the gate 915“de separated with the semiconductor layer.
`seem? second major distinction of the TFT is the level of the gate
`
`LG Display Co., Ltd.
`’ LG Display 00., Ltd.
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`Page 007
`Page 007
`
`

`

`poly-5i
`
`147
`
`
`
`Figure I. Basic poly-Si TFT structures are shown of (a) top gate, planar; (b) top gate,
`staggered; (c) bottom gate, planar and (d) bottom gate, staggered. The TFTs are n-channel.
`
`2.1.2 Device Isolation
`
`Unlike the bulk MOSFETs, TFTs are electrically isolated from each
`other by forming the island,
`i.e., by completely etching off the thin
`semiconductor layer from the device-nonactive area. This yields a complete
`electrical isolation of the device and increases in the non-TFT area, which is
`limited for most applications.
`
`. 2.1.3
`
`Source and Drain Regions
`
`Poly-Si TFTs need the drain and source regions of a heavrly doped
`POly-Si for their unipolar operation. For n-channel TFTs, _when the pastime
`gate bias is applied to the gate, electrons accumulate ‘at the interface an ‘ cm
`the channel from the source to drain. When the negative gate bias is applied to
`the gate, holes accumulate at the interface to form field-induced pn Junctlons
`between the channel edge and both drain and source regions. The depletion
`regions at source and drain prevent carriers flowmg from both Sides of. the
`channel and the source and drain. In this way, the source and dram regions
`
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`Exhibit 1007
`Page 008
`Page 008
`
`

`

`143
`
`j
`
`Poly-Si TFT,
`
`select the ”carriers. The drain and source regions need to be heavily d
`form ohmic contacts between the electrode and the Si layer,
`
`oped to
`
`2.1.4
`
`Formation of Drain and Source Region
`
`. .The drain and source regions can be fabricated in two Way; (1)
`deposrtion of doped Si layer or (2) introduction into the poly-Si layer.
`-
`The first approach,
`the deposition of the doped Si
`layer, has the
`advantage of doping a large doped area in a simple step. This is the same as
`the fabrication of a-Si TFTs in LCDs, which involves the deposition of
`heavily doped a—Si
`layers1 for the source and drain regions (called ohmic-
`layer). If the doped Si layer is used, the source and drain regions cannot be
`formed just beside the channel. Instead, they are formed atop or below the
`channel region, as shown in Figure 4. For the staggered structure, this means
`that
`the carriers must first cross the channel
`layer vertically,
`then flow
`laterally through the channel, and finally cross vertically through the channel
`layer to the contact region. Since the channel is undoped, and thus, has high
`resistance,
`the vertical current-paths create an extra parasitic resistance.
`Therefore, an advantage of the planar structure over the staggered is that there
`is no such parasitic resistance. The doped poly-Si layer can be formed by an
`in-sr‘i‘u doping process in which dopants are introduced during the deposition
`of the poly-Si. The process, however, may require a high temperature, of
`which glass substrates cannot be tolerant. Recrystallization of the heavily
`doped a-Si
`layer, e.g., by excimer—laser crystallization, can lower the
`formation temperature. It is difficult to fabricate CMOS configuration Wltl'l
`the method of depositing the doped layer, since local deposition of the heavily
`doped regions is very difficult.
`
`In the latter approach, i.e., doping impurity into undopcd poly-Si, the
`. source and drain contacts can be formed just beside the channel region. As In
`the bulk 81' MOSFET, by doping local area, CMOS configuration can also :8
`easily obtained. The classical thermal diffusion of impurity atoms with ih:
`furnace drive-in generally requires a high temperature and thus, resmCtS ‘n
`application to the high temperature substrate. Pulsed-laser irradiation 11:13
`eiflier a solid2 or gaseous3 diffusion source can prevent the thermal damaghcat
`the substrate because of the short pulse duration and ‘ hence short This
`diffusion length. The doping can also be done by ion-irnplantatlttlrll-mg 0
`technique, however, might be difficult over a large area due to the scans uires
`small beam size and hence the low throughput. The dopant activation
`t-l
`'
`lsed-IEISer
`a high temperature, which can be lowered, however, by P”
`LG Display Co., Ltd.
`LG Display Co., Ltd.
`Exhibit1007
`Exhibit 1007
`Page 009
`Page 009
`
`

`

`-
`‘
`Poly Si TFT
`
`Stru
`
`ctures
`
`149
`
`irradiation“ or rapid thermal annealing (RTA). Recently, the development of
`non-mass separated ion-shower doping techniques (hereafter referred to as
`ion~doping) can overcome the problem of ion-implantation. The technique
`uses a large beam size and hence is proper for doping a large area. Also the
`ion-doping lowers the activation temperature of impurity atoms. Detéiled
`discussions of the performance process and related issues are included in
`other chapters of this book.
`
`2.1.5 Top- vs. Bottom-Gate
`
`A fundamental difference in the fabrication process between these
`two structures is that, for the bottom gate structure, a semiconductor layer and
`gate insulator layer can be formed continuously without breaking vacuum. For
`the top gated structure,
`the continuous formation is not possible, since
`semiconductor islands should be patterned before the gate oxide formation
`because the islands have to be electrically isolated from the gates by oxide
`sidewall formation. The bottom gate structure can easily form a clean and
`stable Si/gate insulator interface, while the t0p gate needs extra care when
`cleaning the semiconductor surface. This unique feature of the bottom gate
`structure made it very attractive, especially for a-Si TFTs, as it is generally
`difficult to obtain a clean a-Si/gate insulator (SiN,) interface. The advantage is
`applicable to poly-Si TFTs, as well.
`
`2.1.6 Gate-Drain Self-Alignment
`
`The edges of the gate electrode and the edges of the drain and source
`regions are preferably aligned. If these are separated far from each other, a
`high parasitic resistance will be formed in the silicon between these lines. The
`. parasitic resistance lowers the output current. If these regions are overlapped,
`the extra capacitance associated with the overlap will be created. The
`capacitance will deleteriously affect circuit performance in high—speed
`operation due to the increase in RC delay. In contrast, the self-alignment
`allows one to align automatically the gate edge to the drain and source; hence,
`no parasitic resistance or capacitance is found. This self-alignment structure
`also reduces the devrce Size.
`
`LG Display Co., Ltd.
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`Exhibit 1007
`Exhibit 1007
`Page 010
`Page 010
`
`

`

`150
`
`Poly-Si TFT,
`
`2.2
`
`Top Gate TFTs
`
`Historically, the first FET proposed by Oscar Heil in 19356 alread
`had, in fact, the top gate TFT structure with the tellurium semiconductor filmy
`Trial and error with experiments of the FETs led to the invention of bipolai
`transistors in 1945. FETs remained an oddity until the invention of the Si
`planar process (MOS) in 1960. When the materials and quality of MOSFETS
`were improved, there were intensive studies on TFTs. Many researchers have
`developed various poly-Si formation techni ues, such as direct deposition by
`LPCVD,7 solid phase crystallization (SPC) and grapho-epitaxy,
`that have
`been used to fabricate poly-Si Tli'l‘s.'°'”‘12 At
`that period,
`the top gate
`structure was the most popular structure. This was because the fabrication
`technologies for bulk MOSFETs,
`such as thermal oxidation and ion-
`implantation, could be used. The first production of active-matrix addressed
`LCDs for pocket TV, which appeared in 1984,” used not the a-Si TFTs but
`the top gate poly-Si TFTs with the high temperature process. Since the late
`19805, low temperature poly-Si crystallization methods, such as excimer-laser
`crystallization” or metal
`induced crystallization,”"‘5 have been developed
`which made poly-Si TFTs on large glass substrate feasible. Based on the low-
`temperature process, large sized, driver-into ated LCDs have been in mass
`production using the top gate poly-Si TFTs.l Detailed discussions on the low
`temperature poly-Si formation processes can be found in Chapters 5, 6, 10,
`and 12 of this book.
`
`2.2.1 Coplanar (Self-Aligned)
`
`The top—gate, coplanar TFT structure is most commonly used among
`the poly-Si TFl‘s. As shown in Figure 2, first, the poly-Si layer is formed on
`top of the substrate and then is patterned into islands by photolithography and
`- etching steps. Then, gate oxide and metal
`layers are deposited. After
`patterning the metal into the gate (in some cases, the gate oxide on top of the
`source and drain regions is also removed), impurity ions are doped by “on'
`rnass separated ion-shower doping or ion-implantation. Here, the gate can be
`used as a mask dining doping so that the source and drain regions are. self—
`aligned with reSpect to the channel edge. The self-alignment capability IS the
`most important feature of this structure. The TFT is complete after passiva’tl‘lm
`oxide deposition, contact hole opening and gate metal deposition/pattemlng'
`A possible drawback of the TFT structure is that the Si surface must be
`carefully
`cleaned
`before
`the
`formation of
`the
`gate
`oxide,
`Since
`photohthography and etching steps must be used to form the Si islands.
`LG Display Co., Ltd.
`LG Display Co., Ltd.
`Exhibit 1007
`Exhibit 1007
`Page 011
`Page 011
`
`

`

`
`
`
`.
`_
`.,
`
`
`._
`" 4
`s“
`
`I .
`I
`' fill—@234.
`3.": y: I ‘ '
`.-'"'-I
`
`
`
`_;...-_g '
`:= "
`.-;....
`JL‘:— r7:7- we
`_i-,-
`MESH“ ELEM William
`_r awe-em
`
`
`
`
`
`
`
`
`
`Figure 2. Fabrication process flow for top gate, coplanar poly-Si TF‘I‘s.
`
`2.2.2 Channel—Etched Coplanar (Non Self-Aligned)
`
`The main feature of this type of coplanar TFT,“3'19 schematically
`shown in Figure 3, is the deposited ohmic-layer, instead of the ion-implanted
`region, which acts as the source and drain regions in the coplanar structure.
`First, the undoped a-Si and doped a-Si layer are deposited by PECVD. The
`deped-a-Si on the channel region is then removed. Successively, both the
`undoped- and doped-a—Si are crystallized into the poly-Si at the same time,
`3-3” by excimer-laser crystallization. Then, islands for undoped-poly-Si and,
`at the same time, the source and drain regions are patterned. The gate oxide
`deposition, contact opening, electrodes formation follow afterwards.
`An advantage of this kind of strueture is that the ohmic-layer can be
`635“? deposited over the large area substrate. One of the disadvantages, apart
`from the difficulties in the fabrication of CMOS configuration and the'non
`self-aligned structure,
`is the difficulty in obtaining a high etch SClCCthty
`between the doped and intrinsic silicon films. Although the created damage at
`the channel surface can be removed after the crystallization process,
`the
`thickness variation of the active channel still remains. Furthermore, the thick
`doped-Si/undoped-Si region will not be fully crystallized because the energy
`density of excirner—laser is determined for the thin undoped-Si. This energy
`LG Display Co., Ltd.
`LG Display Co., Ltd.
`Exhibit 1007
`Exhibit 1007
`Page 012
`Page 012
`
`

`

`152
`
`Poly-Si TFTS
`
`' kdoped-Si/undoped Si st k
`.
`nmum and too low for the th10
`.
`.
`ac ed
`'
`.
`deIlSItyl;::1-tc?grc
`small grain size of the doped'POIY'Sl 1"381011 Wlll be
`’
`region.
`gh series resistance.
`expected, and hence, create a hi
`source and drain region can also be fOUned
`h uld be added that the
`'
`.
`.
`either b3 sdifect deposition of doped poly-Si or solid-phase crystallization
`(SPC) of the doped a-Si film.” A high process temperature, however, restricts
`the application.
`
`i
`
`" 5:311: ;-.-
`‘I
`I
`- - ‘ If
`‘j'
`"alumni
`
`-
`
`.
`
`Figure 3. Schematic cross-section of top gate, coplanar poly-Si TFTs with channel etch. (After
`Kuriyama et al., Ref. 18. © 1991 IEEE.) Staggered (Non Self-Aligned)
`
`Top gate, staggered TFT structure is depicted in Figure 4.2] In this
`TFT process, first, a high-temperature resistant metal (such as WSi film) and
`a doped Si layer are deposited and patterned into source and drain regions.
`Then, the a-Si layer is deposited by PECVD and crystallized by excimer—laser
`into poly—Si. The poly-Si layer is then patterned into islands. The TFT is
`complete after gate oxide deposition, contact hole opening, gate metal
`deposition and patterning. The structure provides low leakage current since it
`has avertical offset where the channel and drain overlap; thereby, the drain
`electric field is reduced. One drawback of this structure, apart from the non-
`lsacii'rahgnmcrllt configuration, is that the bottom metal may be damaged during
`crystallization, smce the metal will be heated to a very high temperature.
`Egogfivent the damage, the laser irradiation condition should be carefully
`
` L...
`
`.‘r.
`
`'
`
`
`'Iilliill
`
`ll.
`!
`rill-rm?"
`_
`'- we Arias; m
`
`Swarm
`‘
`Figure 4. Schematic cro
`.
`21‘ © 1989 IEEE)
`ss-sectlon oftop Bate, staggered poly-Si TFTs. (After Sera et al, Ref,
`LG Display Co., Ltd.
`LG Display Co., Ltd.
`Exhibit 1007
`Exhibit 1007
`Page 013
`Page 013
`
`

`

`poly-Si TFT Structures
`
`153
`
`2.2.3
`
`Semi-Staggered (Non Self-Aligned)
`
`In this structure,22‘23 as shown in Figure 5, a heavily doped a-Si is first
`formed and patterned. An intrinsic a-Si is then deposited and recrystallized
`e.g.. by excimer laser. Here,
`impurities in the heavily doped a—Si
`film;
`incorporate throughout the entire undoped Si above it, since both undoped-
`and doped—a-Si are conventionally thin (~50 nm). Thereby, the n+—region can
`be formed adjacent to the channel edge, hence the name, “semi-staggered.”
`This feature lowers the series resistance. Before the poly-Si island formation,
`the gate oxide is deposited without breaking vacuum. Then, both poly—Si and
`gate oxide are patterned into the island. To protect the shortage between poly-
`Si and the gate, an additional gate oxide needs to be deposited. The process is
`complete after gate metal formation, contact opening, and source and drain
`metal formation. In this TFT structure, the poly-Si/gate oxide interface can be
`formed without breaking the vacuum, and hence, a clean interface can be
`obtained. A possible drawback, apart from the non self-alignment structure
`and the requirement of two gate oxides, is that there might be contamination
`and defect formation between the two gate oxides, which will deteriorate the
`device stability.
`
`
`
`1L"
`_'-
`_'I
`I
`an L
`
`'1ng
`.._
`
`
`
`an"
`
`. r
`{1
`m. "I"an:
`
`
`
`Figure 5. Schematic cross-section of top gate, semi-staggered poly-Si TFTs. (After Sekiya et
`3]., Ref. 22. © 1994 IEEE., afier Kohno et al., Ref. 23. © 1995 IEEE.)
`
`‘ 2.3
`
`Bottom Gate TFTs
`
`The bottom gate TFI‘ structure is the most common configuration for
`a-Si TFTs. It is often referred to as the inverted-staggered structure. This is
`because the a—Si film can be deposited immediately after SiN, deposition
`without breaking vacuum. If SiNx film is deposited after the a-Si film, such as
`in the top gate structure, the SiN, process deposition deteriorates the interface,
`since it generally requires a higher deposition temperature and a high plasma
`power. The bottom gate TFT contains a clean a—Si/SiN,
`interface and
`
`LG Display Co., Ltd.
`LG Display Co., Ltd.
`Exhibit 1007
`Exhibit 1007
`Page 014
`Page 014
`
`

`

`154
`
`Poly-Si TFTS
`
`'
`‘
`than the top gate TF1“, Th
`'
`nt larger electron mobility
`.
`-
`.
`ese
`1tIiEtzcllvlt‘iarflEgt:Isairritfielnfl:ebottom-gate TFT structure Widely accepted in a-81 TFT.
`LCD design, despite the unusual upside-down structure.
`In the early stage of the development oLthe low-temperature p01”,
`this structure was also widely studied
`because the Iexcrrner-laser
`TFTs,
`crystallization was taken as an additional process step to the a-Sr TFTs. In this
`sense, the bottom gate poly-Si TFTs are attractlvc because the 3-81 TFT plxels
`and poly-Si TFT drivers can be prepared in a few Simple .steps. Moreover,
`with the bottom gate poly-Si TFTs, the existing production infrastructure and
`the expertise for a-Si TFTs can be utilized. Indeed, the first production of the
`poly-Si TFT driver integrated LCDs with the excimer-laser crystallization
`method was based on the bottom gate TFT structure.25
`
`The bottom gate structure is used also for integrated circuit, mainly by
`SRAM,“ for a number of reasons. The structure allows sharing the gate
`between the bottom MOSFETs and top TFTs. This increases the integration
`density, improves the topography, reduces the number of levels, and thereby
`simplifies fabrication in the sub-micrometer regime. The structure will be also
`indispensable in 3D integration because of interconnection restraint. Detailed
`discussions on the poly-Si TFT applications in VLSI can be found in chapter
`13 of this book.
`
`2.3.1
`
`Inverted-Staggered with Channel Etching (Non Self-Aligned)
`
`The “channel etching"
`e of the invert
`_
`-
`-
`‘
`‘
`ed Staggered P013! 51 TFTS 15
`Show“ in Figure 6. First, a typ
`typically Molybdenum (M0) 0‘
`metal
`layer,
`nd subsequent process steps, is deposited and
`‘ de. After the metal etching step, the gate oxide
`
`LG Display Co., Ltd.
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`Exhibit 1007
`Exhibit 1007
`Page 015
`Page 015
`
`

`

`-
`'TFT Structures
`Poly 3‘
`
`155
`
`because the gate oxide is typically thinner than the heat diffusion length («~st
`mm)” of the excimer-laser crystallization process.
`
`The metal layer also induces a fast heat transfer from Si and thus
`influences
`the
`crystallization
`characteristics.
`In
`the
`cxcimer-laser
`crystallization process, there exists an optimum energy density range Where
`silicon crystallizes with the largest grain size. The optimum energy density
`range for the silicon above the gate metal is higher than the surroundings due
`to the fast heat transfer towards the metal. 0n the other hand, a higher energy
`density will results in a small grain size in the surroundings. Furthermore,
`even with the optimum energy density range, the fast heat transfer towards the
`gate metal results in the fast grain growth, and hence, deterioration of crystal
`quality. With such conditions, the grain size and grain quality across the poly—
`Si will be non-uniform. In order to obtain a uniform distribution, one must use
`a lowered energy density, with which only the medium size of grains can be
`obtained. Consequently, the field effect mobility of the bottom gate poly-Si
`TFT is generally smaller than that of the top—gate structure.
`
`
`
`Figure 6. Schematic cross-section of the inverted staggered poly-Si 'l‘F‘l‘ structure with channel
`etch process.
`
`2-3-2
`
`Inverted-Staggered with Channel Protective Film (Non Self-
`Aligned)
`
`the over etching of the
`In this. type of inverted staggered TFTs,
`channel poly-Si. ls prevented by a protective film ("etch-stopper”) on it.29 This
`TFT structure 15 Often referred to as (rt-layer type inverted staggered. The
`process flgw 1s Show“ 1“ Figure 7. First, the gate electrode is formed by a
`metal, typically M0 01' Ta, which can stand the subsequent process steps.
`LG Display Co., Ltd.
`LG Display Co., Ltd.
`Exhibit 1007
`Exhibit 1007
`Page 016
`Page 016
`
`

`

`156
`
`Poly—Si TFTs
`
`Then, gate oxide and a-Si layers are (1.313051:th by PEQVD—vnthout breéking
`the vacuum. The a-Si is then recrystallized into-poly-Si,-e.g., by the excnner-
`laser crystallization method. Either a SiOz or SIN,‘ film is then deposned and
`patterned into small islands, which defines the channel region-1:0 The channel
`protective film can alternatively be a highly reSIStive a-Si.
`_A]so,
`theSe
`channel protective films can be formed before the laser crystallization. The
`contact hole to the gate is then opened. A doped a—Si film is deposited ova
`the structure and is crystallized by excimer-laser irradiation. The source and
`drain can be formed also by ion-implantation using a photoresist mask. The
`process is complete after the metal deposition and etching. The n+ layer and
`the intrinsic poly-Si can be simultaneously etched using the same mask.
`Because of the presence of the channel protection layer,
`the last 11+ and
`intrinsicpoly-Si layer can be extensively over—etched. Therefore, thickness of
`the active Si layer can be set as an optimum value for the poly-Si TFTs.
`
` Law mailman
`
`Initiator «mien
`
`
`
`LG Display Co., Ltd.
`LG Display Co., Ltd.
`Exhibit 1007
`Exhibit 1007
`Page 017
`Page 017
`
`

`

`beam, as shown ’
`the back illumination requires a U1?
`It should be noted that
`Figure 8.
`transparent glass 'wafer and an Opaque metal. The selection of glass and
`masking metal Will be limited by their material properties. The proximity
`effect in performing the backside lithography through a thick substrate also
`limits the accuracy of the pattern transfer from the gate pattern.
`
`
`
`Figure 8. Schematic cross-section of the inverted, staggered poly-Si TFT with self-aligned
`LDD. (After Hayashi et al., Ref. 33. © 1995 IEEE.)
`
`2.3.4
`
`Inverted-Staggered with CMP (Self-Aligned)
`
`Another self-aligned inverted-stagger structure is shown in Figure 9.34
`After gate metal
`formation and gate insulator deposition, a-Si
`film is
`deposited. The a—Si layer is heavily doped by boron ion implantation. At this
`time, lightly doped regions are formed adjacent to the gate because the surface
`0f the a-Si layer is tilted there. The wafer is then chemical mechanical
`901$th (CMP) down to the gate insulator, which acts as a stopper. Thin a-Si
`is subsequently deposited and recrystallized by methods, such as the nickel
`'0‘“)
`induced crystallization method. The metal-induced crystalliaanon
`process can be found in Chapter 6 of this book. Finally, the fabrication IS
`cOmplete after several processes, such as contact opening and metalhzatron.
`With this structure, the self-aligned lightly doped drain region is achieved.
`There are a number of issues to be solved in this structure. The use Of CMP
`reStil‘iots the application to small size substrate. The TFT has a rather large
`subthreshold swing of 1.1 V/dec, which is probably attributed to damages at
`the Si/SiOz interface due to CMP. Additionally, contamination at the interface
`from the CMP process is also anticipated-
`
`LG Display Co., Ltd.
`LG Display Co., Ltd.
`Exhibit 1007
`Exhibit 1007
`Page 018
`Page 018
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`

`

`158
`
`Poly-Si "1‘st
`
`
`
`Figure 9. Process flow of inverted, staggered poly-Si TFTs with self-aligned drain and source
`using the CMP method. (After Zhang et 31., Ref. 34. © 1996 IEEE.)
`
`3.
`
`DRAIN ENGINEERING
`
`Electrical characteristics of the poly-Si TFTs have specific concerns:
`‘
`high leakage current, kink effects, and hot carrier effects. Detailed discussions
`of these top1cs can be found in Chapter 3 of this book.
`
`generally higher than that of
`-Si TFTs into active matrix ClI'CLlltS the
`
`LG Display Co., Ltd.
`LG Display Co., Ltd.
`Exhibit 1007
`Exhibit 1007
`Page 019
`Page 019
`
`

`

`Poly-Si TFT Structures
`
`and causes a premature
`,
`.
`breakdown. Thls effect 1ncreases the current, which increases the output
`conductance, and hence, power dissipation in digital circuits. It also reduces
`gain in analogue Cll‘cult.
`
`The impact ionization generated hot-carriers can be injected into the
`gate oxide. This phenomenon produces
`the device degradation. The
`predominant mechanism for device degradation induced by the hot carrier
`injection is formation of interface states near the drain.39 The formation of the
`interface traps is related to sequential trapping of holes followed by electron
`captures. Prolonged drain bias stress degrades the transfer characteristics. The
`electrical instability is a serious issue for long-term reliability of the circuit.
`Since these effects are induced by the presence of the intense electric field at
`channel/drain region, many structures engineered at the drain electric field
`have been reported. They are discussed in the following sections.
`
`3.1 Multiple Gates
`
`The first approach to decrease the drain electric field was the
`introduction of multiple gates in the TFTs,'3‘40 as shown in Figure 10. 'By
`dividing the channel into several heavily doped regions connected in series,
`the voltage and field between the source and drain Will Simply be dmdeglé
`.thereby the drain field for each TFT becomes moderate. It has been reported
`that by having two gates, the leakage current can be suppressed by one orc'lder
`0f magnitude while the on—current is reduced by a factor of two compare to
`the single gate TFT, This is because linear partition of the total potentia gives
`an exponential decrease in the leakage current, which exponentially increases;
`With the drain field. A drawback of the multiple gates is that the channe
`width must be increased in order to compensate by the llmlt on the l'l’llI'llmum
`feature size. This increases the TFT’s area, and thus, decreases the aperture
`ratio of the LCDs. The trade-off between the leakage current and TFT area
`often results in selecting of the gate number of two.
`
`LG Display Co., Ltd.
`LG Display Co., Ltd.
`Exhibit 1007
`Exhibit 1007
`Page 020
`Page 020
`
`

`

`160
`
`POIY-Si TFTS
`
`J lllllllliiliflllllflllléflllllllllllllmllllllmL
`
`
`
`
`Figure :0. Schematic cross-section of top gate, coplanar poly-Si TFT with mUltiple gates.
`(Atter Morozumi et al., Ref. I3. © 1983 SID.)
`
`3.2
`
`Offset Gate
`
`The drain electric field can be reduced if the distance between the two
`edges of the channel and the drain increases, as shown in Figure 11. An
`experiment“l showed that, with an offset length of 5 pm, the leakage current
`could be reduced by about one decade in magnitude compare to that of the
`conventional TFT structure. However, the on-current was also reduced by the
`same order due to the high parasitic resistance,
`i.e., current pinching
`phenomenon. This results in almost the same value of the on/off current ratio.
`The ratio can be improved by shortening the offset length; however, this
`would lead to a severe alignment requirement. An additional lithography step
`is required to define the offset region. This raises two major drawbacks. One
`IS the increased process complexity, and the other is the variation in the
`channel length due to the difficulty in precise control of the offset length.
`metal (£116 ox1dation layer, such as A1203 formed at the sidewall of the gate
`by the “1.131311 solve the latter problem,42 since the offset length is determined
`by hot
`FSS 0f the 4oxidized layer. The offset length can also be controlled
`p
`O‘TCSISt reflow. Photoresist formed on top of the gate can be reflown
`
`LG Display Co., Ltd.
`LG Display Co., Ltd.
`Exhibit 1007
`Exhibit 1007
`Page 021
`Page 021
`
`

`

`TFT Structures
`
`—Simy
`
`161
`
`
`JIIMHHIMHIIMWH
`
`.
`
`
`
`'
`re ii. Schematic cross-section of top gate, coplanar
`:fika et al., Ref. 41. c 1988 15135.)
`
`.
`
`.- GM"
`
`
`
`
`
`1 -Si TFT '
`p° 3’
`“"“1 W8“ sate- (After
`
`3.3
`
`Lightly Doped Drain (LDD)
`
`The current pinching phenomenon in the offset gate structure can be
`improved by employing an n'-region between the channel and drain,
`i.e.,
`lightly doping the offset region as shown in Figure 12.“4 The LDD region can
`be formed by, for example, an additional implantation or ion-doping“ of
`impurity atoms with a low dosage. Altematively, the LDD region can be
`formed by doping through a thick insulating layer, such as SiOz or Tan,“
`extending from the gate edge. LDD region can be formed together with
`doping for the source and drain, since the insulating layer lowers the
`acceleration voltage and hence the doping concentration.
`
`
`
`Figure I2. Schematic cross-section of top gate, coplanar poly-Si TF'I‘ with lightly doped drain
`region. (Afier Nakazawa et 81., Ref. 44. © 1990 SID.)
`
`Since the parasitic resistance effect is inversely proportional to the
`LDD doping concentration Nmn while the drain field decreases for decreasing
`the NLDD:
`the choice of Nmo is determined on the actual application
`r'3Cluiretnent of the TFT. As shown in Figure 13, with a concentration of about
`1x101? 01114,
`the TFT’s on/ofi' current ratio is improved by one ordcifif
`magnitude compared